JP2003075485A - Wiring capacity measurement circuit and method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wiring capacity measurement circuit for reducing circuit scale and costs and to provide a simple wiring capacity measurement method. SOLUTION: The wiring capacity measurement circuit comprises a first unloaded clocked inverter CIV1, a second clocked inverter CIV2 where an input node is shared with the input node of the first clocked inverter CIV1 and wiring 3 is connected to an output node, a delay circuit 12 that delays a pulse signal SV to be supplied to a common input node by specific time for supplying to the clock gates of the first and second clocked inverters CIV1 and CIV2, and ammeters A1 and A2 for measuring the level of a current that flows to the first and second clocked inverters CIV1 and CIV2 when a pulse signal SV is supplied to the common input node.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and circuit for measuring wiring capacitance.

[0002]

2. Description of the Related Art In general, with the miniaturization of semiconductor devices, it has become important to accurately grasp the wiring capacitance. Conventionally, various circuits and methods for measuring the wiring capacitance have been devised. There is.

FIG. 6 is a circuit diagram showing the structure of a conventional wiring capacitance measuring circuit 1. As shown in FIG. 6, the conventional wiring capacitance measuring circuit 1 has a P-channel MOS transistor P
11 and an N-channel MOS transistor N12, an unloaded inverter, and a P-channel MOS transistor P
21 and an N-channel MOS transistor N22, and an inverter to which the wiring 3 is connected at the output node,
It further includes an ammeter A1 for measuring the value of the current flowing through P channel MOS transistor P11 and an ammeter A2 for measuring the value of the current flowing through wiring 3 through P channel MOS transistor P21.

Here, for example, the pulse signal SV1 shown in FIG. 7A is supplied to the gates of the two P-channel MOS transistors P11 and P21, and the gates of the two N-channel MOS transistors N12 and N22 are For example, the pulse signal SV2 shown in FIG. 7B is supplied. The period during which the pulse signal SV2 is at the high level is a part of the period between the time T1 and the time T2 when the pulse signal SV1 is at the high level, and the shoot-through current generated in the inverter is suppressed.

Then, the wiring capacitance measuring circuit 1 as described above
With respect to the pulse signal SV1 and the pulse signal SV2
Are supplied at frequency F. At this time, when the power supply voltage supplied to the inverter is V and the average current values measured by the ammeters A1 and A2 are I1 and I2, respectively, the wiring 3
The capacity C of is calculated by calculating (I1-I2) / VF.

However, when the wiring capacitance is measured as described above, two pulse signals SV1 and SV are externally applied.
Since it is necessary to supply V2 to the wiring capacitance measuring circuit 1,
A circuit for generating these two pulse signals SV1 and SV2 and supplying them to the wiring capacitance measuring circuit 1 is required. As a result, in the conventional measurement of the wiring capacitance, there is a problem that the scale and cost of the required measuring device increase.

Next, a conventional method for calculating the coupling capacitance (Cc) between wirings will be described with reference to FIG.

First, as shown in FIG. 8A, the first wiring 25 and the second wiring 27 are short-circuited by a jumper 29, and the first and second wirings 25 and 27 and the ground node 23 are connected. The capacity (Ct) between and is measured.

Next, as shown in FIG. 8B, the short circuit between the first wiring 25 and the second wiring 27 is released, the first wiring 25 is grounded, and the second wiring is grounded. The capacitance (C1) between 27 and the first wiring 25 is measured.

Then, as shown in FIG. 8C, the short circuit between the first wiring 25 and the ground node 23 is released, and the second wiring 27 is grounded, so that the first wiring 25 and the second wiring 25 are grounded. The capacitance (C2) between the wiring 27 and the (C1 + C2
Calculate the coupling capacitance Cc by calculating -Ct) / 2.

However, in the conventional method as described above, in order to calculate the coupling capacity, the three capacities (Ct, Ct,
C1 and C2) have to be measured separately, which is complicated and requires a complicated circuit to measure the capacitance.

[0012]

The present invention has been made to solve the above problems, and provides a wiring capacitance measuring circuit and a simple wiring capacitance measuring method which can reduce the circuit scale and cost. The purpose is to do.

[0013]

SUMMARY OF THE INVENTION An object of the present invention is to provide a first clocked inverter which is unloaded, an input node of which is shared with an input node of the first clocked inverter, and an output node of which is wired. A second clocked inverter connected to, and a delay means for delaying a pulse signal supplied to a common input node for a predetermined time, and supplying the delayed clock signal to the clocked gates of the first and second clocked inverters, A wiring capacitance measuring circuit comprising: current measuring means for measuring the magnitude of the current flowing through each of the first and second clocked inverters when a pulse signal is supplied to a common input node. It is achieved by providing.

According to such means, the capacitance of the wiring can be easily calculated from the magnitudes of the currents flowing through the first and second clocked inverters measured by the current measuring means. Also, an object of the present invention is to connect only one of two facing wirings to a ground node and to measure a first capacitance (Ca) made by the other wiring with respect to the ground node, and two wirings. Is set to a floating state, and the second capacitance (Cb) made by the other wiring with respect to the ground node is measured, and (Ca · (Ca-Cb)) ^{1 /} based on the first and second capacitances. ²
By calculating a coupling capacitance between two wirings.

By such means, it is possible to easily obtain the coupling capacitance between the wirings facing each other.

By calculating the difference between the first capacitance (Ca) and the coupling capacitance, the ground capacitance of the other wiring can be easily calculated.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. The same reference numerals in the drawings indicate the same or corresponding parts. [First Embodiment] FIG. 1 is a circuit diagram showing a configuration of a wiring capacitance measuring circuit 10 according to a first embodiment of the present invention. As shown in FIG. 1, in the wiring capacitance measuring circuit 10 according to the first embodiment, P-channel MOS transistors P11 and P12 and N-channel MOS transistors N11 and N12 are connected in series between a power supply voltage node and a ground node. The P-channel MOS transistor P is connected between the clocked inverter CIV1 and the power supply voltage node and the ground node.
21, P22 and N-channel MOS transistor N2
Clocked inverter CI in which 1 and N22 are connected in series
V2 and.

Here, the power supply voltage node and the P channel MO
An ammeter A1 is connected between the S-transistor P12 and the S-transistor P12 to connect the power-supply voltage node and the P-channel MOS transistor P
An ammeter A2 is connected to the line 22. The wiring 3 is connected to the drain of the P-channel MOS transistor P21.

The wiring capacitance measuring circuit 10 includes a signal line 11
And a delay circuit 12 connected to the signal line 11,
The gates of the channel MOS transistors P11 and P21 and the N channel MOS transistors N12 and N22 are both connected to the signal line 11, and the P channel MOS transistors P12 and P22 and the N channel MOS transistor N1.
The gates of 1 and N21 are both connected to the delay circuit 12.

The operation of the wiring capacitance measuring circuit 10 according to the first embodiment having the above structure will be described below. First, the pulse signal SV shown in FIG. 2A is supplied to the signal line 11 at the frequency F. At this time, the delay circuit 12 delays the pulse signal SV, and the delay circuit 12 shown in FIG.
The delayed pulse signal SVD shown in is generated. The delay amount by the delay circuit 12 is set to a period T2 shorter than the period in which the pulse signal SV is at high level.

As a result, during the period T1 shown in FIG. 2, since the pulse signal SV and the delayed pulse signal SVD are both at the low level (L), the N-channel MOS transistors N11, N12, N21, N22 are all turned off. , P-channel MOS transistors P11, P12, P
21 and P22 are both turned on. Thus, in the period T1, charge is supplied from the power supply voltage node having the voltage V to the wiring 3.

Next, in the period T2 shown in FIG. 2, the pulse signal SV becomes high level (H) and the delayed pulse signal SVD maintains the low level, so that the P-channel MOS transistors P11 and P21 are turned off. , N-channel MOS transistors N12 and N22 are turned on.

In the period T3 shown in FIG. 2, the delay pulse signal SVD is also at high level, so P
The channel MOS transistors P12 and P22 are turned off and the N channel MOS transistors N11 and N21 are turned off.
Turns on. At this time, the electric charge charged in the wiring 3 is discharged to the ground node.

In the period T4 shown in FIG. 2, the pulse signal SV becomes low level (L) and the delayed pulse signal SVD maintains high level, so that the N-channel MOS transistors N12 and N22 are turned off, and at the same time, The P channel MOS transistors P11 and P21 are turned on.

In the period T5 shown in FIG. 2, the delay pulse signal SVD also becomes low level, so that the N-channel MOS transistors N11 and N21 are turned off and the P-channel MOS transistors P12 and P22 are turned on. Therefore, in the period T5, the period T
4 P-channel MOS transistors P1 as in 1
1, P12, P21, P22 are turned on, and the wiring 3 is charged again with the voltage V.

As described above, when the pulse signal SV having the frequency F is supplied to the signal line 11, the above operation is repeated F times in one second. Then, in such an operation, assuming that the average current values measured by the ammeters A1 and A2 are I1 and I2, respectively, the capacitance of the wiring 3 is (I1-
It is calculated by calculating I2) / VF.

The wiring capacitance measuring circuit 1 shown in FIG.
0, P-channel MOS transistors P11, P12 and N-channel MOS transistor N1 connected in series
1, N12 and P-channel MOS transistor P21,
P22 and N-channel MOS transistors N21, N2
In 2, the generation of a through current is avoided.

As described above, according to the wiring capacitance measuring circuit 10 according to the first embodiment of the present invention, one type of pulse signal SV is used.
Since the capacitance of the wiring 3 can be measured by supplying the signal to the signal line 11, a circuit that generates one kind of pulse signal SV is sufficient to measure the wiring capacitance.
The scale and cost of the device for measuring the wiring capacitance can be reduced. [Second Embodiment] FIGS. 3 and 4 show a second embodiment of the present invention.
FIG. 6 is a diagram for explaining a wiring capacitance measuring method according to the present invention. A method of measuring the ground capacitance C10 of the wirings 21 and 22 and the coupling capacitance C20 of the wirings 21 and 22 will be described below.

First, the switch SW shown in FIG. 3 is turned on to connect the wiring 22 and the ground node 23, and the capacitance (Ca) of the wiring 21 is measured using the method according to the first embodiment. . At this time, the capacitance Ca of the wiring 21 is Ca = C10
+ C20 ... Represented by formula (1).

Next, as shown in FIG. 4, the switch SW is turned off and the capacitance (Cb) of the wiring 21 is measured. At this time, when the switch SW is turned off, the wiring 22 is brought into a floating state. Therefore, the capacitance formed by the wirings 21 and 22 is the coupling capacitance C20 between the wirings 21 and 22 and the two wirings 2.
This is a combined capacity with the ground capacity C10 of 1 and 22. Therefore, the above capacity (Cb) is Cb = C10 + C10 · C20
/ (C10 + C20) ... It is represented by Formula (2).

From the above, the coupling capacitance C20 is (Ca (Ca-Cb) ^1/2 ) according to the above equations (1) and (2).
Therefore, by measuring the capacitance (Ca) and the capacitance (Cb) as described above, the coupling capacitance C20 between the wirings can be obtained.
Can be calculated. The ground capacity C10 can also be calculated by calculating the difference between the measured capacity Ca and the calculated coupling capacity C20.

The wiring capacitance measuring method according to the second embodiment can be easily realized by using, for example, the wiring capacitance measuring circuit 10 according to the first embodiment. That is, as shown in FIG. 5, the wiring capacitance measuring circuit 10 is connected to the wiring 21, and the switch SW formed of an N-channel MOS transistor is connected between the wiring 22 and the ground node 23, and the first embodiment described above is adopted. The capacity (Ca) and the capacity (Cb) can be easily measured by executing the method described in (1).

More specifically, the level of the signal supplied to the gate of the N-channel MOS transistor is set to high level (H) or low level (L) to connect or disconnect the wiring 22 and the ground node 23. , The pulse signal SV is supplied to the wiring capacitance measuring circuit 10.

As described above, according to the wiring capacitance measuring method according to the second embodiment of the present invention, since the coupling capacitance between adjacent wirings can be easily obtained, the capacitance between wirings can be accurately measured in the design environment of the semiconductor device. It can be reflected well and the crosstalk delay and the amount of coupling noise can be accurately estimated.

Further, since it becomes possible to estimate the malfunction of the circuit at the designing stage of the semiconductor device, the number of trial manufactures can be reduced and a high quality semiconductor device can be obtained in a short period of time.

[0036]

According to the wiring capacitance measuring circuit of the present invention, the wiring capacitance can be easily calculated based on the magnitudes of the currents flowing through the first and second clocked inverters measured by the current measuring means. Therefore, the scale and cost of the circuit required for measuring the wiring capacitance can be reduced.

Further, according to the wiring capacitance measuring method of the present invention, since the coupling capacitance between the opposing wirings can be easily obtained, a highly accurate design considering the capacitance can be easily realized. .

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a wiring capacitance measuring circuit according to a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the wiring capacitance measuring circuit shown in FIG.

FIG. 3 is a first diagram illustrating a wiring capacitance measuring method according to a second embodiment of the present invention.

FIG. 4 is a second diagram illustrating a wiring capacitance measuring method according to a second embodiment of the present invention.

FIG. 5 is a diagram showing a configuration example for realizing a wiring capacitance measuring method according to a second embodiment of the present invention.

FIG. 6 is a circuit diagram showing a configuration of a conventional wiring capacitance measuring circuit.

7 is a timing chart explaining the operation of the wiring capacitance measuring circuit shown in FIG.

FIG. 8 is a diagram illustrating a conventional wiring capacitance measuring method.

[Explanation of symbols]

1,10 wiring capacitance measuring circuit, 3,21,22 wiring,
11 signal lines, 12 delay circuits, 23 ground nodes, 2
5 first wiring, 27 second wiring, 29 jumper,
A1, A2 ammeter, P11, P12, P21, P22
P-channel MOS transistor, N11, N12, N
21, N22 N-channel MOS transistor, CIV
1, CIV2 Clocked inverter, C10 ground capacitance, C20 coupling capacitance, SW switch.

Claims (3)

[Claims] 1. A wiring capacitance measuring circuit for measuring the capacitance of a wiring, wherein a first clocked inverter that is not loaded and an input node are shared with an input node of the first clocked inverter. The second clocked inverter having the wiring connected to the output node and the pulse signal supplied to the common input node are delayed for a predetermined time, and the first and second clocked inverters Delay means for supplying the clocked gate; and current measuring means for measuring the magnitude of the current flowing through each of the first and second clocked inverters when the pulse signal is supplied to the common input node. A wiring capacitance measuring circuit comprising: 2. A method of measuring a wiring capacitance, wherein only one of two facing wirings is connected to a ground node, and the other wiring has a first capacitance (Ca) with respect to the ground node. And a second capacitance (C) formed by the other wiring with respect to the ground node, with the two wirings in a floating state.
b), and (Ca · (Ca-C) based on the first and second capacities.
b)) calculating a coupling capacitance between the two wirings by calculating ^1/2 , and a wiring capacitance measuring method. 3. The wiring capacitance measuring method according to claim 2, further comprising calculating a ground capacitance of the other wiring by calculating a difference between the first capacitance (Ca) and the coupling capacitance.