JP2003072146A - Image writing unit and imaging apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a high quality image even in the case of divided exposure to a photosensitive layer of a photosensitive member by a plurality of light emitting element array units. SOLUTION: An image writing unit comprises a plurality of LED heads (light emitting element array units) 503 disposed zigzag along the axis direction of a photosensitive member (main scanning direction). An LED writing controlling circuit 501 transmits image data (image information) to the LED heads 503 while dividing the same for each LED head 503 and lagging the time for a focusing position in the photosensitive member rotation direction. At the time, according to the temperature detected by a thermistor (temperature detecting means) provided in the inside of or in the vicinity of each LED head 503, the light emitting amount of either one or both of two light emitting elements disposed at the joint of the LED heads 503 corresponding to a part of or the entirety of an image data dividing position is corrected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plurality of light emitting elements (for example, LEs) for writing image information on a photoconductor.
D) is a plurality of light emitting element array units arranged in an array at a predetermined density in the main scanning direction orthogonal to the sub-scanning direction, which is the rotation direction of the photoconductor, are arranged in a staggered pattern in the main scanning direction to form an image. An image writing device provided with division transfer control means for dividing and transferring information for each light emitting element array unit,
And an image forming apparatus using the same.

[0002]

2. Description of the Related Art For example, in an LED printer, a plurality of LEDs (light emitting elements) as a light emitting element array unit (recording head) are arranged at a predetermined density in a main scanning direction which is orthogonal to a sub-scanning direction in which a photoconductor is rotated. It is equipped with an image writing device that uses one-dimensional LED heads arranged in an array.
LE according to the signal (image information) corresponding to the written image
The light emission of each LED of the D head is controlled, and the light information is imaged and projected on the photoconductor to write an image (electrostatic latent image). Such an LED printer has high reliability because it does not have a moving part such as the polygon mirror used in a laser printer. Further, in the case of a wide-width machine requiring a large size print output, an optical space for scanning the light beam in the main scanning direction is not necessary, and the LED array and the optical element such as the Selfoc lens are integrated. By arranging the LED head, the size of the entire device can be reduced, so that the laser printer has been replaced.

A laser printer emits (turns on) one light source (laser diode) with an output of about 10 mW.
While the light beam is scanned by the polygon mirror and the fθ lens, the LED printer is
A plurality of LEDs are arranged in the main scanning direction for each pixel, and a current of several mA to 10 mA is applied to each LED to emit light. Therefore, as the size of the printer or copier becomes larger, more LEDs and driver ICs are used, the production yield is reduced, the unit becomes longer, and the precision of parts is increased in order to maintain the writing beam alignment precision. It needs to be improved, and the unit price of parts is much higher than that of small printers and copiers.

Therefore, there has been proposed a large-sized machine in which a plurality of LED heads for a low-priced small printer or a copying machine are arranged in the main scanning direction. For example, JP-A-10
In the digital copying machine described in Japanese Patent Publication No. 86438,
The exposing means for exposing the surface of the photoconductor to form an electrostatic latent image is constituted by a plurality of LED heads arranged along the axis of the photoconductor, and the axial direction of the photoconductor (main scanning direction)
The maximum photosensitivity width can be divided and exposed by each LED head.

[0005]

In such a digital copying machine, in order to expose a photosensitive member having a photosensitive layer of A0 width (maximum width), for example, a plurality of LED heads for A3 width are used as the photosensitive member. It suffices to arrange them in a zigzag pattern along the axis and separately expose the photosensitive layer of A0 width of the photosensitive member by the respective LED heads, but in JP-A-10-86438,
No specific control for the divided exposure is mentioned, and it cannot be said that a high-quality image can be obtained.

Therefore, the present applicant did not previously configure the image writing device (writing device) with one light emitting element array unit (light emitting element array unit for wide width at high cost), but with a photoconductor. A plurality of light emitting element array units arranged in a zigzag pattern along the axis direction (main scanning direction) of (light emitting element array unit of small width and low cost)
There is proposed an image forming apparatus which is configured by the above and divides the image information to be transferred to each light emitting element array unit into each light emitting element array unit by the division control means (see Japanese Patent Application No. 2001-83198).

According to such an image forming apparatus, it is possible to obtain a high quality image even by the division exposure of the photosensitive layer to the photosensitive layer by the plurality of light emitting element array units. However, the unevenness of the light amount caused by the mechanical positional deviation of the joints of the light emitting element array units corresponding to the division position of the image information in the main scanning direction, especially the unevenness of the light amount due to the temperature change is not taken into consideration. I couldn't say that I could get the image reliably. The present invention has been made in view of the above problems, and ensures that a high-quality image can be surely obtained even by the divided exposure of the photoconductor to the photosensitive layer by the plurality of light emitting element array units described above. The purpose is to

[0008]

SUMMARY OF THE INVENTION According to the present invention, a plurality of light emitting elements for writing image information on a photosensitive member have a predetermined density in a main scanning direction which is orthogonal to a sub scanning direction which is a rotating direction of the photosensitive member. An image having division transfer control means for arranging a plurality of light emitting element array units arranged in an array in a zigzag pattern in the main scanning direction and dividing and transferring the image information for each light emitting element array unit. The writing device and the image forming apparatus using the writing device are characterized by the following in order to achieve the above object. In the image writing apparatus according to the invention of claim 1, temperature detecting means is provided inside or near each of the light emitting element array units, and the image information by the division transfer control means is transferred in accordance with the temperature detected by the temperature detecting means. A light amount correction means for correcting the emitted light amount of one or both of the two light emitting elements located at the joints of the light emitting element array units corresponding to some or all of the division positions is provided.

An image writing apparatus according to a second aspect of the present invention is the image writing apparatus according to the first aspect, further comprising:
This is a means for correcting the amount of emitted light by controlling the light emission time of one or both of the two light emitting elements. An image writing apparatus according to a third aspect of the present invention is the image writing apparatus according to the first aspect, wherein the light amount correction means controls the amount of current flowing through one or both of the two light emitting elements. This is a means for correcting the amount of emitted light. An image forming apparatus according to a fourth aspect of the present invention includes the image writing apparatus according to any of the first to third aspects, and the image writing apparatus is used to perform image formation.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be specifically described below with reference to the drawings. First, an outline of a digital copying machine which is an image forming apparatus using an image writing apparatus embodying the present invention will be described with reference to FIG. Figure 1
1 is a block diagram showing a configuration example of a digital copying machine embodying the present invention.

In this digital copying machine, an image reading device 100 as an image reading means for reading an image of a document and an image information storage device as a storage means for storing image data (digital image information) read by the image reading device 100. A copying machine main body 200 including a printing apparatus 300 and a printer apparatus 500 that executes a series of processes for printing (copying) image data stored in the image information storage device 300 as a visible image on a transfer paper, and various information is input. The operating device 400 is provided.

Next, the image reading apparatus 100 of FIG. 1 will be described with reference to FIG. FIG. 2 shows the image reading apparatus 100.
It is a schematic block diagram which shows an example of the mechanism part. When the operator inserts a document through the insertion opening of the image reading apparatus 100, the document is conveyed on the upper surface of the contact glass 2 according to the rotation of the roller 1. The fluorescent lamp 4 is attached to the document being conveyed.
Is emitted, and the reflected light is imaged through a lens 5 on a CCD line image sensor (hereinafter simply referred to as “CCD”) 6 which is an image sensor (photoelectric conversion element), and an image of a document is read. .

The reflected light from the original image formed on the CCD 6 is converted into an analog image signal there and inputted to the image amplification circuit 101 of FIG. 1, where it is amplified and synchronized with the clock signal from the synchronization control circuit 105. And output. A
The / D conversion circuit 102 converts the analog image signal amplified by the image amplification circuit 101 into a multivalued digital image signal (digital image information) for each pixel. The shading correction circuit 103 subjects the digital image information converted by the A / D conversion circuit 102 to processing for correcting distortion due to uneven light amount, dirt on the contact glass 2, uneven sensitivity of the CCD 6, and the like.

The corrected digital image information is subjected to predetermined image processing by the image processing circuit 104 and output to the image information storage device 300 as digital recorded image information.
It is written in the image memory unit (page memory) 301.
Further, the digital recording image information (image data) written in the image memory unit 301 is appropriately read and output to the digital writing device (image writing device) 506 of the printer device 500, and the LED writing control circuit 501. And a plurality of LEDs via the LED head control circuit 502
It is converted into infrared light by the head 503. The system controller 302 controls writing and reading of digitally recorded image information to and from the image memory unit 301.

Next, the copying machine main body 200 of FIG. 1 will be described with reference to FIG. FIG. 3 is a schematic configuration diagram showing an example of a mechanical section of the copying machine main body 200. This copier body 2
In 00, reference numeral 26 is a charging device, which drives the photosensitive drum 25 rotated by a main motor (not shown) to -850V.
It is called a scorotron charger with a grid that charges the surface uniformly. 503 is a plurality of LEDs
A plurality of one-dimensional LED heads (light-emitting element array units) in which (light-emitting elements) are arranged in an array at a predetermined density in the main scanning direction, and each infrared light passes through an SLA (selfoc lens array). And is irradiated onto the photosensitive drum 25.

An LED writing control circuit 501 shown in FIG. 1 which will be described later.
When the light emission (lighting) control of the plurality of LED heads 503 is performed according to the digital recording image information read from the image memory unit 301, and the light is applied to the photoconductor drum 25, the photoconductive phenomenon occurs. The charges on the surface of the photoconductor flow to the ground and disappear. Here, in each LED head 503,
The LED corresponding to the portion of the original image with low image density (the binary signal is the non-recording level) is kept from emitting light, and the LED corresponding to the portion of the original with the high image density (the binary signal is the recording level) is emitted. . As a result, the photosensitive drum 2
The infrared light non-irradiating portion of No. 5 has a potential of −850 V, and the infrared light irradiating portion has a potential of about −100 V, and an electrostatic latent image corresponding to the light and shade of the image is formed. This electrostatic latent image is developed by the developing unit 27. That is, the developing unit 27
The toner inside is negatively charged by stirring, and is -600.
Since the developing bias of V is applied, the toner adheres only to the infrared light irradiation portion.

On the other hand, in the main body 200 of the copying machine, the transfer paper 11 (11a, 11b, 11) wound in a roll shape, respectively.
c) is housed in the three paper feed devices 10 (10a, 10)
b, 10c), and the transfer paper 11 of the paper feeding device 10 selected from one of them is fed by a feed roller 12 (1
2a, 12b, 12c), and the cutter 13
After being cut to a predetermined length by (13a, 13b, 13c), the resist roller 24 passes under the photosensitive drum 25 at a predetermined timing, and at this time, the transfer charger 2
By 3, the toner image is transferred.

The transfer paper on which the toner image has been transferred is then separated from the photosensitive drum 25 by the separation charger 28, conveyed by the conveyor belt 31 and sent to the fixing unit 30, where the toner is fixed on the transfer paper. . The transfer paper on which the toner has been fixed is sent to the paper discharge tray 32 and discharged outside the machine. A cleaning unit 29 removes the residual toner on the photosensitive drum 25.

Next, the operation panel 420 of the operation device 400 of FIG. 1 will be described with reference to FIG. FIG. 4 is a layout diagram showing a configuration example of the operation panel 420. The operation device 400 includes an operation control circuit 410 and an operation panel 42.
It consists of zero. The operation panel 420 includes keys for designating various functions, such as a start key 421 and a stop key 42.
2, mode clear key 423, setting key 424, ten key 425, paper type designation key 426, density adjustment key 427,
An image quality adjustment key 428, a paper size key 429, a scaling key 430, a set number display 431, a copy number display 432, a scaling display 433, and an original insertable display 434.
It has and.

Next, the flow of the entire image data will be described with reference to FIG. FIG. 5 is a block diagram for explaining the flow of the entire image data in this digital copying machine. Image memory unit 301 to even (E): 2bi
t, odd (O): 2-bit image data is sent to the LED writing control circuit 501 at 25 MHz in parallel with two lines. The image data sent to the LED writing control circuit 501 in two lines is once combined into one line in the LED writing control circuit 501, and then divided into two for each LED as a whole into six. 2bit to 5b
The plurality of LED heads 503_1, 503_2, 50 are converted into it through the LED head control circuit 502.
3_3 is transferred at 9.5 MHz.

A thermistor (TH) 504a as a temperature detecting means is connected to the printer control circuit 504. The thermistor 504a is provided inside or in the vicinity of each LED head 503_1, 503_2, 503_3 (light emitting element array unit), detects the temperature of the LED head itself or the temperature in the vicinity thereof, and responds to the detected temperature. A signal (analog signal) is input to the analog port of the printer control circuit 504. The thermistor signal input to the analog port of the printer control circuit 504 is A (not shown) in the printer control circuit 504.
Digitized by the / D conversion circuit, temperature data ON
The DO is serially sent to the LED writing control circuit 501, and the joint light amount correction (including the temperature correction) is performed there according to the temperature data ONDO, which will be described later in detail. In addition, the thermistor 504a is connected to each LE.
When provided inside the D heads 503_1, 503_2, 503_3, the respective LED heads 503_1, 503_
It is mounted as a chip component on the LED array substrate (LED array chip) in 2, 503_3.

Next, each block (circuit) of the LED writing control circuit 501 will be described with reference to FIGS. 6 and 7.
6 and 7 are block diagrams showing a configuration example of the LED writing control circuit 501. First, the LVDS receiver 512 that constitutes the image data input unit will be described.

Image data even (E): 2 bits,
Odd (O): 2 bits, and the timing signal is converted from parallel to serial using the LVDS receiver of the low voltage operation signal element from the image memory unit 301,
Since it is sent to the ED write control circuit 501 at 25 MHz,
Even in the LED writing control circuit 501, the LVDS receiver 5
12 to convert serial signals to parallel signals, PKDE (1..0), PKDO (1..0), XPC
LK, XPLSSYNC, XPLGATE, XPFGAT
It is input to the CPLD 510 (CPLD1) as E_IPU. Timing signals XPLSYNC and XPFGA
TE_IPU is delayed by the processing time of CPLD 510, and CPLD 511 is set as RLSYNC and RFGATE.
It is input to (CPLD2).

Next, the SR which constitutes the image data RAM section
AM 514A_1-514A_6 and 514B_1-
514B_6 will be described. The image data input to the CPLD 510 is ED (1 .. 0), OD (1 .. 0)
As SRAM address signals AADR (10..0) and BADR (10..0) together with 6 groups of SRAM (5
14A_1 to 514A_6), B group 6 SRAMs (5
14B_1 to 514B_6) at 25 MHz. The LED heads 503_1 to 503_3 have a total dot
The number is 23040 dots (A3 width 7680 dots x 3)
Since the data transfer is a 6-division (1/2 division × 3) method, one A3 width LED head is one division 3840.
6 for A group for each dot (7680 dots / 2 divisions)
The SRAMs 514A_1 to 514A_6 are provided.

Then, 2 dot (ED: 2 bit, O
The image data of D: 2 bits) is assigned to one address as 4 bits, and the LE of the image data of one line of the main scanning is stored in the SRAM 514A_1 (SRAM1) of the A group.
The image data of the first division of the D head 503_1 is set to SRA.
LED head 503_ on M514A_2 (SRAM2)
The image data of the second division of No. 1 is stored in the SRAM 514A_3.
The image data of the first division of the LED head 503_2 is stored in (SRAM3), and the image data of the second division of the LED head 503_2 is stored in SRAM 514A_4 (SRAM4).
The LED head 50 is attached to the RAM 514A_5 (SRAM5).
The image data of the first division 3_3 is stored in the SRAM 514A_
6 (SRAM 6) stores the image data of the second division of the LED head 503_3.

SRAM 514A with six A groups at 25 MHz
The image data sequentially stored in _1 to 514A_6 is
SRAMs 514A_1 to 5 of A group 6 at 4.75 MHz
14A_6 simultaneously read from the SRAM 514A_
1, the image data of the LED head 503_1 read from the SRAM 514A_2 is transferred to the CPLD 511 by SOD.
A1 (3.0), SODA2 (3.0), SODB1
(3..0), input as SODB2 (3..0), S
The image data of the LED head 503_2 read from the RAM 514A_3 and the SRAM 514A_4, and S
The image data of the LED head 503_3 read from the RAM 514A_5 and the SRAM 514A_6 is stored in the field memory (Field Memor).
y) It is sent to 515_1 to 515_3.

Six SRAMs 514A_1 to 514 in the A group
While A_6 is reading, the image data of the next line is transferred to the six SRAMs 1514B_1 to 514B of group B.
The data is stored in B_6 in the same manner as the A group. This read (read) 0, write (write) operation is performed by the SRA of six counties A.
M514A_1 to 514A_6, B count 6 SRAM5
14B_1 to 514B_6 are toggled to connect the lines.

Next, the field memories 515_1 to 515_3 forming the image data delay section will be described. (1) Image Data Delay Unit for LED Head 503_2 In this embodiment, three (three) A3 width LED heads 503_1 to 503_3 are arranged in a staggered pattern along the axial direction of the photoconductor drum 25. Therefore, the LED head 5
With reference to 03_1, the LED head 503_2 is mounted with a 7 mm offset in the sub-scanning direction in terms of mechanical layout (see FIG. 5).

Therefore, the six SRAMs 514A_ in the A group
1 to 514A_6 or six SRAMs 514B_1 in B group
When the image data read from ˜514B_6 are processed at the same time and transferred to the LED head 503_2, the LED head 503_2 has a size of 7 mm (7 mm / 42.3 μm (600 dpi) in the sub-scanning direction with respect to the LED head 503_1.
1 dot) = 165 lines) and the printing is done.
Therefore, in order to correct this mechanical deviation, 4.75M
3. The image data (4 bits each) for two divisions of the LED head 503_2 read from the SRAMs 514A_3, 514A_4 of the A group or the SRAMs 514B_3, 514B_4 of the B group at 4 Hz is transferred to the field memory 515_1 as the image data of 8 bits in the transfer line order. 75MHz
To write 100 lines (fixed).

Next, the image data is read from the field memory 515_1 at 4.75 MHz in the written order, and at the same time, the cascaded field memories 51 are connected.
Write 65 lines (variable) to 5_2. Next, the field memory 515_ is written in the order of writing at 4.75 MHz.
The image data is read out from No. 2 and input to the CPLD 511 as FMOD2 (7..0). This allows the LED
The image data of the head 503_2 has 165 lines (7 m
m) It has been delayed. The number of lines to delay is LE
Since the D head 503_2 varies depending on the accuracy of parts and variations in assembly, control can be performed in units of one line (42.3 μm).

(2) Image data delay unit for LED head 503_3 In this embodiment, three LED heads 503 of A3 width are used.
The LED heads 503_1 are arranged in a zigzag pattern along the axial direction of the photoconductor drum 25.
The LED head 503_3 is mounted with a shift of 1 mm in the sub-scanning direction on the mechanical layout (see FIG. 5).
reference). Therefore, the six SRAMs 514A_1 to
514A_6 or B count 6 SRAMs 514B_1 to 5
When the image data read from 14B_6 is processed at the same time and transferred to the LED head 503_3, the LED head 503_3 is 1 mm (1 mm / 42.3 μm (1 dot at 600 dpi) = 23 lines) in the sub-scanning direction with respect to the LED head 503_1. It will be misaligned and printed.

Therefore, in order to correct this mechanical deviation, the SRAMs 514A_5, 5 of the A group at 4.75 MHz.
14A_6 or B-group SRAM 514B_5, 514B
The image data (4 bits each) for two divisions of the LED head 503_3 read from _6 is written as 8 bits of image data into the field memory 515_3 for 23 lines (variable) at 4.75 MHz in the order of transfer lines. Next, the image data is read from the field memory 515_3 at 4.75 MHz in the order of writing, and the FMOD3
Input to CPLD511 as (7..0). As a result, the image data of the LED head 503_3 is delayed by 23 lines (1 mm). The number of lines to be delayed varies depending on the component accuracy of the LED head 503_3 and the variation in assembly, so one line (42.3
It is possible to control in units of μm.

Next, the light quantity correction ROMs 516_1, 516_2 and 516_3 which constitute the light quantity correction ROM section will be described. In this embodiment, each LED head 503_
The LED heads 503_1, 503_2, and 503 are used to correct the light amount variations of the LEDs 1 to 503_3.
For _3, the correction data (5
(Bit data) and a light amount correction ROM 516 storing correction data for each 192 LEDs (LED array chip)
_1, 516_2, 516_3 are provided, and each of the above-mentioned correction data in the light amount correction ROM 516_1 (hereinafter collectively referred to as “light amount correction data”) when the power is turned on (when the power is turned on) or after the LED writing control circuit 501 is reset. ) Is L
The light amount correction data in the light amount correction ROM 516_2 is transferred to the ED head 503_1, and the light amount correction data in the light amount correction ROM 516_3 is transferred to the LED head 503_3.

That is, first, the LED head 503_1
From the light amount correction ROM 516_1 corresponding to
Address signal from 11 HOSEIADR (12.0)
Accordingly, the light amount correction data is sequentially read from 0000h and input to the CPLD 511 as HOSEID (4..0). Then, inside the CPLD 511, 000
The data of 0h (light amount correction data of 1 dot) is latched, and the data of 0001h (light amount correction data of 3841 dot) is simultaneously transferred to the LED head 503_1 at 9.5.
Transferred in parallel at MHz. This process is 1E28h (77
The light quantity correction of the LED head 503_1 can be performed repeatedly by repeating up to 20 pieces of light quantity correction data).

After the transfer of the light quantity correction data from the light quantity correction ROM 516_1 to the LED head 503_1 is completed,
Similar to the above, the light amount correction data is transferred from the light amount correction ROM 516_2 to the LED head 503_2, and the light amount correction RO is performed.
The light amount correction data is sequentially transferred from M516_3 to the LED head 503_3. Each LED head 503_
1,503_2 and 503_3 are off
Unless otherwise, the transferred light amount correction data can be held internally. Therefore, when performing lighting ON / OFF (ON / OFF) control of each LED according to the image data transferred thereafter, the light quantity at the time of lighting (emission light quantity) is determined according to the light quantity correction data held inside. Can be corrected. At this time, it is also possible to perform joint light amount correction, which will be described later.

Next, the double copy SRAM 513 which constitutes the double copy RAM section will be described. This digital copier can print images up to 420 mm (A2 vertical size) in the main scanning direction up to 841 mm (A0 vertical size).
It has the function of doubling the productivity of copying and printer by arranging them twice on paper and printing (image formation). During double copy, image data (E [1 ..
0], O [1..0]) is transferred to the LED writing control circuit 501 when XPLSYNC is 1/2 or less. By utilizing this, a dubbing operation of image data is performed in one XPLSYNC.

The image data (E [1..0], O [1..0]) sent from the image memory unit 301 at 25 MHz is
From CPLD510, EDW (1..0), ODW (1 ..)
0) is output to the double copy SRAM 513 together with the address signal WADR (13..0), and the double copy S
Image data RAM stored at the same time as RAM513
It is also stored in the six SRAMs 514A_1 to 514A_6 of the group A. Simultaneously with the end of the storage of the image data from the image memory unit 301, the image data stored in the double copy SRAM 513 is read out, loaded into the CPLD 510, and similarly to the image data transmitted from the image memory unit 301, the A group 6 SRAMs 514A_1 to 514A
It is additionally read into _6.

As a result, the SRAM 514A having six A groups
In _1 to 514A_6, one main scanning line of the double copy image data is stored. The above operation is performed by toggling the six SRAMs 514A_1 to 514A_6 in the A group and the six SRAMs 514B_1 to 514B_6 in the B group to connect the lines.

Next, the driver 1000 constituting the image data output section will be described. LPH1 to 3 input to the CPLD 511 (LED heads 503_1 to 503_
The 2 line image data of 3) is combined into 1 line in the CPLD 511. Next, the image data obtained by combining one line is bit-converted from 2 bit data to 5 bit data, and as the final stage, the image data of the first division of the LED head 503_1 is D1A (4.0) and the image of the second division. Data is D1B (4.0), 1 of LED head 503_2
The image data of the second division is D2A (4.0), the image data of the second division is D2B (4.0), the image data of the first division of the LED head 503_3 is D3A (4.0), the second division. The image data of the eye is output as D3B (4.0) from the CPLD 511 together with the timing signal, and the driver 1000 drives each LED head 503_ at a speed of 9.5 MHz.
1 to 503_3, respectively.

Next, the EPRO which constitutes the download section
The M517 will be described. CPLD510, CPLD
Since 511 is an SRAM type CPLD,
The FF erases all the write control programs in the CPLD 510 and CPLD 511. Therefore, when the power is turned on (when the power is turned on), the program is downloaded (configuration) from the EPROM 517 every time. First, when the power is turned on, the CPLD51
0 from EPROM 517 DOWNLOAD_CPLD
The program is transferred as serial data as 1 and is downloaded, and at the same time when the download to the CPLD 510 is completed, the EPROM 517 is stored in the CPLD 511.
As a result, the program is transferred as DOWNLOAD_CPLD2 as serial data, and the program is downloaded.

Next, the reset IC 518 constituting the reset circuit section will be described. At power on or LE
Due to the voltage drop of the power supply to the D head control circuit 502, the system reset signal RE is sent from the reset IC 518.
SET_CPLD1 and RESET_CPLD2 are output. System reset signal RESET_CPLD
1 to CPLD 510, system reset signal RESE
T_CPLD2 is input to CPLD511 respectively,
Based on this, the counter circuits inside the CPLD 510 and CPLD 511 are reset, and the system is initialized.

Next, the printer control circuit 504 constituting the condition setting section will be described. LED writing control circuit 50
The setting of the write condition for 1 (presence or absence of double copy, write paper size, etc.) is set by each control signal LDATA (7..0), LADR (6 ..) from the printer control circuit 504.
0), VDBCS, XPFGATE_IOB, XPSG
ATE and XTLGATE are CPLD510 and CPLD5
It is performed by inputting in 11. Here, the printer control circuit 504 and the LED writing control circuit 501
Perform the functions according to the present invention shown in (1) and (2) below.

(1) Each LED head 503_1 to 503
Image data to be transferred to the LED head 50
Function as division transfer control means for transferring by dividing into 3_1 to 503_3 (in this example, image data is divided into 2 for each LED head 503_1 to 503_3, total 6 divisions) (2) of each LED head 503_1 to 503_3 Depending on the temperature detected by a thermistor which is provided inside or in the vicinity of the temperature detection means, which will be described later, a part of the division position of the image data by the function (1) (the number of divisions of the image data is the minimum 3
Each LED head 503_ corresponding to (if divided)
A function as a light amount correction unit that corrects the emitted light amount of one or both of the two LEDs (light emitting elements) located at the joints 1 to 503_3

Next, referring to FIG. 8 and FIG.
10 (CPLD1) and CPLD511 (CPLD
Before describing the details of the inside of 2), FIGS.
The inside of the LED heads 503_1 to 503_3 will be described below. First, referring to FIG. 10, the LED head 50
The LED head 503_1 of 3_1 to 503_3 will be described. The other LED heads 503_2,
Since 503_3 is also the same, the description is omitted.

FIG. 10 is a block diagram showing a configuration example of the LED head 503_1. LED head 503_1
Inside the LED array 530_1 to LED array 53
It is divided into 40 units of 192 0_40 LEDs and arranged at equal intervals in the main scanning direction. Driver ICs 531_1 to 531_40 are connected to the respective LEDs.

In addition to the image data corresponding to each dot (pixel), each of the driver ICs 531_1 to 531_40 has a strobe (STB) signal and data for lighting (emitting) each LED for a time corresponding to the image data. A transfer clock (CLK), a reset (RST) signal for clearing data, a light emission amount signal Vref for setting the light emission amount (brightness) of the entire LED, and the like are input as input signals. The image data transferred to the LED head 503_1 is the LED head control circuit 502 first.
Is input to the driver IC corresponding to each LED of the LED array 530_1. Then, the previous image data is cleared by the RST signal, the LED corresponding to the image data is turned on by the STB signal, and a latent image is formed on the surface of the photoconductor.

Next, referring to FIG. 11, the driver IC 53
Driver IC 531_1 of 1_1 to 531_40
The internal circuit and the LED will be described. The internal circuits of the other driver ICs 531_2 to 531_40 and the LEDs are the same, and thus the description thereof will be omitted. FIG. 11 is a block diagram showing a configuration example of the internal circuit of the driver IC 531_1 and the LED.

LEDs 1 to 192 are connected to GND with the cathode common, and the anode is the driver IC 531_.
It is connected to the emitters of the transistors 535_1 to 535_192 inside one. Transistors 535_1 to 5
The collectors of 35_192 are all connected to Vcc. The bases of the transistors 535_1 to 535_192 are amplifiers 536_1 to 536 that set the current of the LED.
_192 is connected to each output terminal.

One of the two input terminals of the amplifiers 536_1 to 536_192 is connected to the common Vref signal output terminal of the LED head control circuit 502, and the other is AND.
It is connected to the output terminals of the gates 537_1 to 537_192. One of the two input terminals of the AND gates 537_1 to 537_192 is connected to the LED head control circuit 502.
Connected to the common STB signal output terminal, and the other is LE
It is connected to an output terminal for image data of the D head control circuit 502.

Next, the control by the internal circuit of the LED writing control circuit 501 of FIG. 5 will be described with reference to FIGS. 8 and 9. 8 is a block diagram showing a configuration example of the CPLD 510 (CPLD1), and FIG. 9 is a CPLD 511 (CPL).
It is a block diagram which shows the structural example of D2).

The CPLD 510 is the image information storage device 30.
Control is performed to write or read 2-bit even data and odd data sent from 0 to the SRAM group. Also, it enables selection with a test pattern and generates a gate signal required for data transfer. The CPLD 511 is a 2-bit even data stored in the SRAM group under the control of the CPLD 510,
The LED data is synthesized into one line, the 2-bit data is converted into 5-bit data, and the LED heads 503_1 to
503_3 is controlled.

Detailed control of each part (each block) of the CPLD 510 will be described below. First, CPLD51
Regarding the control of the data input thinning unit 521 within 0, FIG.
An explanation will be given by (1) of 2. Figure 12 shows CPLD5
3 is a circuit diagram showing a configuration example of a data input thinning unit 521 in FIG. In the figure, “FF” is a flip-flop circuit. The printer control circuit 504 inputs 2-bit unit even data PKEDI and odd data PKODI in synchronization with the transfer reference clock XPCLK.
It is latched by _1, 2ndFF600_2, 3rdFF600_3, and the data before and after the pixel of interest is input to the combination circuits 601_1 and 601_2, and the output thereof is input to the comparator 602.

The data output from the comparator 602 is input to the mask FF 603 in the next stage and masked so that it is output only during the image effective range signal. The masked data is output as PKEDI3 and PKODI3.
Here, in order to perform the control, the image information storage device 3 is selected by selecting a mode in which the pixel of interest is converted by a key operation on the operation panel 420 of the operation device 400.
00, the converted signal (thin line signal) is input to the CPLD 510 via the register unit 530.

Next, the control of the signal selection unit 520 in the CPLD 510 will be described with reference to FIG. Figure 1
3 is a circuit diagram showing a configuration example of the signal selection unit 520 in the CPLD 510. The printer control circuit 504 sends the transfer reference clock XPCLK or the test clock TEST_CLK from an internal circuit (not shown) to the EXTMOD from the register unit 530 by the selector circuit 620.
The SRAM write control unit 5 in the next stage is selected by a signal.
25 as the write clock SWCLK.
In addition, the write clock SWCLK is set to the internal LSYN
The write start signal WST is input to the C generation circuit 622.
Generate and output TP.

Further, the mask area setting circuit 621 receives the image area signal XPLGATE from the image information storage device 300.
Image mask ISR from the register unit 530.
The range is specified by EG, and the image effective range signal PLGA
Output as TEIS. The image effective range signal PL
GATEIS is input to the selector circuit 625, selected with the write start signal WSTTP by the signal TESTMOD from the register unit 530, and output as the main scan write start signal WRSTART. The image period signal XPFG output from the image information storage device 300
The image period signal IOBFGATE synchronized with the ATE and the internal LSYNC synchronizing circuit 623 is input to the selector circuit 624, selected by the signal FGTMOD from the register unit 530, and output as the writing period signal SWFGATE.

The write start signal WSTTP generated and output by the internal LSYNC generation circuit 622 and the main scan pixel start signal XPL output from the image information storage device 300.
SYNC is input to the selector 626, and the register unit 5
A signal TESTMOD from 30 is used for selection and output. The signal output from the selector circuit 626 is SY
The signal is input to the SCLK synchronizing circuit 627, synchronized with the internal reference clock SYSCLK, and output as the read main scanning image start signal RLSYNC.

The read main scanning image start signal RLSY
NC is input to the 1-line delay circuit 628, and the write period signal SWFGA output from the selector circuit 624.
The read image period signal RFGATE is output in synchronization with TE. Each gate signal described above is the SR of the next stage.
AM write control unit 525, SRAM read control unit 5
26, the block switching control unit 524, the double copy control unit 519, and the test pattern generation unit 522.

Next, the control of the test pattern generator 522 in the CPLD 510 of FIG. 8 will be described with reference to FIG. FIG. 14 is a circuit diagram showing a configuration example of the test pattern generation unit 522 in the CPLD 510. The printer control circuit 504 inputs the main-scanning write start signal WSTTP and the sub-scanning writing period signal SWFGATE generated by the signal selection unit 520 to the main-scanning counter circuit 604 and the sub-scanning counter circuit 605, and the main-scanning counter circuit 604 outputs the signal. LCOUNT is generated by the sub-scanning counter circuit 605 to generate a signal FCOUNT, and a combination circuit 606 combines both signals to generate a pattern.

Each of the generated patterns is input to the selector circuit 607, selected by the pattern selection signal from the register unit 530, and output as the data TPDATA. The data T output from the selector circuit 607
PDATA is input to the 2-bit conversion circuit 608, and 2
The bit data PKEDTP and PKODTP are output.

Next, the control of the selector section 523 in the CPLD 510 of FIG. 8 will be described with reference to FIG. FIG. 15 is a circuit diagram showing a configuration example of the selector unit 523 in the CPLD 510. The printer control circuit 504 outputs 2-bit even data PKEDI3 and odd data PKODI3 output from the data input thinning unit 521,
2-bit even data PKEDT that forms the test pattern output from the test pattern generation unit 522
P and odd data PKODTP are input to the selector circuit 609, and the register unit 53 is read from the image information storage device 300.
Pattern selection signal (operation device 40
0 is selected by a key operation on the operation panel 420), and data PKED4, PKOD4
To output.

Next, the control of the double copy controller 519 in the CPLD 510 of FIG. 8 will be described with reference to FIGS.
Explained by. FIG. 16 is a circuit diagram showing a configuration example of the double copy control unit 519 in the CPLD 510. FIG. 17 is a timing chart showing the operation of the double copy control unit 519. The printer control circuit 504 uses the transfer reference clock XPCLK, the write start signal WRSTART from the signal selection unit 520, and the register unit 5.
Counter copy circuit 630
To output a count signal synchronized with XPCLK by the count set in the register unit 530.

The count signal output from the counter generation circuit 630 is the SRAM write period circuit 631, SR.
AM read period circuit 632 and selector circuit 63
Input to 3. The SRAM write period circuit 631
The count signal, the write start signal WRSTART from the signal selection unit 520, and the double copy signal from the register unit 530 are input, and the write period signal WCP_WEN to the SRAM is output. The SRAM read period circuit 632 uses the SRAM write period signal WCP_W.
After EN is input and the input of the signal is completed, the read period signal WCP_REN to the SRAM is output.

Control signal to external SRAM, write signal WRW, read signal RDW, count signal WADR
Is a write period signal WCP_WEN output from the SRAM write period circuit 631 and a read period signal WCP output from the SRAM read period circuit 632.
_REN is input to the combination circuit 638, the inverting circuit 639, and the selector circuit 633 to be generated and output. Data PKED output from the selector unit 523
4, PKOD4 is input to selector circuits 634 and 637.

The data input to the selector circuit 634 is selected there by the write period signal WCP_WEN from the SRAM write period circuit 631, the write start signal WRSTART and the write period signal SWFGATE from the signal selector 520, and the data PKED.
5, PKOD5, and is input to the selector circuit 635. The selector circuit 635 uses the write period signal WCP_WEN from the SRAM write period circuit 631.
Input data is selected by, and data EDW, ODW
Output as.

These data EDW and ODW are external SR
It is AM data, has bidirectionality, and inputs a read signal from the SRAM to the selector circuit 636. The selector circuit 636 selects the input data by the SRAM read period signal WCP_REN, and outputs the data PKE.
It is output as DD and PKODD and input to the selector 637. The selector circuit 637 uses the data PKEDD, P
KODD and data PKED4 and PKOD4 are input,
It is selected by the write period signal WCP_WEN from the SRAM write period circuit 631 and the double copy signal from the register unit 530, and output as output data PKED and PKOD.

Here, the operation timing of the double copy control section 519 will be described with reference to FIG. When the double copy mode is selected, the write start signal W
When RSTART becomes a high level “H” (ON), the SRAM writing period WCP_WEN for double copy also becomes “H”, and the input image data is transferred to the SRAM group for normal operation and also to the SRAM for double copy. Written. At the midpoint of the main scanning direction, the SRAM read period WCP_REN for double copy becomes “H”, and the data of the SRAM group is read from the double copy SRAM and transferred, so that the main scan is performed. The same image data is written in the line.

Next, the data format conversion unit 518, the block switching control unit 524 and the block format control unit 524 in the CPLD 510 of FIG.
Before describing the SRAM write control unit 525, the SRAM read control unit 526, the write pulse generation unit 527, and the address selector unit 528, each LED head 5 is described.
The image areas of 03_1 to 503_3 will be described. FIG. 18 is an explanatory diagram for explaining the image areas of the LED heads 503_1 to 503_3. Each LED head 5
03_1 to 503_3 are all 7680 dots (d
ot) has a length corresponding to the number of pixels.

The LED heads 503_1 to 503_3 are overlapped at both ends to have a blank area, and the effective image area is controlled so that the images do not overlap each other.
In addition, the LED head 503_2 fixes the effective image area and prevents the image from being captured by setting 258 dots at both ends as blank areas, and the LED heads 503_1 and 503_
3, the effective image area remains fixed, but the image is shifted so that the LED heads (LED heads 503_1 and 503_
2 and between the LED heads 503_2 and 503_3). Each LED head 503_1
SR assigned image of effective image area of 503_3
Data is written to AM in units of 2 dots (pixels).

Next, referring to FIGS. 19 to 21, the A group 6
The SRAM 514A_1 to 514A_6 and the B group Six SRAMs 514B_1 to 514B_6, the order of writing and reading the data, the data transfer direction to each LED of each LED head 503_1 to 503_3, and the SRAM address will be described. 19-
FIG. 21 shows an SRAM 514A_1 (SRAM with six A groups).
1) to 514A_6 (SRAM6), SRA of 6 B groups
M514B_1 (SRAM1) to 514B_6 (SRA
The order (direction) of writing data to and reading data from M6), and the LED heads 503_1 to 503
It is explanatory drawing for demonstrating the data transfer direction to each LED of 3_3, and SRAM address.

The effective pixel number corresponds to one pixel data transferred from the image information storage device 300 shown in FIG.
The numbers 0 to 21611 are arranged in the order of transfer to the ED. Three LED heads 503_1 to 503
The data sharing of _3 is 0 to 7223 dots for the LED head 503_1, 7224 dots to 14387 dots for the LED head 503_2, and 14388 dots to 21611 dots for the LED head 503_3.

The physical position on the LED head (LPH) is
It shows where each of the LED heads 503_1 to 503_3 is turned on by one pixel data of each effective pixel number. Each of the LED heads 503_1 to 503_3 has a corresponding data transfer of two divisions.
There are 3840 dots, which is half of the dots. 3 LEs
The D heads 503_1 to 503_3 are the photoconductor drums 25.
Since they are arranged in a staggered pattern along the axis of
The data transfer direction from the RAM to each LED of each LED head 503_1 to 503_3 is as follows.

That is, the LED head 503_1 (LP
Data transfer to each LED in H1) starts from the bottom (actually right to left). LED head 503_2 (LPH
The data transfer to each LED in 2) starts from the top (actually from left to right). LED head 503_3 (LPH
The data transfer to each LED in 3) starts from the bottom (actually from right to left). Three LED heads 503_1-5
If 03_3 are overlapped to form a straight line, the LED head 5
Since the 258th dot of the A block of 03_1 is followed by the 258th dot of the A block of the LED head 503_2, the image data is connected without deviation.

Similarly, the B block 3581th dot of the LED head 503_2 follows the B block 3581th dot of the LED head 503_2. The address on the SRAM is 1 of 2 divided data transfer per LED head.
One SRAM is associated with the division (3 LED heads * 2 divisions = 6). That is, the image data of the first line is transferred to the SRAMs 514A_1 (SRAM1) to 514A of group A.
A_6 (SRAM6) is written to, and image data of the second line is written in SRAMs 514B_1 (SRAM1) to 5 of group B.
Since it is written in 14B_6 (SRAM6), 12 S
This is a configuration that uses a RAM.

The data transfer direction to the LEDs of the LED heads is that the LED heads 503_1 and 503_3 are from the bottom,
Since the LED head 503_2 is from above, each SRA
The write address to M is set to the LED head 503_1,
503_3 down count, LED head 5
It counts up to 03_2. Also, SRA
Since data is written (stored) in units of 2 dots in the M1 address, the data for one division of the LED head is 384.
The 1920 address is half of 0 dot. The write start address and write end address of SRAM are
The image information storage device 300 depends on the size of the original / transfer paper.
Output the appropriate address value, and register unit 5
30 is transferred.

On the other hand, the LED heads 503_1 and 503_
Address between 2 and (LPH1-2), LED
Between the heads 503_2 and 503_3 (LED head 2
The joint address (between −3) is input by a key operation on the operation panel 420 of the operation device 400 of FIG. 1, and is transferred from the image information storage device 300 by the register unit 530. By the above-mentioned operation, the joint can be adjusted. Further, the write start address and the end address are also changed according to the adjustment of the above-mentioned joint. Next, in the SRAM read direction, all the data written to the addresses on each SRAM are simultaneously up-counted and read from the address 0. The reading direction is the transfer direction when each LED head is attached. The above operation is performed by SRA with 6 A groups.
M514A_1 to 514A_6 and SRAM 5 with six B groups
The data of the main scanning line can be transferred by alternately performing 14B_1 to 514B_6.

Next, the control of the block switching controller 524 in the CPLD 510 of FIG. 8 will be described with reference to FIG. FIG. 22 is a circuit diagram showing a configuration example of the block switching control unit 524 in the CPLD 510. Input write clock SWCLK, read main scan image start signal RLS
YNC and the read image period signal RFGATE are input to the block switching signal generation circuit 814, from which the line block switching signal BLOCK that switches for each main scanning line when the read image period is valid is output, and the group A S.
The RAM and the B-group SRAM are switched.

Next, the SRAM in the CPLD 510 shown in FIG.
The control of the write controller 525 will be described with reference to FIG. FIG. 23 is a circuit diagram showing a configuration example of the SRAM write control unit 525 in the CPLD 510. The printer control circuit 504 uses the input write clock SWCL.
K, reference synchronization clock SYSCK, and register unit 5
The clear signals MCLR and SRESET from 30 are input to the reset pulse generation circuit 816 to output the reset pulse SRESRP, and the SRAM write control circuit 8
17 and write address counter circuit 818.

The SRAM write control circuit 817 receives the write start address signal HS from the register section 530.
TADRS, write start SRAM block signal HST
Based on BLK, the write end address signal HENADRS, and the write end SRAM block signal HENBLK, processing is performed from which SRAM the write operation is started, and under what conditions the transition to the next SRAM and the return to the start position are performed. The SRAM write processing sequencer signal seq_p is output. Printer control circuit 504
Causes the SRAM write processing sequencer signal seq_p to be input to the write address counter circuit 818, and SR
S in response to the AM write processing sequencer signal seq_p
The RAM write address counter signal WCNT is set and output.

SRAM write processing sequencer signal se
The SRAM write address counter signal WCNT is set according to q_p, but as shown in FIGS. 19 to 21, the write address setting to each SRAM is down-counted for the odd-numbered LED heads 503_1 and 503_3. , Even-numbered LED heads 503_2 are up-counted, and odd-numbered LED heads 5
The transfer directions of the image data to the LEDs of 03_1 and 503_3 and the transfer directions of the image data to the LEDs of the even-numbered LED heads 503_2 are controlled to be opposite. It is possible to control even if a plurality of LED heads are arranged in the same direction and the transfer direction of image data to each LED of each LED head is the same.

Next, the SRAM in the CPLD 510 of FIG.
The control of the read control unit 526 will be described with reference to FIG. FIG. 24 is a circuit diagram showing a configuration example of the SRAM read control unit 526 in the CPLD 510. The printer control circuit 504 reads the reference synchronization clock SYSCK, the read main scanning image start signal RLSYNC, and the read image period signal RFGATE and reads the counter generation circuit 82.
2 and the reference synchronization clock SYSCK is divided by 4 to read the SRAM read timing counter signal SRRD.
CK is output and input to the SRAM read control circuit 823.

In the SRAM read control circuit 823, the SR
In addition to the AM read timing counter signal SRRDCK, the SRAM write processing sequencer seq_p from the SRAM write control unit 525, the SRAM write address counter signal WCNT, and the reset pulse SRESR.
By inputting P, the SRAM read address counter signal RCNT is output. The SRAM read address counter signal RCNT is the line block switching signal BLOCK from the block switching control unit 524.
A signal indicating which of the SRAMs of the A and B groups is enabled, that is, the SRAM read signal RDA of the A group or B group SRAM read signal R
The DB is selectively output.

Control of the write pulse generator 527 and the address selector 528 in the CPLD 510 of FIG. 8 will be described below with reference to FIGS. 25 to 27. Figure 2
5 is a circuit diagram showing a configuration example of the write pulse generation unit 527 in the CPLD 510, and FIG. 26 is a circuit diagram showing a configuration example of the address selector unit 528 in the CPLD 510. FIG. 27 is a timing chart showing the operations of the write pulse generator 527 and the address selector 528.

The printer control circuit 504 receives the SRAM write processing sequencer signal seq_p from the SRAM write control unit 525 and the line block switching signal BLOCK from the block switching control unit 524, and the write pulse generation circuit 81 which constitutes the write pulse generation unit 527.
9 to input the line block switching signal BLOC, for example.
If K is "H", write enable signals WEA1 to WEA6
To select the SRAM write processing sequencer signal se
High enable the corresponding SRAM of q_p. Therefore, the write enable signals WEA1 to 6 are sequentially enabled in the first main scanning line, and the write enable signals WEB1 to WEB1 in the second main scanning line.
6 are sequentially enabled.

Write enable signals WEA1-6 and WEB1-6 output from the write pulse generation circuit 819.
6 is input to the write signal generation circuit 820. The write signal generation circuit 820 synchronizes the input write enable signals WEA1 to 6 and WEB1 to 6 with the input write clock SWCLK, and the A group SRAM write signals WRA1 to 6 and the B group SRAM write signal W.
Output RB1 to RB6. The printer control circuit 504 uses the S
In order to validate the RAM write signal, the write period enable signal SWFGATE is input to the SRAM write block signal generation circuit 821, and the A group SRAM buffer gate signal ASEL and the B group SRAM buffer gate signal BSEL are output.

On the other hand, the printer control circuit 504, when the read image period indicated by the read image period signal is valid,
An address selector circuit 815 that forms an address selector unit 528 receives a line block switching signal BLOCK that switches from the block switching control unit 524 for each main scanning line.
And the SRAM write address counter signal WCNT output from the SRAM write control unit 525 and the SRAM output from the SRAM read control unit 526.
The input of the read address counter signal RCNT is switched to switch the group A SRAM address signal AADR or the group B S
It is output as a RAM address signal BADR.

Next, the control of the data format conversion unit 518 in the CPLD 510 of FIG. 8 will be described with reference to FIG. FIG. 28 is a circuit diagram showing a configuration example of the data format conversion unit 518 in the CPLD 510. S
Data for one address to the RAM is in units of 2 pixels. In order to control the position correction between the heads of the joint between the LED heads 503_1 and 503_2 and the joint between the LED heads 503_2 and 503_3 on a pixel-by-pixel basis,
The input data is set to 1 without changing the SRAM write address.
Pixel shift.

The printer control circuit 504 receives the input 2-bit even data PKED and the input 2-bit odd data P.
KOD is input to the latch 1 circuit 810 and latched by the input write clock SWCLK, and the data PKE
Output as D1D and PKOD1D. Also, latch 1
The data PKOD1D output from the circuit 810 is latched by the latch 2 circuit 811 and output as PKOD2D. Latch 1 circuit 810 and latch 2 circuit 81
The data output from 1 is the LED head 503_3
1-dot delayed data for (LED head 3), LE
D head 503_2 (LED head 2), regular data to LED head 503_3 (LED head 3), LED
The data delayed by one dot to the head 503_1 (LED head 1) and the regular data to the LED head 503_1 are input to the selector circuit 813.

The printer control circuit 504 determines which of the data input to the selector circuit 813 is the SRA.
The SRAM write processing sequencer signal seq_p that determines whether the data is M data and the shift signal SHIFT transferred from the image information storage device 300 by the register unit 530.
1, 3, write start address signal HSTADRS, head 2-3 connection address signal HCHADRS2, SR
It is selected based on the AM write address counter signal WCNT and output as data ED or OD.

Next, the control of the field memory write controller 529 in the CPLD 510 of FIG. 8 will be described with reference to FIG.
Explained by. FIG. 29 is a circuit diagram showing a configuration example of the field memory write control unit 529 in the CPLD 510. The field memory write control unit 529
This is a block for generating a gate signal for writing the image data to be transferred to the LED heads 503_2 and 503_3 output from the SRAMs 514A_3 to 514A_6 of the A group 6 and the SRAMs 514B_3 to 514B_6 of the B group 6 to the field memory (FM). .

The image data to be transferred to the LED head 503_2 includes two field memories 515_1 and 515_.
2, the data for 100 lines is written (stored) in the field memory 515_1, then transferred to the field memory 515_2, and the image data to be transferred to the LED head 503_3 is the field memory 515_3.
Write in. The printer control circuit 504 uses the reference synchronization clock SYSCK and the read main scanning image start signal RLSY.
NC, the sub-scanning delay counter signal SSDC for inputting the read image period signal RFGATE to the sub-scanning counter generation circuit 825 and delaying it by 100 lines to transfer the data to the field memories 515_1 to 515_2.
Output NT.

Next, the read main scanning image start signal RLS
YNC, S in addition to the readout image period signal RFGATE
SRAM read address counter signal RCNT from RAM read control unit 526, reference clock SYSCK
The SRAM read timing counter signal SRRDCK divided by 4 is input to the FM write address reset signal generation circuit 826, and the read main scan image start signal R
When LSYNC is set to “H”, the FM write address reset signal FMWRST is generated and output, and the addresses of the field memories 515_1 to 515_3 are initialized.

FM write address reset signal FMW
The RST is input to the conversion circuit group 831. The conversion circuit group 831 uses the FM write address reset signal FMWR.
By inputting ST, the field memory 515_1 (FM
1), FM for resetting 515_2 (FM2)
1, 2, write address reset signal FM2RSTW,
Alternatively, an FM3 write address reset signal F for resetting the field memory 515_3 (FM3)
Outputs M3RSTW.

Here, the field memory 515_1 (F
The write addresses of M1) to 515_3 (FM3) are reset, and the write enable signal described later is “H”.
When the line data (image data) is written in the field memory 515_1 (FM1) and the line data of the sub-scanning line 100 is written (stored), the read address of the field memory 515_1 (FM1) is reset. , The printer control circuit 504 causes the FM1 read address reset signal generation circuit 827 to output the FM read address reset signal FMRRST1 in order to transfer the line data to the field memory 515_2 (FM2).

Further, in order to determine the FM write-on time, the printer control circuit 504 causes the FM write enable signal generation circuit 828 to output the FM write enable signal FMWE. FM write enable signal F
The MWE is input to the conversion circuit group 831. The conversion circuit group 831 receives the FM write enable signal FMWE and receives the FM1 and 2 write enable signals FM2W that allow writing to the field memory 515_1 (FM1) and the field memory 515_2 (FM2).
E, FM3 write enable signal FM3W that permits writing to the field memory 515_3 (FM3)
E, or an FM2 read enable signal FM2RE that permits reading from the field memory 515_2 (FM2) is output.

The printer control circuit 504 inputs the SRAM read timing counter signal SRRDCK obtained by dividing the reference clock SYSCK by 4 to the clock generation circuit 829 and outputs the FM write clock FMWCLK. The conversion circuit group 831 receives the FM write clock FMWCLK from the clock generation circuit 829 and receives the FM1 and 2 write clocks FM2SWCK and field memory 515_3 for writing the line data in the field memory 515_1 (FM1) and the field memory 515_2 (FM2). FM3 write clock FM3SWC for writing line data to (FM3)
K, or FM2 read clock FM2SRCK for reading line data from the field memory 515_2 (FM2) is output.

The printer control circuit 504 outputs the A group SRAM read signal RDA and the B group SRAM read signal RDB output from the SRAM read control unit 526 to FM.
1, 3A group / B group write buffer gate generation circuit 83
Field memory 515_1 (FM1)
And whether to write the SRAM data of the A group or the SRAM data of the B group to the field memory 515_3 (FM3). The FM3 write buffer gate signal FM3DASEL or the B group FM3 write buffer gate signal FM3DBSEL is output. The output operation of these gate signals is the toggle operation of the A and B groups.

Next, control of the register unit 530 in the CPLD 510 of FIG. 8 will be described with reference to FIG. FIG. 30 is a circuit diagram showing a configuration example of the register unit 530 in the CPLD 510. The printer control circuit 504 causes the address data output from the image information storage device 300 to be latched by the SYSCLK synchronizing circuit 900 that constitutes the register unit 530 by the clock SYSCLK,
Confirm the input data and output it. In addition, CP to be described later
The register unit 542 in the LD 511 has the same configuration,
Performs the same operation.

Subsequently, CPLD 511 (CPLD
Detailed control of each part of 2) will be described. CPLD51
In 1, the internal clock SYSCK is input to each control unit as the reference synchronization clock. The CPLD 511 generates a gate signal for reading the data of the field memories 515_1 to 515_3 and the LED heads 503_1 to 503_1.
A gate signal for transferring data to the LED head 503_3 is generated.

Under the control of the CPLD 510, 2-bit even data and odd data to be transferred to the LED head 503_1 stored in the SRAM group are format-converted into 1-line composite, and further 2-bit data are converted into 5-bit data. To the LED head 503_1. Similarly, the LED head 50 stored in the field memory
Read the data to be transferred to 3_2, 503_3, and
2 as well as the data to be transferred to the ED head 503_1
The LED heads 503_2 and 503_3 are formed by converting the bit even data and the odd data into a one-line composite format, and further converting the 2-bit data into 5-bit data.
Transfer to each.

Detailed control of each part (each block) of the CPLD 511 shown in FIG. 9 will be described below. First, CPLD
An LED head transfer controller (hereinafter simply referred to as “transfer controller”) 540 and a test pattern generator 54 in 511.
The control of No. 1 will be described with reference to FIG. Figure 31
FIG. 6 is a circuit diagram showing a configuration example of a transfer control unit 540 and a test pattern generation unit 541 in the CPLD 511. However, this circuit diagram shows one configured by a circuit group having both the function of the transfer control unit 540 and the function of the test pattern generation unit 541.

The printer control circuit 504 outputs the read main scan image start signal RLSYNC from the reference synchronization clock SYSCK and the CPLD 510 to the sub scan counter circuit 7.
The sub-scanning counter signal indicating the count value is output to the test pattern generation circuit 703. Further, the read main scan image start signal RL from the reference synchronization clock SYSCK and the CPLD 510.
SYNC is input to the main scanning counter circuit 702 and counted, and a main scanning counter signal indicating the count value is generated by the P sensor generation circuit 704, the LED head (LPH) transfer signal generation circuit 1 705, and the LED head (LPH) transfer signal generation circuit. 2 to output to the circuit 706 and the clock generation circuit 707.

The test pattern generation circuit 703 outputs the internal test pattern TPDATA when the sub-scanning counter signal is input from the sub-scanning counter circuit 701. P
The sensor generation circuit 704 is used for image density detection,
By inputting the main scanning counter signal, the LED head 503
The P sensor pattern PSLGATE is output only to the defined portion of the A block (group A) of _2. The LED head transfer signal generation 1 circuit 705 receives the LPH image data clock effective range signal HC by inputting the main scanning counter signal.
Outputs LKEN.

LED head transfer signal generation 2 circuit 706
Outputs the LPH image data transfer clock HCLK only to the image data effective range to the LED heads 503_1 to 503_3 by inputting the main scanning counter signal and the LPH image data clock effective range signal HCLKEN. The clock generation circuit 707 clears the reference clock SYSCK for each main scanning counter signal and divides the clock CL by two.
It outputs KEN95 and a clock CLKEN475 divided by four.

Next, the control of the light quantity correction ROM read control unit 543 in the CPLD 511 of FIG. 9 will be described with reference to FIGS. 32 and 33. 32 and 33
FIG. 6 is a circuit diagram showing a configuration example of a light amount correction ROM read control unit 543 in the CPLD 511. When the power is turned on,
The printer control circuit 504 includes a light amount correction counter circuit 70.
8, a reference synchronization clock SYSCK, a read main scanning image start signal RLSYNC output from the CPLD 510, and a light quantity correction mode switching signal (light quantity correction start signal) KHST
The AT is input and the sub-scanning counter signal KHFCNT is generated and output.

The selector / comparison circuit 709 outputs the sub-scanning counter signal K output from the light quantity correction counter circuit 708.
Based on the HFCNT, the light amount correction ROM (PR
OM) access enable signal ROMCE for permitting access to 516_1, 516_2, 516_3
Outputs 1, 2, 3 In addition, the light amount correction start signal KHS
TCLR, light quantity correction data LOAD signal KHLOADR to each LED head 513_1 to 513_3, light quantity correction effective signal LPHSEL, light quantity correction main scanning count signal K
HLCNT is generated and output as a gate signal. RO
The M address generation circuit 710 uses the light amount correction valid signal LPH.
SEL and light quantity correction main scanning count signal KHLCNT
The address of the light amount correction ROM is generated based on the above and output.

Here, one light quantity correction ROM (PRO
In M), the light amount correction data for one LED head is stored, and each LED head 503_1 to 503_3 is stored.
Correspond to the two-part data transfer method, so that the respective light amount correction ROMs 516_1, 516_2, 5
The stored data of 16_3 are A blocks (A group), respectively.
It is arranged alternately with the first data of the eye and then the first data of the B block (B group).

Therefore, the ROM output data latch circuit 71 is provided.
2 is the input ROM light amount correction data ROMDT (5
(Bit data) Light intensity correction main scan count signal KHLC
It is latched three times by NT, divided into LED head A block light amount correction data KHDATA1R and LED head B block light amount correction data KHDATA2R, and simultaneously output. In addition, the light amount correction effective range circuit 711 is
A clock CTCKR for light amount correction data transfer to the ED heads 503_1 to 503_3 is generated and output.

Next, the control of the field memory read control unit 531 in the CPLD 511 of FIG. 9 will be described with reference to FIG.
Explain by. FIG. 34 is a circuit diagram showing a configuration example of a field memory (hereinafter also referred to as “FM”) read control unit 531 in the CPLD 511. The FM read control unit 531 generates an FM gate signal for delaying the data of the LED heads 503_2 and 503_3 which are attached to the LED head 503_1 with their positions displaced in the rotational direction of the photosensitive drum 25.

In the FM read control section 531, the counter sub-scanning circuit 719 and the FM delay period generating circuit 720 are provided.
And an FM read reset generation circuit 721, a reset signal generation circuit 721 for reset signal FM2RST for starting the reading of FM515_2, 515_3.
R, FM3RSTR is generated and output. The FM read range generation circuit 718 allows the FM read enable signal FM2 to permit the read of the FMs 515_2 and 515_3.
Outputs RE2 and FM3RE. Counter circuit 717
Generates and outputs clocks FM2SRCK2 and FM3SRCK for reading the data stored in the FM.

The sub-scanning delay circuit 722 outputs signals DMSK1 and DSK for delaying the delayed sub-scanning to the rear end side.
Generates and outputs MSK2 and DMSK3. The read start signal generation circuit 715 synchronizes the read main scanning image start signal RLSYNC generated by the CPLD 510 with the reference clock SYSCK, and reads the read signal RLSYNC.
DD is output and input to each circuit in the subsequent stage. The counter circuit 716 counts the reference clock SYSCK,
A count signal RDCK indicating the count value is output,
Read signal RLS synchronized with reference clock SYSCK
Reset with YNCDD and count again.

(1) Reset signals FM2RSTR, F for starting the reading of FM515_2, 515_3
The printer control circuit 504 of the M3RSTR generates a read signal RLSYNCD synchronized with the read image period signal RFGATE generated by the CPLD 510 and the reference clock SYSCK.
D is input to the counter sub-scanning circuit 719, and the FM 515
_2 count signals DLCNT2 and FM515_
The count signal DLCNT3 for 3 is output and input to the FM read reset generation circuit 721 and the delay circuit 722.

Further, the sub-scanning delay set value set in the register section 542 by the key operation on the operation panel 420 of the operation section 400, the FM2DL and FM3DL for FM, and the read signal R synchronized with the reference clock SYSCK.
FMSYNC_2 (for LED head 503_2), FM515_3 (LED head 50) by inputting LSYNC2D (RLSYNCDD) to the FM delay period generation circuit 720
3_3) delay period enable signal DLCNT2,
Generates and outputs DLCNT3. Further, the signals output from the counter sub-scanning circuit 719, the FM delay period generation circuit 720, and the counter circuit 716 are converted into FM signals.
The read reset generation circuit 721 is input to generate and output the FM read reset signals FM2RSTR and FM3RSTR. Note that the pulse width is the counter circuit 716.
4 counts from

(2) Generation of clocks (FM3SRCK, FM2SRCK2) of FM515_2, 515_3 The counter circuit 717 divides the count signal RDCK from the counter circuit 716 by 4 to generate a clock FM3SRC.
K, FM2SRCK2 is generated and output.

(3) Generation of Read Ranges (FM3RE, FM2RE2) of FM515_2, 515_3 The printer control circuit 504 outputs the count signal RDCK from the counter circuit 716 to the FM read range generation circuit 71.
The read image period signal RFGATE generated by the CPLD 510 and the LED head 503_ to be described later are input by the counter circuit which is input to
FM read enable signals FM3RE and FM that enable (enable) the reading of FM515_3 and FM515_2, respectively, for two delayed DMSK2 periods.
Output 2RE2. The sub-scan delay start can be set by the above control, and the FM delay FGATE generation circuit 722 sets the sub-scan delay FGATE of each of the LED heads 503_1 to 503_3 in order to delay the sub-scan by the amount of the delayed output. Generate and output DMSK 1, 2, 3.

The printer control circuit 504 is the operating device 40.
No. 0 operation panel 420 key operation, the sub-scanning delay set value set in the register unit 542, FM2 for FM
Read signal RLSYNC2D (RLSYNCD) synchronized with DL and FM3DL and reference clock SYSCK.
D) is input to the FM delay period generation circuit 720, and FM5
15_2 (for LED head 503_2), FM515_
The sub-scanning of the three LED heads 503_1 to 503_3 can be adjusted by outputting the delay period enable signals DLCNT2 and DLCNT3 to the LED heads 3 (for LED head 503_3). Note that the LED heads 503_1 to 5
The default value is set on the assumption that the mounting of 03_3 is mechanically correct, the sub-scanning adjustment test chart (grating or the like) is output, and the operation panel 420 of the operation device 400 is further considered in consideration of the deviation. Do the above key operations.

Next, LPH1 in the CPLD 511 of FIG.
Regarding control of the image data input selection unit 534 and the LPH1 image data format conversion unit 535, FIG.
Explain by. FIG. 35 shows L in the CPLD 511.
PH1 image data input select section (hereinafter “select section”)
5) and an LPH1 image data format conversion unit (hereinafter referred to as “format conversion unit”) 535. FIG. However, this circuit diagram shows one configured by a circuit group having both the function of the selection unit 534 and the function of the format conversion unit 535.

The printer control circuit 504 uses the reference synchronization clock SYSCK, the read main scan image start signal RLSYNC from the CPLD 510, and the read image period signal R.
FGATE is input to the data switching signal generation circuit 723, and a data switching signal BANKSEL that switches using the read main scanning image start signal RLSYNC as a trigger is output during the read image period and is input to the data conversion circuit 724. The data conversion circuit 724 includes a transfer control unit 5
40 and the clocks CLKEN95 and CLKEN475 generated by the test pattern generation unit 541, and LE.
Sub-scanning delay of D head 503_1 FGATE, DMSK
1 is input.

The image data used here is the data to be transferred to the LED head 503_1, and is the SRA of the group A.
M514A_1, 514A_2 and B5 SRAM5
14B_1, 514B_2 are output from S of group A.
The 2-bit unit even / odd data output from the RAM 514A_1 is used as a 4-bit unit, and the data SO
Input as DA1.

In addition, 4-bit even-odd data in 2-bit units output from the B-group SRAM 514B_1 is used.
Data SODB1 as a bit unit and SRA of group A
Data SOD with 2-bit unit even and odd data output from M514A_2 as 4-bit unit
2 output from the RAM 514B_2 of the B group as A2
The even-odd data in bit units is set as data SODB2 in 4-bit units. Here, SR of group A
The data format of the SRAM 514B_1 of the AM 514A_1, B group will be described.

SRAM 514A_1 of group A, SR of group B
4-bit data SODA1, SO of AM514B_1
Since DB1 is mounted on the LED head 503_1 in the image transfer direction from the left to the right,
Since the data transfer of the head corresponds to the B block of the A and B blocks, it is output from the B block data IMDATA2. The data conversion circuit 724 controls the data switching signal BANK.
SRAM 514A_1 of the A group during the period when ASEL is “H”
The 4-bit data SODA1 from is selected. 4
As described above, the bit data SODA1 is composed of 2-bit even data and odd data. That is, the upper 2 bits of the 4-bit data SODA1 are odd data, and the lower 2 bits are even data.

Then, the clock CLKEN generated by the transfer controller 540 and the test pattern generator 541 is used.
From the relationship between 95 and CLKEN475, the clock CLKE
When N95 is "H" and CLKEN475 is "L",
IMDAT by converting the upper 2 bits of the 4-bit data SODA1 into serial data.
Output as A2 and clock CLKEN95 and CL
When both KEN475 are "H", the lower 2-bit even data of the 4-bit data SODA1 is format-converted into serial data and output as IMDATA2, and thereafter, the respective operations are alternately performed.

Further, while the data switching signal BANKASEL is "L", the 4-bit data SODB1 from the SRAM 514B_1 of the B group is selected and the data SODA1 is selected.
Similarly to the operation for, the format conversion of the upper 2 bits of the odd data into the serial data is performed and IMDATA
Then, the lower 2 bits of the even data are converted to serial data and converted to IMDATA2.
, And thereafter, the respective operations are alternately performed. S of group A
The 4-bit data SODA2 from the RAM 514A_2 and the 4-bit data SODB2 from the SRAM 514B_2 of the B group are converted into serial data by format conversion of the upper 2-bit odd data in the same manner as described above.
The operation of outputting as DATA1 and the format conversion of the lower 2 bits of even data into serial data are performed, and M
The operation of outputting as DATA1 is alternately performed.

Next, the LPH in the CPLD 511 of FIG. 9 is
The control of the 2,3 image data format conversion unit 532 will be described with reference to FIG. Figure 36 shows CPLD
5 is a circuit diagram showing a configuration example of an LPH2,3 image data format conversion unit (hereinafter referred to as “format conversion unit”) 532 in 511. FIG. The data conversion circuit 725 forming the format conversion unit 532 performs format conversion of data to be transferred to the LED head LED head 503_2 and format conversion of data to be transferred to the LED head 503_3.

Among them, the format conversion of the data to be transferred to the LED head 503_2 is performed as follows. The printer control circuit 504 uses the reference synchronization clock SY.
SCK, read main scan image start signal RLSYNC from CPLD 510, read image period signal RFGAT
E, the transfer control unit 540, and the test pattern generation unit 5
Clocks CLKEN95 and CLKE generated at 41
N475 is input to the data conversion circuit 725, and FM5
The 8-bit data from 15_2 is format-converted, and the 2-bit data IMDATA1 to the A block and the 2-bit data IMDATA2 to the B block of the LED head 503_2 are output.

Here, among the 8-bit data from FM515_2, the upper 4-bit data is the SRAM 51 of the A group.
4A_4, 2-bit even data and 2-bit odd data from 514B_4 of the B group, lower 4-bit data is SRAM 514A_3 of the A group, 514B_ of the B group.
They are 2-bit even data and 3-bit odd data from 3. The former is converted into output data IMDATA2, and the latter is converted into output data IMDATA1.

The data conversion circuit 725 includes a transfer controller 54.
0 and the relationship between the clocks CLKEN95 and CLKEN475 generated by the test pattern generation unit 541,
When the clock CLKEN95 is "H" and CLKEN475 is "L", the upper 2-bit even data of the upper 4-bit data is format-converted into serial data and output as IMDATA2.
When both N95 and CLKEN 475 are "H", the lower 2 bits of the odd data are converted into serial data and output as IMDATA2, and thereafter, the respective operations are alternately performed. The LED head 503_
The format conversion of the data to be transferred to No. 3 is similar to the above, but the transfer start data is odd data.

Next, LPH1 in the CPLD 511 of FIG.
The control of the image data gamma correction unit 536_1 and LPH3 image data gamma correction unit 536_3 will be described with reference to FIG. FIG. 37 shows an LPH1 image data gamma correction unit (hereinafter simply referred to as “gamma correction unit”) 536_.
1 is a circuit diagram showing a configuration example of an LPH3 image data gamma correction unit (hereinafter simply referred to as “gamma correction unit”) 536_3. However, this circuit diagram shows one configured by a circuit group having both the function of the gamma correction unit 536_1 and the function of the gamma correction unit 536_3.

The gamma correction unit (γ correction unit) 536_1 is
Gamma correction (bit conversion) is performed on the image data to be transferred to the LED head 503_1. Gamma correction unit 53
6_3 performs gamma correction on the image data to be transferred to the LED head 503_3. Among them, gamma correction and bit conversion by the gamma correction unit 536_1 are performed as follows. Note that the gamma correction by the gamma correction unit 536_3 is also the same, so description thereof will be omitted.

The printer control circuit 504 uses the reference synchronization clock SYSCK and 5 set by the register unit 542.
Bit gamma correction data (2-bit data “0”
The “1” conversion data) GMDT1 and the 5-bit gamma correction data (2-bit data “1” “0” conversion data) GMDT2 are input to the data conversion circuit 726 of the gamma correction unit 536_1, and the format conversion unit 535 is input. 2-bit serial data IMDATA1, output from
IMDATA2 is converted into 5-bit data and output as GMMODAT1 and GMMODAT2. The 5-bit data GMMODAT1, GMMODAT2 or the test pattern TPDATA output from the data conversion circuit 726 is selected by the data conversion circuit 727 and output as GMMODAT1, GMMODAT2.

Next, LPH2 in the CPLD 511 of FIG.
The control of the image data gamma correction / joint light amount correction unit 536_2 will be described with reference to FIG. FIG. 38 shows
6 is a circuit diagram showing a configuration example of a LPH2 image data gamma correction / joint light amount correction unit (hereinafter referred to as “gamma correction / joint light amount correction unit”) 536_2 in the CPLD 511. FIG.
The gamma correction / joint light amount correction unit 536_2 performs gamma correction / joint light amount correction on the image data to be transferred to the LED head 503_2.

Here, the image effective range of the LED head 503_2 is fixed, and 258 dots on the left and right are blank areas with respect to the total number of dots of the LED head 503_2, 7680 dots, and the data transfer is divided into two. The divided portion is 3840 dots, and the leading effective pixel data to the LED head 503_2 corresponds to the 259th dot of the A block. The last effective pixel data to the LED head 503_2 corresponds to the 3582th dot of the B block (see FIGS. 18 and 19 to 21).

The printer control circuit 504 uses the reference synchronization clock SYSCK, the read main scanning image start signal RLSYNC from the CPLD 510, and the read image period signal R.
FGATE and the clock CLKEN95 generated by the transfer control unit 540 and the test pattern generation unit 541 are input to the joint light amount correction effective dot generation circuit 728 of the gamma correction / joint light amount correction unit 536_2 to perform the counting operation. . Joint light amount correction effective dot generation circuit 7
When the counter value reaches "259," 28 sets the joint light amount correction effective dot signal CNADAT1 to "H". Note that this joint light amount correction effective dot signal CNADAT1
Therefore, the joint light amount correction effective dot of the 2-bit data (A block data) IMDATA1 to the A block of the LED head 503_2 (the two dots located at the joint of the LED heads 503_1 and 503_2 corresponding to a part of the division position of the image data) LED head 503_ of the LEDs
(Corresponding to the LED on the second side) can be recognized.

When the count value reaches "3582", the joint light amount correction effective dot signal CNADAT2 is set to "H". It should be noted that this joint light amount correction effective dot signal CNADAT2 causes B of the LED head 503_2 to change.
2-bit data (B block data) IM to block
DATA2 Joint light amount correction effective dots (LED heads 503_2 and 5 corresponding to a part of the division position of the image data)
LE of the two LEDs located at the joint of 03_3
The bit data corresponding to the LED on the D head 503_2 side) can be recognized. Printer control circuit 504
Is a joint light amount correction effective dot signal CNADAT1, C
NADAT2, 5-bit gamma correction data GMDT1, GMDT2 set by the register unit 542, 5-bit joint light amount correction data ADJL1, 2, 3 similarly set by the register unit 542, and output from the format conversion unit 532. 2-bit data IMDATA1,
IMDATA2 and temperature data ONDO for temperature correction are input to the data conversion circuit 729.

The data conversion circuit 729 performs conversion processing on the 2-bit data IMDATA1, 2. That is, when the 2-bit data IMDATA1 is “0” or “0”, the 5-bit data indicating “0” is changed to GMMODAT1.
Output as. When the 2-bit data IMDATA1 is "1" or "1", 5-bit data indicating 32 values of 5-bit MAX is output as GMMODAT1. Two
When the bit data IMDATA1 is “0” or “1”,
The 5-bit gamma correction data GMDT1 set by the register unit 542 is selected and output as GMMODAT1. When the 2-bit data IMDATA1 is “1” or “0”, the 5-bit gamma correction data GMDT2 set in the register unit 542 is selected and output as GMMODAT1.

When the 2-bit data IMDATA2 is "0" or "0", 5-bit data indicating "0" is output as GMMODAT2. 2-bit data IM
When DATA2 is “1” or “1”, 5-bit data indicating 32 values of 5-bit MAX is output as GMMODAT2. 2-bit data IMDATA2 is "0"
In the case of "1", the 5-bit gamma correction data GMDT1 set in the register unit 542 is selected, and GMMOD
Output as AT2. 2-bit data IMDATA2
Is “1” or “0”, the 5-bit gamma correction data GMDT2 set in the register unit 542 is selected, and G
Output as MMODAT2. Data conversion circuit 729
5-bit data GMMODAT1, GM output from
The MODAT2 or test pattern TPDATA is
The data conversion circuit 730 allows the GCOMBD1, GCO
It is output as MBD2.

Here, in this embodiment, the dot spacing of the joint between the LED heads 503_1 and 503_2 or the dot spacing of the joint between the LED heads 503_2 and 503_3 becomes narrower so that the joint becomes brighter than its surroundings ( The amount of emitted light increases), and vertical black stripes may occur in the corresponding image. Therefore,
When such a vertical black stripe is generated, the register unit 54 is operated by a key operation on the operation panel 420 of the operation device 400.
From 2, it is assumed that there is a joint light amount correction mode. When the data conversion circuit 729 enters the joint light amount correction mode,
D head LED head 503_1, 503_2, 503
Output is performed based on the joint light amount correction data of ADJL1, 2, 3 set in the register unit 542 so that the light amount of the seam of _2 is corrected (so that vertical black stripes do not occur in the corresponding image). 5-bit data GMMODA that should be
A joint light amount correction process is performed on T1 and GMMODAT2.

LED heads LED heads 503_1 and 5
In the case of correcting the light amount of the joint 03_2, the joint light amount correction effective dot signal CNADAT1 generated by the joint light amount correction effective dot generation circuit 728 (the connection light amount correction effective dot of the A block data IMDATA1 of the LED head 503_2 is 25 bits of the input 2-bit data IMDATA1 by the signal indicating the corresponding bit data).
Attention is paid to the ninth dot so that the joint light amount correction data of ADJL 1, 2, 3 set in the register unit 542 can be varied by 5 bits. LED head LED head 5
When correcting the light amount of the joint between 03_2 and 503_3, the joint light amount correction effective dot signal CNADAT2 generated and output by the joint light amount correction effective dot generation circuit 728.
(B block data IMDA of the LED head 503_2
Input 2-bit data IMDAT by a signal indicating the bit data corresponding to the joint light amount correction effective dot of TA2)
Pay attention to the 3582th dot of A2, and register unit 542
The joint light amount correction data of ADJL1, 2, 3 set in step 5 is made variable by 5 bits.

Here, the joint light amount correction data of ADJL1, 2, 3 set in the register section 542 is input data "0""1","1""0","1", respectively.
Corresponding to "1", MAX32 value can be converted. Therefore, when black stripes are generated due to the narrowed dot interval at the joint between the LED heads 503_1 and 503_2, the input 2-bit data IMDATA at the 259th dot
If 1 is “1” and “1”, then 5 from the register unit 542.
By setting the bit joint light amount correction data ADJL3 to a small value (for example, half 5 bit 16 value) instead of the MAX32 value, the LED corresponding to the joint dot becomes dark (the emitted light amount decreases), and the corresponding image The black streaks on the screen are not noticeable. Similarly, if the input 2-bit data IMDATA1 of the 259th dot is “0” or “1”, the 5-bit joint light amount correction data ADJL1 is set. If the input 2-bit data IMDATA1 is “1” or “0”, the 5-bit joint light amount correction data ADJL2 is set. By setting each to a small value as described above, the LED corresponding to the joint dot becomes dark, and the black stripes in the corresponding image become inconspicuous.

When black streaks occur due to the narrowing of the dot intervals at the joints of the LED heads 502_2 and 503_3, the input 2-bit data I of the 3582th dot is obtained.
If MDATA2 is “1” or “1”, the register unit 54
5-bit joint light amount correction data ADJL3 from 2 is M
By using a small value instead of the AX32 value, the LED corresponding to the joint dot becomes dark, and the black streak in the corresponding image becomes inconspicuous. Similarly, if the input 2-bit data IMDATA2 of the 3582th dot is "0" or "1", the 5-bit joint light amount correction data ADJL1 is changed to "1".
If "0", 5-bit joint light amount correction data ADJL
By setting 2 to the same small value as above respectively,
The LED corresponding to the joint dot becomes dark, and the black streak in the corresponding image becomes inconspicuous.

Here, such adjustment is performed in a factory under temperature control during the manufacturing process, but in an environment where this digital copying machine is actually used, each LED head is subject to fluctuations in ambient temperature and self-heating. 503_1, 503_
The joint dot interval between 2, 503_3 changes. Therefore, the temperature correction is further applied to the seam light amount correction data converted by 5 bits. That is, temperature data is ON
Since the DO is sequentially sent from the printer control circuit 504, the 5-bit joint light amount correction data ADJL1, 2, 3 set in the register unit 542 for each print is read, and those values are indicated by the temperature data ONDO. Every time the (detection temperature) rises by 10 ° C., it is decreased by 1/32.

The joint light amount correction and the temperature correction described above are performed at both ends of the effective image area of the LED head 503_2 (the LED on the LED head 503_2 side of the two LEDs located at the joint between the LED heads 503_1 and 503_2). And corresponding to the bit data corresponding to the LED on the LED head 503_2 side of the two LEDs respectively located at the joint between the LED heads 503_2 and 503_3), as well as for the effective image area of the LED head 503_1. One end (LED heads 503_1 and 503_
Bit data corresponding to the LED on the LED head 503_1 side of the two LEDs located at the second joint and one end of the effective image area of the LED head 503_3 (LE
2 located at the joint between D heads 503_2 and 503_3
LE on the LED head 503_3 side of the LEDs
It is also possible to perform it on the bit data corresponding to D).

Next, the control of the P sensor output section 537 and the image data / light quantity correction data selection section 538 in the CPLD 511 of FIG. 9 will be described with reference to FIG. FIG. 39 shows the P sensor output unit 53 in the CPLD 511.
7 is a circuit diagram showing a configuration example of an image data / light amount correction data selection unit (hereinafter simply referred to as “select unit”) 538. FIG. However, this circuit diagram shows the P sensor output unit 537.
It is shown that it is configured by a circuit group having both the function of (1) and the function of the selection unit 538.

When the power is turned on, the printer control circuit 504
Causes the mode switching signal KHSEL to be input to the selector circuit 732 that constitutes the selection unit 538, and the LED head 5
03_1 to 503_3 dot-based and chip-based light amount correction data and a gate signal as the light amount correction data and gate signal from the image information storage device 300, or the light amount correction from the light amount correction ROM controlled by the light amount correction ROM read control unit 543. Data and gate signals are selected and output. Also, the process conditions, the P sensor enable signal generated for the toner density output, and the LED head 503
The A block data of _2 is input to the selector circuit 731, and both are output as output data PSOD.

Further, the light amount correction data output from the selector circuit 732, the light amount correction gate signal, the image data from the gamma correction / joint light amount correction unit 536_2, and the image data from the gamma correction units 536_1 and 536_3 are collected. It is input to the selector circuit 733, and the light amount correction mode and the normal image data transfer (gradation mode) are switched by the mode switching signal KHENBL and output to the LED heads 503_1 to 503_3.

Next, the control of the LPH strobe output control section 539 in the CPLD 511 of FIG. 9 will be described with reference to FIGS. 40 and 41. FIG. 40 shows the CPLD 51.
3 is a circuit diagram showing a configuration example of an LPH strobe output control unit (hereinafter simply referred to as “strobe output control unit”) 539 in FIG. FIG. 41 is a timing chart showing the operation of the strobe output control section 539.

The strobe output control unit 539 generates a lighting pulse signal for lighting the LED heads 503_1 to 503_3. LED heads 503_1 to 503
The lighting method of _3 reduces the burden on the power source, so the main scan 1
This is a method (LED head four-division lighting method) in which five bits of data for a line are latched and then output by outputting four signal lines in order based on a clock lighting period for 32 counts set from the main scanning period. Then, the image is printed.

The printer control circuit 504 first determines the CPL.
The image start signal RLSYNC and the reference synchronization signal SYSCK generated by D510 are input to the counter circuit 736 and counted up, and the counter signal STBWD indicating the count value is output. Counter signal STBWD
Is an internal counter signal indicating the count value for one clock of the lighting strobe output to the LED head. The counter circuit 736 is reset by the STB cycle signal STBCYC indicating the cycle of one strobe clock set in the register unit 542.

Further, the intermediate count value period signal S indicating the period of the intermediate count value by the STB cycle signal STBCYC.
TBDTY is set similarly to the STB cycle signal STBCYC, and combined with the counter signal STBWD, the intermediate enable signal STBWDDT for one strobe clock is generated.
Y is generated and output. Next, 1 clock cycle signal STB
WDCYC (STBWD = STBCYC) is input to the counter circuit 737, and the counter signal ST
Output BCNT. When the counter circuit 737 is reset, the count value indicated by the counter STBCNT is “31”.
It is performed when it reaches (count from "0" to "31").

Next, the counter signal STBCNT indicating the count value "31" is input to the counter circuit 738, and the counter signal STBBLK is output based on the signal.
The counter circuit 738 is reset by the counter signal STB.
It is performed when the count value indicated by BLK reaches "3".
Next, the counter signal STBBL indicating the count value "3"
K and the read main scan image start signal RLSYNC generated by the CPLD 510 are supplied to the main scan STB period generation circuit 73.
9 and outputs the STB period signal STBLEN indicating the strobe signal period in one main scanning line.

Further, the STB period signal ST indicating the sub-scanning strobe period is generated by the sub-scanning STB period generation circuit 740.
Generate and output BFEN. Then, the counter circuit 73
6 to 738, the main scanning STB period generation circuit 739, and the sub-scanning STB period generation circuit 740
It is input to the clock generation circuit 741 and the four strobe clocks STBCLK0 to STBCLK3 are sequentially output. Here, the setting of the STB cycle signal STBCYC indicating the cycle of one strobe clock and the intermediate count value period signal STBDTY indicating the period of the intermediate count value will be described.

The lighting time (light emitting time) of the LED heads 503_1 to 503_3 is 8% to 15% of the main scanning period.
%. Assuming that the lighting time is 10%, the main scanning period is 470.3 μsec, and the main scanning period is 47.03 μsec.
Is the strobe clock cycle, which includes 32 clocks. The period of one clock is 47.03 μsec /
It is 1.47 μsec in 32 clocks. The reference synchronization clock SYSCK is 19 MHz and 0.052 μs
Since it is a period of ec, the period of one clock is 1.47 μsec.
Becomes 28 counts of the reference synchronization clock SYSCK (counter signal STBWD is 0 to 27 counts).

Therefore, the set value corresponding to the cycle of one strobe clock indicated by the STB cycle signal STBCYC is "27", and the set value corresponding to the period of the intermediate count value indicated by the intermediate count value period STBDTY is "13". Become. Using the control described above, the LED heads 503_1 ...
Pulse control of the lighting time of each LED of 503_3 (PWM
By performing the control), the amount of light emitted from each LED can be adjusted in 32 steps. Therefore,
One or both of the two LEDs located at the joint between the LED heads 503_1 and 503_2, or LE
2 located at the joint between D heads 503_2 and 503_3
By performing pulse control of the lighting time of one or both of the individual LEDs, it is possible to correct the amount of light emitted from that LED in 32 steps.

The LED heads 503_1 to 503_
L of each internal circuit (see FIG. 11) provided in each
The emitted light amount signal (reference voltage) Vref, which determines the value of the current flowing through the ED, can be individually adjusted via a D / A converter (not shown).
The amount of light emitted from each LED can also be adjusted steplessly by controlling the current flowing through the LED. Therefore,
One or both of the two LEDs located at the joint between the LED heads 503_1 and 503_2, or LE
2 located at the joint between D heads 503_2 and 503_3
By controlling the value of the current flowing through one or both of the individual LEDs, the amount of light emitted from each LED can be corrected steplessly.

[0154]

As described above, according to the present invention, the image writing device is not constituted by one light emitting element array unit (high cost and wide width light emitting element array unit), but A plurality of light emitting element array units arranged in a zigzag pattern along the axial direction (main scanning direction) of the photoconductor (light emitting element array unit of small width and low cost)
The image information can be divided and transferred for each light emitting element array unit by the division transfer control means, and further according to the temperature detected by the temperature detecting means provided inside or in the vicinity of each light emitting element array unit, Located at the joint of each light emitting element array unit corresponding to a part or all of the division position of the image information by the division transfer control means 2
Since the amount of emitted light of one or both of the individual light emitting elements is corrected by the light amount correction means, it is possible to prevent uneven light amount at the joint position of each light emitting element array unit due to temperature fluctuation. Therefore, it is possible to reliably obtain a high-quality image even by the division exposure of the photosensitive layer to the photosensitive layer by the plurality of light emitting element array units.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration example of a digital copying machine embodying the present invention.

FIG. 2 is a schematic configuration diagram showing an example of a mechanical section of the image reading apparatus 100 of FIG.

3 is a schematic configuration diagram showing an example of a mechanical section of a copying machine main body 200 of FIG.

FIG. 4 is a layout diagram showing a configuration example of an operation panel 420 of FIG.

5 is a block diagram for explaining a flow of entire image data in the digital copying machine of FIG.

6 is a block diagram showing a configuration example of the first half of the LED writing control circuit 501 of FIG. 1. FIG.

FIG. 7 is a block diagram showing a configuration example of the latter half of the same.

8 is a block diagram showing a configuration example of CPLD 510 (CPLD1) in FIG.

9 is a block diagram showing a configuration example of a CPLD 511 (CPLD2) in FIG.

10 is a block diagram showing a configuration example of an LED head 503_1 in FIG.

11 is a block diagram showing a configuration example of an internal circuit of the driver IC 531_1 and LED of FIG.

12 is a circuit diagram showing a configuration example of a data input thinning unit 521 of FIG.

FIG. 13 is a circuit diagram showing a configuration example of a signal selection unit 520 in the same manner.

FIG. 14 is a circuit diagram showing a configuration example of a test pattern generator 522.

FIG. 15 is a circuit diagram showing a configuration example of a selector section 523.

FIG. 16 is a circuit diagram showing a configuration example of a double copy control unit 519.

17 is a timing diagram showing an operation of the double copy control unit 519 shown in FIG.

FIG. 18 is a diagram showing the LED heads 503_1 to 503_ of FIG.
It is explanatory drawing for demonstrating the image area of 3.

FIG. 19 is a schematic diagram of the six A-group SRAMs 514A_1 (S in FIG. 6;
RAM1), 514A_2 (SRAM2), and SRAMs 514B_1 (SRAM1) and 514B_2 with six B groups
The sequence of writing data to (SRAM2) and reading the data and the LED head 503_1 (LPH
It is an explanatory view for explaining the data transfer direction to each LED and SRAM address of 1).

FIG. 20 is a diagram showing the six SRAMs 514A_3 (S in FIG.
RAM3), 514A_4 (SRAM4), and SRAMs 514B_3 (SRAM3) and 514B_4 with six B groups
The order of writing data to and reading data from (SRAM4) and LED head 503_2 (LPH
It is explanatory drawing for demonstrating the data transfer direction to each LED of 2), and SRAM address.

FIG. 21 is a diagram showing the six SRAMs 514A_5 (S in FIG.
RAM5), 514A_6 (SRAM6), and SRAMs 514B_5 (SRAM5) and 514B_6 having six B groups
The order of writing data to and reading data from (SRAM 6) and LED head 503_3 (LPH
It is explanatory drawing for demonstrating the data transfer direction to each LED of 3), and SRAM address.

22 is a circuit diagram showing a configuration example of a block switching control unit 524 in FIG.

FIG. 23 is a circuit diagram showing a configuration example of an SRAM write controller 525.

FIG. 24 is a circuit diagram showing a configuration example of an SRAM read control unit 526.

FIG. 25 is a circuit diagram showing a configuration example of a write pulse generator 527.

FIG. 26 is a circuit diagram showing a configuration example of an address selector unit 528.

27 is a timing chart showing the operation of the write pulse generator 527 of FIG. 25 and the address selector 528 of FIG. 26.

28 is a circuit diagram showing a configuration example of a data format conversion unit 518 in FIG.

FIG. 29 is also a field memory write control unit 52.
It is a circuit diagram which shows the structural example of 9.

FIG. 30 is a circuit diagram showing a configuration example of a register unit 530.

31 is a circuit diagram showing a configuration example of a transfer control unit 540 and a test pattern generation unit 541 of FIG.

FIG. 32 is also a light amount correction ROM read control unit 543.
3 is a circuit diagram showing a configuration example of the first half of FIG.

FIG. 33 is a block diagram showing a configuration example of the latter half of the same.

FIG. 34 is a circuit diagram showing a configuration example of a field memory (FM) read control unit 531 in the same manner.

[FIG. 35] Similarly, LPH1 image data input selection unit 5
34 and LPH1 image data format conversion unit 53
5 is a circuit diagram showing a configuration example of FIG.

FIG. 36 is a circuit diagram showing a configuration example of an LPH2,3 image data format conversion unit 532 of the same.

FIG. 37 is also an LPH1 image data gamma correction unit 53
6_1 is a circuit diagram showing a configuration example of an LPH3 image data gamma correction unit 536_3.

FIG. 38 is a circuit diagram showing a configuration example of an LPH2 image data gamma correction / joint light amount correction unit 536_2.

39 is a circuit diagram showing a configuration example of a P sensor output section 537 and an image data / light quantity correction data selection section 538. FIG.

FIG. 40 is a circuit diagram showing a configuration example of an LPH strobe output control section 539, similarly.

41 is a strobe output control unit 539 shown in FIG.
6 is a timing chart showing the operation of FIG.

[Explanation of symbols]

100: Image reading device 200: Copier main body 300: Image information storage device 301: Image memory unit 400: Operating device 410: Operation control circuit 420: Operation panel 500: Printer device 501: LED writing control circuit 502: LED head control Circuit 503 (503_1 to 503_3): LED head 504: Printer control circuit 510, 511: CPLD 518: Data format conversion unit 519: Double copy control unit 520: Signal selection unit 521: Data input thinning unit 522: Test pattern generation unit 523: Selector unit 524: Block switching control unit 525: SRAM write control unit 526: SRAM read control unit 527: Write pulse generation unit 528: Address selector unit 529: Field memory write control units 530 and 542: Register unit 31: Field memory read control unit 532: LPH2,3 image data format conversion unit 534: LPH1 image data input selection unit 535: LPH1 image data format conversion unit 536_1: LPH1 image data gamma correction unit 536_2: LPH2 image data gamma correction / connection Eye light amount correction unit 536_3: LPH3 image data gamma correction unit 537: P sensor output unit 538: Image data / light amount correction data selection unit 539: LPH strobe output control unit 540: Transfer control unit 541: Test pattern generation unit 543: Light amount correction ROM read control unit

Continued front page    F-term (reference) 2C162 AE21 AE28 AE47 AF07 AF13                       AF29 AF60 AF70 AF71 AF86                       FA04 FA17 FA45 FA50                 5C051 AA02 CA08 DA04 DB02 DB22                       DB29 DC02 DC05 DE04 DE30                       FA01                 5C072 AA03 BA17 HA01 HB04 XA04

Claims (4)

[Claims] 1. A plurality of light emitting elements for writing image information on a photoconductor are arranged in an array at a predetermined density in a main scanning direction orthogonal to a sub-scanning direction which is a rotating direction of the photoconductor. In the image writing device having a plurality of light emitting element array units arranged in a zigzag pattern in the main scanning direction and dividing and transferring the image information for each of the light emitting element array units, Temperature detecting means is provided inside or in the vicinity of the element array unit, and each of the light emitting element arrays corresponding to a part or all of the division position of the image information by the division transfer control means according to the temperature detected by the temperature detecting means. An image writing apparatus comprising: a light amount correction unit that corrects the light emission amount of one or both of the two light emitting elements located at the joint of the units. 2. The image writing apparatus according to claim 1, wherein the light amount correction unit is a unit that corrects the light emission amount by controlling the light emission time of one or both of the two light emitting elements. An image writing device characterized by the above. 3. The image writing apparatus according to claim 1, wherein the light amount correction unit corrects the emitted light amount by controlling the amount of current flowing through one or both of the two light emitting elements. An image writing device characterized by: 4. An image forming apparatus comprising the image writing device according to claim 1, wherein the image writing device is used to perform image formation.