JP2003070246A - Dc-to-dc converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a DC-to-DC converter which prevents increase of the number of insulated circuits for transmitting control information from the primary side to the secondary side, prevents the circuits from being complicated, and makes it unnecessary to use the insulated circuits for transmitting information on primary-side states to the secondary side. SOLUTION: A constant voltage control circuit 201 outputs a switching pulse width signal for a switching TR 109 so that secondary-side voltage becomes constant. If a main control circuit 205 receives a DATA request signal from outside, a driver circuit 208 changes a pulse amplitude and transmits a transmission request signal to the primary side. When a transmission request detector 210 detects the transmission request, a transmission control circuit 213 converts the parallel outputs of a monitor circuit 214 into a serial. An on-time changeover circuit 212 modulates the pulse width of a switching timing signal according to the serial data, and transmits it to the secondary side.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DCDC converter for converting a DC voltage on the primary side into a DC voltage on the secondary side, and more particularly to a DCDC converter in which the primary side and the secondary side are insulated. D with improved transmission of control information between secondary and secondary
It relates to a CDC converter.

[0002]

2. Description of the Related Art In a hybrid car that uses both an engine and an electric motor, or in an electric car that uses an electric motor, a main battery serving as a power source for driving the motor has a high voltage to reduce the current flowing through the motor. is doing.
By doing so, power loss due to electrical resistance is reduced and power efficiency is improved. However, the electrical components and accessories used in these vehicles (hereinafter collectively referred to as “auxiliaries”) have a proven track record in manufacturing and are supplied at a low cost from the conventional 12V.
Auxiliary equipment is often used, and a 12V battery for driving the auxiliary equipment is mounted in addition to the main battery. And 12V
In order to charge the battery and supply power to auxiliary equipment,
D that converts the high voltage of the main battery into a low voltage for driving auxiliary equipment
A CDC converter is provided.

In the above vehicle, in order to avoid an electric shock due to a high voltage of the main battery, in the DCDC converter, the high voltage primary side and the low voltage secondary side are insulated by a transformer and have a common potential. It is designed so that it does not exist.

As a conventional technique relating to such a DCDC converter in which the primary side and the secondary side are insulated from each other, there is known a "switching power supply device" described in JP-A-6-245505. According to this conventional technique, the voltage applied to the primary winding of the transformer is turned on and off by the switching element, the switching current induced in the secondary winding of the transformer is rectified and smoothed, and a DC voltage is supplied to the load side. is doing.

At this time, a signal related to the output voltage on the secondary side is digitized by an A / D converter, and a pulse train signal obtained by parallel / serial converting this digital signal is passed from the secondary side to the primary side via an insulating circuit such as a photocoupler. To the side. On the primary side, the pulse train is converted to a digital signal related to the secondary side output voltage by serial / parallel conversion,
By comparing this digital signal with the reference voltage value and controlling the switching element on the primary side according to the comparison result, a stabilized secondary side DC voltage is obtained.

Further, it is judged whether or not the DC voltage on the secondary side is an excessive voltage, and if it is excessive, an excessive output detection flag is transmitted to the primary side to switch the primary current by the switching element. The circuit is protected by stopping. The excessive output detection flag is transmitted to the primary side by the same transmission system as the pulse train signal indicating the DC voltage.

[0007]

However, in the above-mentioned conventional technique, the data indicating the output DC voltage value from the secondary side to the primary side and the flag indicating whether or not the DC voltage output to the load side is excessively large. However, there is a problem that the transmission data becomes long, the transmission takes time, and the circuit for that becomes complicated.

Further, when the number of abnormalities or failures to be detected increases, the serial data to be transmitted becomes longer and the circuit becomes more complicated.

In view of the above problems, an object of the present invention is to provide a DCDC converter which can shorten the time for transmitting control information from the primary side to the secondary side and can prevent the circuit from becoming complicated. It is in.

[0010]

The invention according to claim 1 is
In order to achieve the above object, the voltage applied to the primary winding of the transformer is turned on / off by a switching element, the switching current induced in the secondary winding of the transformer is rectified and smoothed, and a DC voltage is applied to the load side. A power conversion unit to be supplied, a constant voltage control circuit that generates a first switching timing signal according to a comparison result of an output voltage of the power conversion unit and a reference voltage, and a first switching timing signal that is isolated from each other. An insulation circuit that transmits as a second switching timing signal from the secondary side to the primary side, a state detection circuit that detects the state of the primary side and outputs a state signal, and a timing that the second switching timing signal indicates A switching control circuit for controlling ON / OFF of the switching element by changing according to the state signal; and a first switching timing signal. 2 associated signal and said transformer
A DCDC converter having a signal determination circuit for determining a transmission signal from the primary side to the secondary side based on comparison with a signal related to a voltage waveform induced on the secondary side.

According to a second aspect of the present invention, in order to achieve the above object, in the DCDC converter according to the first aspect, the output of the state detection circuit is an overvoltage detection signal indicating an overvoltage on the primary side, and a primary side. The low-voltage detection signal indicating the low voltage and the overcurrent detection signal indicating the overcurrent on the primary side are included.

According to a third aspect of the present invention, in order to achieve the above object, in the DCDC converter according to the first or second aspect, the first switching timing signal is amplitude-modulated, and the first switching timing signal is first modulated from the secondary side. The gist is to have a signal to be transmitted to the next side.

In order to achieve the above object, the invention according to claim 4 is the DCDC converter according to claim 3, wherein the signal transmitted from the secondary side to the primary side is a state signal of the primary side. It is a transmission request signal for requesting transmission to the secondary side, and the gist is that a plurality of status signals are serially transmitted from the primary side to the secondary side according to the transmission request signal.

According to a fifth aspect of the invention, in order to achieve the above object, in the DCDC converter according to any one of the first to fourth aspects, a motor driving inverter is provided on the primary side. The switching timing change by the switching control circuit is used for transmission from the driver unit of the motor driving inverter to the secondary side, and the amplitude of the first switching timing signal is transmitted for transmission from the secondary side to the driver unit. The point is to use modulation.

In order to achieve the above object, the invention according to claim 6 is characterized in that, in the DCDC converter according to claim 5, the output of the state detection circuit includes a power supply confirmation signal of the driver unit. .

According to a seventh aspect of the invention, in order to achieve the above object, in the DCDC converter according to the fifth aspect, a signal transmitted from the secondary side to the driver unit is smoothed from a primary side power source. The gist of the present invention is to include either or both of a discharge command signal for the smoothing capacitor and an enable signal for enabling the inverter operation of the driver unit.

[0017]

According to the first aspect of the invention, the voltage applied to the primary winding of the transformer is turned on / off by the switching element, and the switching current induced in the secondary winding of the transformer is rectified and smoothed. And a constant voltage control circuit for generating a first switching timing signal in accordance with a comparison result between an output voltage of the power converter and a reference voltage; An insulating circuit for insulating a timing signal and transmitting it as a second switching timing signal from the secondary side to the primary side;
A state detection circuit that detects the state of the next side and outputs a state signal; and a switching control circuit that controls the ON / OFF of the switching element by changing the timing indicated by the second switching timing signal according to the state signal. ,
A signal determination circuit for determining a transmission signal from the primary side to the secondary side based on a comparison between a signal related to the first switching timing signal and a signal related to a voltage waveform induced on the secondary side of the transformer. With the provision of (1) and (2), it is possible to shorten the time for transmitting the status signal from the primary side to the secondary side and prevent the circuit from becoming complicated.

According to a second aspect of the present invention, the output of the state detection circuit is an overvoltage detection signal indicating an overvoltage on the primary side, a low voltage detection signal indicating a low voltage on the primary side, and an overvoltage detection on the primary side. Since at least one of the overcurrent detection signals indicating the current is included, in addition to the effect of the invention according to claim 1, when at least one of the primary side overvoltage, the low voltage, and the overcurrent occurs, There is an effect that appropriate processing can be performed on the secondary side.

According to the third aspect of the present invention, the first switching timing signal is amplitude-modulated to have a signal to be transmitted from the secondary side to the primary side. In addition to the effect of the invention described in item 2, there is an effect that information can be transmitted from the primary side to the secondary side without changing the switching timing that affects the secondary side DC voltage.

According to the fourth aspect of the present invention, the signal transmitted from the secondary side to the primary side is the state signal of the primary side is 2
A transmission request signal requesting transmission to the secondary side, and a plurality of status signals are serially transmitted to the secondary side in response to the transmission request signal. Thus, there is an effect that a plurality of primary side status signals can be transmitted to the secondary side in response to the request from the secondary side.

According to the invention of claim 5, a motor driving inverter is provided on the primary side, and the switching control circuit is used for transmission from the driver unit of the motor driving inverter to the secondary side. 5. The switching timing change is used, and the amplitude modulation of the first switching timing signal is used for transmission from the secondary side to the driver unit.
In addition to the effects of the described invention, the status signal of the system that drives the motor using the high voltage battery as the power source
There is an effect that transmission can be performed without providing an insulating circuit to the next side.

According to the invention of claim 6, the output of the state detection circuit includes a power supply confirmation signal of the driver unit. Therefore, in addition to the effect of the invention of claim 5, Power supply confirmation signal from primary side to 2
There is an effect that transmission can be performed without providing an insulating circuit to the next side.

According to the seventh aspect of the present invention, the signal transmitted from the secondary side to the driver unit includes a smoothing capacitor discharge command signal for smoothing the primary side power source or an inverter operation of the driver unit. Since either or both of the enable signals that are enabled are included, the discharge command signal or the enable signal of the smoothing capacitor is insulated from the secondary side to the primary side in addition to the effect of the invention of claim 5. There is an effect that transmission can be performed without providing a circuit.

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 shows a DC according to the present invention.
It is a circuit block diagram explaining 1st Embodiment of a DC converter. In the figure, the DCDC converter 101 according to the present embodiment converts the voltage of the main battery 103, which is the primary side, into the voltage of the auxiliary battery 115, which is the secondary side, and supplies the load 114 with the auxiliary battery. The power conversion unit 102 for charging 115 is provided.

The voltage of the main battery 103 is not particularly limited, but in the case of an electric vehicle or a hybrid vehicle,
It is a high voltage of several hundred volts, and the voltage of the auxiliary battery is, for example, 12V or 24V. And the primary side and 2
The secondary side is the isolation transformer 106 and the pulse transformer 20.
Are insulated by 9 and each have a different reference potential (GN
D).

The primary winding 107 of the insulation transformer 106 of the power converter 102 has one end connected to the + HV terminal 104 to which the positive electrode of the main battery 103 is connected, and the other end connected to the drain of the transistor (Tr) 109. ing. The source of the transistor (Tr) 109 is a shunt resistor 24.
1 is connected to the high-voltage side ground. The gate of the transistor 109 is connected to the output of an on-time switching circuit 212 described later and is on / off controlled.

The secondary winding 108 of the isolation transformer 106 is
It is connected to the rectifying unit 110, and the output of the rectifying unit 110 is connected to the smoothing unit 111. The switching current induced in the secondary winding 108 is rectified by the rectification unit 110, smoothed by the smoothing unit 111, and supplies a DC voltage to the load 114 and the auxiliary battery 115 via the output terminal (Vo) 112.

Further, the DCDC converter 101 operates a constant voltage control circuit 201 for generating a switching timing signal so that the voltage on the secondary side becomes a constant value, and an amplitude of the switching timing signal output by the constant voltage control circuit 201. From the switching timing signal, the driver circuit 208 that sends a transmission request from the secondary side to the primary side, the pulse transformer 209 that insulates the switching timing signal output from the driver circuit 208 from the secondary side to the primary side, and the switching timing signal. Transmission request detection path 21 for detecting transmission request
0, a limiter circuit 211 that limits the amplitude of the switching timing signal to generate a drive signal, an on-time switching circuit 212 that sends an on-off drive signal to the transistor 109, and switches the on-time under the control of the transmission control circuit 213. , A transmission control circuit 213 that serializes the status signal on the primary side detected by the monitoring circuit 214 based on the enable signal 218 output by the transmission request detection circuit 210 and sends the serialized status signal to the on-time switching circuit 212; A monitoring circuit 214 that detects an overvoltage, an undervoltage, and an overcurrent of the main battery 103, and notifies the transmission control circuit 213 of them.
And a main control circuit 205 for controlling the entire DCDC converter 101.

The constant voltage control circuit 201 divides the secondary side DC output voltage by the voltage dividing circuit 202 and the reference voltage circuit 2
03 is compared with the reference voltage generated by the control circuit 03, and a switching timing signal whose pulse width corresponding to the ON time of the transistor 109 is controlled is generated according to the comparison result.
The start of the generation of this switching timing signal is
It is controlled by an activation signal externally applied to the activation terminal 204.

Further, the main control circuit 205 receives the data from the primary side, performs serial / parallel conversion, and outputs DATA0 to DATA0 to the outside.
The OR circuit 242 outputs a signal that needs to stop the DCDC converter 101 from the primary side state signal output as n.
Then, the logical sum is taken, and the switching timing signal output of the constant voltage control circuit 201 is stopped by using the logical sum result as a stop signal.

The main control circuit 205 uses DA from an external device.
An En input to which the TA request flag 237 is input, an Rx input to which the output voltage pulse of the transformer isolation transformer 106 is input from the output of the rectification unit 110 via a limiter circuit 207, and a switching timing signal output from the constant voltage control circuit 201. Are input via the delay circuit 206 as an operation clock, and DATA0 to DATA0 for converting the serial data string input to the Rx input into parallel and outputting it.
DATAn output, Req output that outputs a transmission request to the driver circuit 208, and E that outputs reception end to another C / U
An nd output and an Err output for outputting an error flag 236 indicating whether or not the reception is normally performed from the primary side through the isolation transformer 106 are provided.

Further, the main control circuit 205 receives the data from the primary side, performs serial / parallel conversion, and outputs DATA0 to DATA0 to the outside.
The OR circuit 242 outputs a signal that needs to stop the DCDC converter 101 from the primary side state signal output as n.
Then, the logical sum is taken, and the switching timing signal output of the constant voltage control circuit 201 is stopped by using the logical sum result as a stop signal.

The delay circuit 206 is a constant voltage control circuit 201.
Is a circuit in which a time longer than the wiring delay and the circuit element delay from the output of the switching timing signal from the output to the appearance of the output voltage on the secondary side of the isolation transformer 106 is set, and the isolation transformer from the primary side to the secondary side is set. A sampling clock of information transmitted by the switching pulse width modulation 106 is output to the main control circuit 205.

The limiter circuit 207 is a circuit that limits the output amplitude of the insulating transformer 106 rectified by the rectifying unit 110 at a logical level.

The driver circuit 208 is a constant voltage control circuit 2
The pulse transformer 209 is driven according to the pulse train of the switching timing signal output by 01. When the main control circuit 205 outputs a transmission request from the Req output, only the output voltage value is changed without changing the timing of the switching timing signal. By changing it, the pulse train for stabilizing the output voltage output from the constant voltage control circuit 201 includes the transmission request signal and outputs it. The internal configuration of the driver circuit 208 is the AND circuit 23 of logic elements.
2 and an AND circuit 233, an inverter 234, and transistors 230 and 231 having an emitter follower configuration driven by the AND circuits 232 and 233, respectively.

The power source V is applied to the collector of the transistor 230.
ccA228 is supplied, the power supply VccB229 is supplied to the collector of the transistor 231, and VccA <Vc.
There is a voltage relationship of cB.

The output pulse of the constant voltage control circuit 201 is input to one input of each of the AND circuit 232 and the AND circuit 233, and the transmission request signal inverted by the inverter 234 is input to the other input of the AND circuit 232. , A
The transmission request signal is directly input to the other input of the ND circuit 233. Then, the transistors 230 and 23
The respective emitters of 1 are both connected to the primary side input of the pulse transformer 219.

Therefore, when there is no request for transmission, the transistor 230 repeats ON / OFF in synchronization with the pulse train output from the constant voltage control circuit 201, whereby VccA2.
The output pulse of the voltage of 28 is output, and when there is a transmission request, the transistor 231 is turned on / off to set V
The circuit configuration is such that an output pulse of the voltage of ccB229 is output. Thereby, the transmission request is transmitted from the primary side to the secondary side by changing the amplitude of the switching timing signal without changing the timing or pulse width of the switching timing signal sent from the primary side to the secondary side. be able to.

The transmission request detection circuit 210 compares the voltage of the switching timing signal 220 output to the primary side while being insulated from the secondary side, which is the transmission side, via the pulse transformer 209 and the reference voltage 227 to the comparator 226. And the voltage of the switching timing signal 220 exceeds the reference voltage 227, the transmission request signal is detected. This transmission request signal is subjected to noise removal by the filter circuit 225, and then the latch 224 is set. The output Q of the latch 224 becomes an enable signal 218 for permitting transmission to the transmission control circuit 213, and the transmission control circuit 213 sends a reset signal 217 for resetting the latch 224 when the transmission is completed.

The limiter circuit 211 is the pulse transformer 2
This is an amplitude limiting circuit that limits the amplitude of the output 220 of 09 to the logical amplitude and outputs it as the drive signal 216.

The transmission control circuit 213 converts the parallel monitoring information of the monitoring circuit 214 on the primary side into a serial data string in synchronization with the drive signal 216 to convert the on-time switching circuit 2 into a serial data string.
The output signal is output to 12 and its internal configuration will be described with reference to FIG.

The counter 250 shown in FIG.
The number of bits to be transmitted is counted by counting the pulse train input to the enable input En21.
When 8 is Low, the count value is reset and output (ou
t) becomes Low, and the enable input En218 is Hi.
It is a counter that performs a counting operation when it is gh, and outputs High to the End output 217 when a predetermined number of pulses are counted. The P / S register 251 receives the input n
Bit parallel data 255 is held (LOAD) in the P / S register 251 at the rising edge of the En signal 218,
It is a parallel-serial conversion register that outputs the data held in synchronization with the ck216 signal while sequentially performing the shift operation. The AND circuit 258 outputs P / from the OUT output 215 when the En signal 218 becomes High level.
The AND circuit 258 is a logic gate capable of outputting the serial data of the S register 251, and the AND circuit 258 outputs the operation clock from the ck input 216 to the counter 250 and P when the En signal 218 is High level and the output (out) of the counter 250 is Low level. It is supplied to the / S register 251.

With the configuration of FIG. 2, the En input 218 becomes High.
When it reaches h, the P / S register 251 outputs a serially converted data string up to a predetermined number of bits, and when the predetermined number of bits is counted, the clock supply from the ck input 216 is stopped to control the operation of the circuit. ing. When the logic level of the N-th bit connected in parallel is High, the N-th logic output output from the P / S register 251 is High.

Referring again to FIG. The on-time switching circuit 212 turns on / off the primary side of the isolation transformer 106.
A circuit that controls the on-time of the transistor 109 that is turned off. The delay circuit 223, the AND circuit 221, and the OR circuit 2
It consists of 22. One input of the OR circuit 222 is connected to the drive signal 216 and unconditionally outputs the drive signal 216 to drive the transistor 109. At the other input of the OR circuit 222, the logical product A of the serial signal of the transmission control circuit 213 and the drive signal delayed by the delay circuit 223 is taken.
The output of the ND circuit 221 is input. By this on-time switching circuit 212, when the serial output of the transmission control circuit 213 is Low, the on-time of the transistor 109 is the same time as the drive signal 216 if the wiring delay on the circuit is ignored, and the serial time of the transmission control circuit 213 is When the output is High, the ON time becomes longer by the delay time of the delay circuit 223.

The monitoring circuit 214 divides the + HV 104 and outputs a voltage monitor signal, and outputs an overvoltage detection signal to the transmission control circuit 213 when the voltage monitor signal exceeds the first predetermined voltage. Overvoltage detection circuit 238, a low voltage detection circuit 239 that outputs a low voltage detection signal to the transmission control circuit 213 when the monitor voltage signal falls below the second predetermined voltage, and the source current of the transistor 109 exceeds a predetermined value. And an overcurrent detection circuit 240 that outputs an overcurrent detection signal to the transmission control circuit 213 when

FIG. 3 is a detailed circuit diagram for explaining the details of the monitoring circuit 214. In the figure, the monitoring circuit 214 is
It includes a voltage dividing resistor 234, an overvoltage detection circuit 238, a low voltage detection circuit 239, and an overcurrent detection circuit 240.

The voltage dividing resistor 234 divides the high voltage of the main battery 103 to a voltage close to the logic voltage and outputs the voltage monitor signal as an overvoltage detection circuit 238 and a low voltage detection circuit 239.
And output to.

The overvoltage detection circuit 238 compares the voltage (HV) of the reference voltage source 244 generating the first predetermined voltage with the voltage of the voltage monitor signal, and the voltage of the voltage monitor signal is HV.
When the voltage exceeds, the overvoltage signal is activated.

The low voltage detection circuit 239 compares the voltage (LV) of the reference voltage source 245 that generates the second predetermined voltage with the voltage of the voltage monitor signal, and the voltage of the voltage monitor signal is LV.
When low, it activates the low voltage signal.

The overcurrent detection circuit 240 includes a transistor 1
09 voltage and current monitor signal discrimination value (IV) of the current monitor signal appearing at the connection point between the source of 09 and the shunt resistor 241.
246 is compared, and the overcurrent detection signal is activated when the current monitor signal exceeds the determination value.

Normally, when the voltage of the main battery 103 drops extremely, the DCDC converter 101 outputs a voltage lower than a predetermined output voltage, and the auxiliary battery 1
15 cannot be fully charged and the load 114
Since the power consumption of an external controller (not shown) is concentrated on the auxiliary battery 115, the life of the auxiliary battery 115 is shortened or the battery is exhausted.

Therefore, the low-voltage detection circuit 239 detects an abnormality in which the DCDC converter 101 cannot output a predetermined voltage and informs the operator that maintenance is required. For example, a unit in which an external controller performs power management. If so, by detecting such a DCDC converter abnormality, it is possible to save the supply power of the high load such as the rear defogger and the load that does not directly affect the running performance, and reduce the load on the auxiliary battery 115, thereby enabling the operation. It is possible to prevent the person from running out of the battery while moving to the vehicle maintenance area.

The transistor 109, which is an element for switching the current on the primary side of the insulating transformer 106, is destroyed when a voltage exceeding its withstand voltage is applied. The voltage applied to the element is the voltage of the main battery 103 plus the surge voltage at the time of switching, and the overvoltage detection level is set in consideration of the magnitude of the surge voltage in advance. When the voltage of the main battery exceeds the set overvoltage detection value (set by HV244), the overvoltage detection circuit 238 informs the constant voltage control circuit 201 on the secondary side of the abnormality, and the switching timing input to the gate of the transistor 109. Stop the signal. This makes it possible to prevent the destruction of the element due to the switching surge, notify the external controller that the output of the DCDC converter 101 is not performed, notify the operator of the abnormality, and perform the same control as the external controller.

The overcurrent detection circuit 240 is the isolation transformer 1
When detecting that the current flowing through the primary winding 107 of 06 exceeds a predetermined value, the overcurrent detection signal is activated to indicate that the overcurrent is detected. As in the case of the overvoltage, the constant voltage control circuit 201 is notified, the switching timing signal of the transistor 109 is stopped, the operator is notified of the abnormality, and the external controller can perform the same control as described above.

Next, the operation of the first embodiment will be described. FIG. 4 is an operation timing chart for explaining the operation of the first embodiment. The signals shown in FIG. 1 are the switching timing signal output from the constant voltage control circuit 201 and the output of the constant voltage control circuit 201 from the delay circuit 20 in order from the top.
The operation clock (ck) delayed by 6 and input to the main control circuit 205 and the rectified waveform by the rectifier 110 are amplitude-limited by the limiter circuit 207 and input to the main control circuit 205 from the primary side to the secondary side. Received data Rx, DATA request flag 2 input to the main control circuit 205 from an external device or the like
37, a reception end flag 2365 which is an output from the main control circuit 205, an error flag 236 which is output from the main control circuit 205 to an external device when the reception from the primary side to the secondary side is not normally completed, the main control circuit 205 DATA0, which is parallel data received from the primary side and output to the outside
~ DATA which is the upper 2 bits of DATAn 234
0 (0 bit), DATA1 (1 bit), V1 voltage (= V2 voltage) which is the input signal 219 of the pulse transformer 209, output of the delay circuit 223 in the transmission request detection circuit 210, and ON output as the gate signal of the transistor 109. The output of the OR circuit 222 in the time switching circuit 212, the output 215 which is the output of serial / parallel conversion by the transmission control circuit 213, the enable signal 218 input to En of the transmission control circuit 213, the clock (ck) of the transmission control circuit 213. Drive signal 216 input to the monitor circuit 2
The status signals (monitoring outputs) output from 14 in parallel to the transmission control circuit 213 are 0 bit and 1 bit.

Further, in FIG. 4, the isolation transformer 106
The information capacity that can be transmitted from the primary side to the secondary side via
There are [n + 1] bits from 0 bit 415 to nbit 417 per frame, and a check bit (check bi) that is a parity bit for [n + 1] bits.
t) 418 is added, and SOM (start of mes
sage) bit 414 and EOM (end of messag) at the end
e) Bit 419 is added to form a frame structure of a total of [n + 4] bits.

The V1 voltage corresponds to the pulse transformer 209 of FIG.
Of the input voltage of the pulse transformer 209
If the number of turns on the secondary side is the same, the V2 voltage that is the output of the pulse transformer also has the same value, and the isolation transformer 106 has 1
While maintaining insulation between the secondary side and the secondary side, signals are sent from the secondary side to the primary side at the same voltage and at the same timing.

Next, a series of operations in the first embodiment will be described with the passage of time. Main control circuit 205
Is a DATA request flag 237 which is first input from the outside.
It is recognized that a transmission request is generated by detecting that the signal is turned from OFF to ON, and one cycle period Req from the falling edge of the first ck input from the change point of the DATA request flag 237.
The transmission request is sent from the output to the driver circuit 208.

The pulse voltage sent from the constant voltage control circuit 201 becomes a voltage of VccB during the period of SOM414 by the driver circuit 208, and the pulse transformer 20
9 is output to the secondary side.

Also, during the period of SOM 414, the transmission request detection circuit 210 compares the output voltage of the pulse transformer 209 with the reference voltage (VrefB) 227, and the comparison result shows that the output voltage of the pulse transformer 209 (VccB)> reference voltage ( VrefB) 227 and the voltage is maintained for the passage time of the filter 225, it is detected that there is a transmission request, and after the passage time of the filter 225 elapses, the enable signal 218 is sent to the transmission control circuit 213. Is entered.

The transmission control circuit 213 serially converts the data such as the status information input in parallel from the monitoring circuit 214 in synchronization with the ck input, and outputs it.
The data of it is output in the order of nbit. 0 bit4
The period 15 is a period in which the transmission control circuit 213 is outputting 0-bit data, and the out 215 indicates the Low level. At this time, the output of the OR circuit 222 in the on-time switching circuit 212 is the transmission Ck of the control circuit 213
The drive signal 216, which is the same signal as the input, is output through.

Further, the output of the OR circuit 222 turns ON / O the transistor 109 for switching the current from the main battery 103 to the primary winding 107 of the isolation transformer 106.
The voltage is transmitted from the primary side to the secondary side of the isolation transformer 106 by the FF, and the main control circuit 20 is output from the output of the rectifying unit 110.
A voltage pulse is input as the Rx input of No. 5, and a "1" or "0" determination is made by the ck input.

The ck input of the main control circuit 205 delays the signal from the output of the constant voltage control circuit 201 by a time corresponding to the delay time of wiring and element operation.
Therefore, since it is delayed by Td1 from the Rx input, the main control circuit 205 holds the Low level in the internal register unless the pulse width of the Rx input changes. That is, the main control circuit 20
If the pulse width of the Rx input of 5 is the same as the output pulse width of the constant voltage control circuit 201, the logical code at this time indicates "0".

In the 1-bit 416 period, the transmission control circuit 2
Since the out output 215 of 13 outputs High, the delay time (Td2) of the output of the delay circuit 223 is OR circuit 22.
2 appears and the pulse width becomes longer by the delay time. At this time, the ck input of the main control circuit 205 holds "High" of the Rx input in the internal register, so that the logical code indicates "1".

The transmission control circuit 213 uses the nbit period 41.
After transmitting the bit data to 7, the check bit for error detection is output in the check bit period 418. In FIG. 1, the error detection method by odd parity is used, and when the code is “1” only in the 1-bit period 416 in the entire data frame, the code of the check bit period 418 is “0”, and the error flag 236 shown by the solid line is the main control circuit. 205
Is a normal output state, the broken line is a case where the code of the check bit 418 is "1" indicating an abnormality, and ck
An error is detected when the input falls and an error flag 236
Goes low to notify the external control device that there is an error.

Further, the error is recovered by the external device recognizing the error, and by setting the DATA request flag 237 to the Low level and setting the error flag 236 to High, the error is recovered.

During the EOM period 419, the transmission control circuit 213
Is the last unsigned bit period of the transmission frame output by the main control circuit 205. The main control circuit 205 sets the reception end flag 235 to the Low level at the fall of the ck input in the EOM period 419, and if the reception is normal, the reception data is DATA0 to DATA0. DAT
Output to external device via An234 or O
Output to the constant voltage control circuit 201 via the R circuit 242,
If there is a reception error, the outputs of DATA0 to DATAn234 retain the values at the time of the previous normal reception.

With the above operation, it becomes possible to transmit the diagnostic information of the circuit operated on the primary side of the isolation transformer 106 to the control circuit on the secondary side without adding an insulating element. Further, the pulse width of the switching timing signal output from the constant voltage control circuit 201 is set to the transmission control circuit 213.
Varies to turn on / off the transistor 109, but the pulse width is unchanged when the '0' code is transmitted.
When transmitting the '1' code, the pulse width is changed to be longer. However, the amount of change is the sum of the setup time and the hold time of the storage element latched by the main control circuit 205, which is a time sufficiently shorter than the switching pulse width of the transistor 109. The influence on the side output voltage is extremely slight, and even if a voltage fluctuation occurs, the constant voltage control circuit 2
Since it is canceled by the feedback control of 01, there is no practical problem.

[Second Embodiment] Next, a second embodiment will be described. FIG. 5 is a diagram showing a configuration of a driver unit of a vehicle motor, which is a premise of the second embodiment. In the figure, a driver unit 500 that is an inverter that generates a three-phase alternating current for driving the motor 502 from a high-voltage main battery 103 is driven by a low-voltage (for example, 12V) auxiliary battery 115, and the driver unit 500.
Is controlled by a motor control circuit 501 for controlling the.

Then, like the DCDC converter of the first embodiment, in order to prevent an electric shock accident during vehicle maintenance,
The driver unit 500 and the motor control circuit 501 are insulated by exchanging signals via the photocoupler group 514 so that they do not have a common potential.

The signals transmitted from the motor control circuit 501 to the driver unit 500 via the photocoupler group 514 include U-phase drive signal A, U-phase drive signal B, V-phase drive signal A, V-phase drive signal B, There are a W-phase drive signal A, a W-phase drive signal B, a smoothing capacitor discharge command, and an enable signal that enables inverter operation. On the contrary, the signal transmitted from the driver unit 500 to the motor control circuit 501 via the photocoupler group 514 is V indicating that the internal power supply Vcc of the driver unit has risen.
There is a cc establish signal.

The IGN-SW 520 is a switch that is turned on / off by an ignition key (not shown), and
The state of the GN-SW 520 is input to the motor control circuit 501, and the motor control circuit 501 starts / stops control of the driver unit 500 according to the state of the IGN-SW 520.

The driver unit 500 includes a motor 502.
U-phase drive section 5 for driving each phase of
03, a V-phase drive unit 504, and a W-phase drive unit 505. Further, the internal configuration of these drive units will be described by taking the W-phase drive unit 505 as an example. Transistor (T
r) a transistor (T that draws current from 506 and the W phase)
r) 508 is a switch element for turning on / off a large current such as an IGBT, which is a push-pull configuration to output / output current to / from the motor.

These transistors 506 and 508 are respectively a driver IC 507 and a driver IC.
509 directly driven by the driver IC 50
The motor control circuit 501 receives the W-phase drive signal A and the W-phase drive signal B, which are ON / OFF pulse signals for driving, and the enable signal as inputs of 7, 509 via a specific photocoupler in the photocoupler group 514. More signal is given. Further, the driver ICs 507 and 509 are supplied with operating power from Vcc 510 which is an internal power supply of the driver unit 500. The same applies to the U-phase drive unit 503 and the V-phase drive unit 504.

The Vcc monitoring circuit 515 has a driver IC 5
This is a circuit for monitoring Vcc 510, which is the power supply for 07 and 509, and is composed of a comparator such as a comparator and a reference voltage. The Vcc 510 is supplied with electric power from the main battery 103 to generate a voltage for the driver IC, and is, for example, a switching power supply such as a flyback converter, and turns on / off the electric power from the main battery 103.
F is supplied through the relay 516, and this relay 516
Are controlled by a motor control circuit 501.

The operation of Vcc monitoring circuit 515 is as follows. Immediately after the relay 516 is turned on, the Vcc 510 starts its operation in order to output a predetermined voltage, but there is a time lag until the predetermined voltage is reached, and immediately after that, the driver IC
Does not reach an operable voltage. Therefore, whether Vcc monitoring circuit 515 has reached an operable voltage is Vcc.
The establishment signal is sent to the motor control circuit 501 via the photo coupler 519. The motor control circuit 501 is V
After receiving the cc establishment signal, the U, V, W phase drive signals are transmitted.

Next, the smoothing capacitor 511 smoothes the voltage fluctuations of the main battery 103 due to the inverter operation of the phase drive units 503, 504, 505, and keeps the voltage of the main battery 103 during the ON period of the relay 516. Smooth. However, even if the relay 516 is turned off, the smoothing capacitor 511 remains in a high voltage state, and it is necessary to discharge this voltage for safety reasons such as prevention of electric shock during vehicle maintenance.
Therefore, after the relay 516 is turned off, the motor control circuit 50
Discharge command is sent from 1 to turn on the transistor 513.
The discharge capacitor 512 and the smoothing capacitor 511.
The electric charge accumulated in the motor unit 502 is discharged to lower the voltage of each part of the driver unit 500 and the motor 502.

Next, the operation of the driver unit 500 will be described step by step. First, when the IGN-SW 520 is turned on, the motor control circuit 501 causes the photo coupler 51 to operate.
The discharge command is turned off via 7 and the transistor 513
Turn off. Next, the relay 516 is turned on to supply the power of the main battery 103 to the driver unit 500. As a result, Vcc in the driver unit 500
510 starts operation so as to supply a voltage to each phase drive unit 503, 504, 505. However, until Vcc reaches a predetermined voltage, Vcc monitoring circuit 515 sets the Vcc establishment signal to "0" to notify the motor control circuit via photocoupler 519 that the Vcc voltage has not been established. After the voltage of Vcc 510 is established, Vcc monitoring circuit 515
Informs the motor control circuit 520 that the Vcc establishment signal has become "1" and is operable, and the motor control circuit 5
01 outputs an enable signal enabling the inverter operation via the photo coupler 518, and U, V, W
Transmission of the drive signal for each phase is started.

When the motor control circuit 501 detects any abnormality, the enable signal is set to "0" (disable) in order to forcibly stop the switching of the inverter of the driver unit 500, and the U-phase drive section 50 is driven.
3, the V-phase drive section 504 and the W-phase drive section 505 can be forcibly stopped.

As described above, between the motor control circuit 501 and the driver unit 500, the UVW phase drive signals, the discharge command, the enable signal, and the Vcc establishment signal are exchanged, and these signals are respectively supplied to the photocoupler 514 as an insulating means. , 517, 518 and 519 are used to exchange signals.

Therefore, in the second embodiment, among the signals exchanged between the motor control circuit 501 and the driver unit 500, the discharge command, the enable signal and the Vcc establishment signal, which are slow signals, can be exchanged via the DCDC converter. And reduce the number of insulation elements such as photo couplers,
It realizes low cost, low circuit scale, and reliability improvement by reducing the number of parts.

FIG. 6 is a block diagram for explaining the configuration of the second embodiment of the DCDC converter according to the present invention,
For simplification of description, the same components as those in FIG. 1 are designated by the same reference numerals, and duplicate description will be omitted. FIG. 7 is a block diagram showing the details of the driver unit in FIG. 6, and the same components as those of the conventional driver unit of FIG. 5 are designated by the same reference numerals to omit redundant description.

In FIG. 6, a difference from the first embodiment shown in FIG. 1 is that the main control circuit 205A and the driver circuit 20 are different.
8A is changed, and the code determination circuit 610, the reception control circuit 640, the driver unit 600, and the motor 502 are added.

In the present embodiment having the above configuration, the parallel data (TD0 to TD) input from the external C / U is input.
m647) is converted into serial data by the main control circuit 205A on the secondary side, and the serial data is converted into the driver circuit 2
08A and pulse transformer 209 to transmit to the primary side code determination circuit 610, and the reception control circuit 640 converts the data again into parallel data, and the parallel output data (RD
0 to RDm641) can be sent to the driver unit 600. Further, the signal 639 output from the driver unit 600 is transmitted to the transmission control circuit 213, the on-time switching circuit 212, the isolation transformer 106.
It can be transmitted to the secondary side via the.

As a result, the primary side driver unit 600 that uses the high-voltage main battery 103 as a power source and the other C / that is the secondary side that uses the low-voltage auxiliary battery 115 as a power source.
A plurality of bits of information can be transmitted / received to / from U without adding an insulating means.

Compared to the first embodiment, the main control circuit 205
An input DAT to which parallel data TD0 to TDm647 of [m + 1] bit is input from other external C / U to A
In addition to the Req signal equivalent to that of the first embodiment in which A is added to indicate a transmission / reception request as an output, a logical code of “1”,
Each output of the '0' signal is added. Then, the main control circuit 205A has a parallel / serial conversion function that serially converts the TD0 to TDm647 of [m + 1] bits input in parallel into an output of either a '1' or '0' signal of a logical code and outputs the output. I have it.

The Req signal and the logically-coded "1" and "0" signals are both connected to the driver circuit 208A, and the driver circuit 208A responds to the input Req signal, "1" signal, and "0" signal. Then, the voltage value of the pulse voltage is changed and output in synchronization with the output pulse of the constant voltage control circuit 201. For this reason, in the driver circuit 208A, a set of a circuit including the AND circuit 646, the transistor 645, and the power supply Vcc is added to the circuit described in FIG. 1, and VccA and Vcc are added.
It is possible to output three types of pulse amplitudes of B and VccC.

Further, the relation of the power supply voltage is VccC> Vcc
With B> VccA, the Req signal, the '1' code, and the '0' code input from the main control circuit 205A are connected to one input of each AND circuit, and the output pulse of the constant voltage control circuit 201 is connected. It is connected to the other input of each AND circuit. As a result, when the main control circuit 205A outputs the Req signal, the pulse amplitude becomes VccC, and when the main control circuit 205A outputs the "1" code, the pulse amplitude becomes VccB and the main control circuit 205A outputs "0". 'When outputting the code, the pulse amplitude becomes VccA.

The code determination circuit 610 of FIG. 6 replaces the transmission request detection circuit 210 of FIG. 1 and has a reference voltage (Vre
fC) 227, reference voltage (VrefB) 622, 2
Two comparators CMPC 226 and CMPB 621 are provided so that a ternary signal transmitted via the pulse transformer 209, that is, a Req signal, a '1' code, and a '0' code can be determined.

Then, the code determination circuit 610 determines the pulse amplitude of the switching timing signal 220 appearing on the secondary side (V2) of the pulse transformer 209 as CMPC 226 and C.
The MPB 621 makes a determination, and the filter 225 removes noise. Although the latch 224 is set to become the enable signal 218 when the sign determination circuit 610 determines the Req signal, as in the first embodiment,
The enable signal 218 is also distributed to the reception control circuit 640.

Further, the CMPB 621 determines a '1' code or a '0' code following the Req signal, and outputs it as a logic signal 642 to RxD of the reception control circuit 640.

When the enable signal is input, the reception control circuit 640 synchronizes with the drive signal 216 and receives the input Rx.
The serial logical signal 642 input from D is stored therein, and if there is no reception error, the reception End 217 outputs [m + 1] bit in parallel as the output DATA RD.
Output as 0 to RDm641.

Next, the structure of the driver unit 600 in this embodiment will be described with reference to FIG. The configuration of the driver unit 600 of FIG. 7 differs from the configuration of the conventional driver unit 500 shown in FIG. 5 in that a photocoupler 517 that insulates and transmits a discharge command, a photocoupler 518 that insulates and transmits an enable signal, That is, the photocoupler 519 for insulating and transmitting the Vcc establishment signal is deleted. The insulation transmission function of these photocouplers is performed via the DCDC converter 601.

That is, the motor control circuit 501 is the other C / U shown in FIG. 6, and the discharge command and the enable signal sent from the motor control circuit 501 to the driver unit 600 are:
The data is input from the motor control circuit 501 to the input DATA (TD0 to TDm647) of the DCDC converter 601, and D
DCDC is insulated inside the CDC converter 601
Output DATA of converter 601 (RD0 to RDm64
It is input to the driver unit 600 from 1).

On the contrary, the Vcc establishment signal sent from the driver unit 600 to the motor control circuit 501 is:
From the driver unit 600 to the DCDC converter 601
Input 639 of the DCDC converter 601 and is insulated inside the DCDC converter 601 to output 2 of the DCDC converter 601.
34 to the motor control circuit 501. Since other configurations are the same as those in FIG. 5, the same reference numerals are given to the same components, and duplicate description will be omitted.

Next, the operation of the second embodiment will be described with reference to FIG.
The operation timing chart of FIG. The signals shown in FIG. 8 are the switching timing signal output from the constant voltage control circuit 201 and the main control circuit 205A in order from the top.
To the main control circuit 205A from an external device or the like.
7. Req output, which is the output from the main control circuit 205A,
Same “0” code output, same “1” code output, V1 voltage (= V2 voltage) which is the input signal 219 of the pulse transformer 209, output of the comparator CMPC226 of the code determination circuit 610, output of the same comparator CMPB621, code Judgment circuit 61
The Req detection signal in 0, the logic signal 642 output from the filter circuit 225 in the code determination circuit 610, the enable signal 218 output from the latch circuit 224 in the code determination circuit 610, and the data received by the reception control circuit 640. Among the parallel data output as RD0 to RDm641 after serial / parallel conversion, the upper 2 bits are RD0 (0 bit) and RD1 (1 bit).

In FIG. 8, the information capacity that can be transmitted from the primary side to the secondary side is [n + 1] bits from 0 bit 815 to nbit 817, to which a check bit 818 for [n + 1] bits is added. And then SOM (start of message) 814 at the beginning
And an EOM (end of message) 819 are added to the end to form a frame of a total of [n + 4] bits, as in the first embodiment.

The difference between the first embodiment and the second embodiment is that this frame is a bidirectional frame and the monitoring circuit 214 and the driver unit 60 from the primary side to the secondary side.
Send status information of 0 to send DATA0 to DATAn234
Is output as the control data TD0 to TDm647 from the other C / U from the secondary side to the primary side.
That is, D0 to RDm641 are output to the driver unit 600.

Referring to FIG. 8 below, as time passes,
The operation of the second embodiment will be described. First, when the DATA request flag 237 for requesting the status information of the DCDC converter from an external device or the like changes from OFF to ON, the Req output becomes High, indicating that there is a transmission / reception request.
During the OM period 814, the output of the driver circuit 208A is VccC.
It is output at the voltage of. At this time, the code determination circuit 610 determines that V
Since refC <VccC, the Req detection signal is H
When it becomes high, the latch circuit 224 is set and the enable signal 218 is output from the latch circuit 224.

In the 0-bit period 815 and thereafter, the main control circuit 205A transmits from the least significant bit, so that the value is "0".
The code output becomes High, and the V1 voltage becomes VccA. The output of the CMPB 621 of the code determination circuit 610 and the output of the CMPC 226 both become Low level, and the logic signal 642 becomes Low indicating the code of "0", and "0" is latched in the reception control circuit 640.

In the 1-bit period 816 and thereafter, TD
Since 0 is a "1" input, the "1" output of the main control circuit 205A becomes High, and the V1 voltage 219 becomes a voltage of VccB. In the code determination circuit 610 that receives this via the pulse transformer 209, the output of the CMPB 621 is Hi.
The logic signal 642 becomes gh level and becomes high indicating the code of "1", and "1" is latched in the reception control circuit 640.

After receiving all data bits and check bits,
If normal, the reception control circuit 640 outputs the data obtained by serial / parallel conversion of the reception data to RD0 to RDn641 at the fall of the V1 voltage 219 in the EOM period 819.

With the above configuration and operation, when the switching timing signal output from the constant voltage control circuit 201 is transmitted from the secondary side to the primary side, the pulse voltage is multivalued by the driver circuit 208A, so that transmission / reception can be performed. The start and the logical value of each bit signal can be transmitted to the primary side circuit of the isolation transformer 106, and when performing complicated diagnosis and control on the primary side of the isolation transformer 106, 2 It becomes possible to send control data from the secondary side to the primary side.

In the first and second embodiments described above, the DCDC converter used in the electric vehicle or the hybrid vehicle has been described, but any DCDC converter that converts the voltage is also applicable. It goes without saying that it has various effects.

[Brief description of drawings]

FIG. 1 is a configuration diagram illustrating a first embodiment of a DCDC converter according to the present invention.

FIG. 2 is a configuration diagram illustrating details of a transmission control circuit according to the first embodiment.

FIG. 3 is a configuration diagram illustrating details of a monitoring circuit according to the first embodiment.

FIG. 4 is an operation timing chart explaining an operation in the first embodiment.

FIG. 5 is a configuration diagram illustrating a driver unit that is a premise of the second embodiment.

FIG. 6 is a configuration diagram illustrating a second embodiment of a DCDC converter according to the present invention.

FIG. 7 is a configuration diagram illustrating details of a driver unit according to a second embodiment.

FIG. 8 is an operation timing chart explaining an operation in the second embodiment.

[Explanation of symbols]

101 ... DCDC converter 102 ... Power converter 103 ... Main battery 106 ... Isolation transformer 109 ... Transistor 110 ... Rectifier 111 ... Smooth section 114 ... Load 115 ... Auxiliary battery 201 ... Constant voltage control circuit 205 ... Main control circuit 208 ... Driver circuit 209 ... Pulse transformer 210 ... Transmission request detection circuit 212 ... On-time switching circuit 213 ... Transmission control circuit 214 ... Monitoring circuit

   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 5H115 PC06 PG04 PI16 PI22 PU01                       PV02 PV09 PV23 QN09 RB21                       SE06 SJ11 SL09 TO12 TO13                       TR01 TU05                 5H730 AA12 AA20 AS00 BB23 BB57                       DD04 EE02 EE08 EE10 EE59                       FD01 FD11 FD41 FF18 FG01                       XX02 XX03 XX12 XX13 XX15                       XX22 XX23 XX32 XX33 XX35                       XX50

Claims (7)

[Claims] 1. A voltage applied to a primary winding of a transformer is turned on / off by a switching element, and
A power conversion unit that rectifies and smoothes the switching current induced in the next winding to supply a DC voltage to the load side, and a first switching timing signal according to the comparison result between the output voltage of the power conversion unit and the reference voltage. , A constant voltage control circuit for generating a first switching timing signal, an insulation circuit for insulating the first switching timing signal and transmitting it as a second switching timing signal from the secondary side to the primary side, and detecting the state of the primary side Related to the first switching timing signal, a state detection circuit that outputs a signal, a switching control circuit that controls the ON / OFF of the switching element by changing the timing indicated by the second switching timing signal according to the state signal. From the primary side to the secondary side based on a comparison of the signal to be generated and the signal related to the voltage waveform induced on the secondary side of the transformer. DCDC converter being characterized in that and a determining signal determination circuit transmission signal. 2. The output of the state detection circuit includes an overvoltage detection signal indicating an overvoltage on the primary side, a low voltage detection signal indicating a low voltage on the primary side, and an overcurrent detection signal indicating an overcurrent on the primary side. The DCDC converter according to claim 1, comprising at least one. 3. The D according to claim 1, further comprising a signal for amplitude-modulating the first switching timing signal and transmitting it from the secondary side to the primary side.
CDC converter. 4. The signal transmitted from the secondary side to the primary side is a transmission request signal requesting to transmit a status signal of the primary side to the secondary side, and in response to the transmission request signal. Serialize multiple status signals
4. The DCDC converter according to claim 3, wherein the DCDC converter transmits from the secondary side to the secondary side. 5. A motor driving inverter is provided on the primary side, and a switching timing change by the switching control circuit is used for transmission from the driver unit of the motor driving inverter to the secondary side. The DCDC converter according to any one of claims 1 to 4, wherein amplitude modulation of the first switching timing signal is used for transmission from the side to the driver unit. 6. The DCDC converter according to claim 5, wherein the output of the state detection circuit includes a power supply confirmation signal of the driver unit. 7. The signal transmitted from the secondary side to the driver unit is either a smoothing capacitor discharge command signal for smoothing the primary side power supply, or an enable signal for enabling the inverter operation of the driver unit. The DCDC converter according to claim 5, wherein one or both of them are included.