JP2003069607A - Atm exchange and its power saving method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an ATM exchange and its power saving method which effectively reduce the power consumption. SOLUTION: A control signal to control the operation frequency of each output buffer is generated depending on the flow rate of ATM cells passing an ATM switch. The operation frequency (operation clock) of a prescribed circuit in the ATM exchange is reduced or its operation is stopped on the basis of the control signal.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to an input ATM
The present invention relates to an ATM switch that switches cells and routes the cells, and a power saving method thereof.

[0002]

2. Description of the Related Art In recent years, in combination with audio compression technology, VT
2. Description of the Related Art A technique for converting voice into an ATM (Asynchronous Transfer Mode) cell format by a technique such as OA (Voice Telephony over ATM) and then transmitting the voice using an ATM network has become widespread. Here, voice has a characteristic that the amount of data transmission per connection time is small due to its nature, while the ATM switch tends to increase its power consumption due to its large capacity and high speed.

As a conventional technique for reducing the power consumption of an ATM exchange, for example, Japanese Patent Laid-Open No. 2000-115188.
There is an "ATM device" disclosed in the publication. In this device, the clock supply to the main circuit of a predetermined interface is stopped in accordance with the detection result of the invalid cell, the operation is stopped, and the power consumption of the ATM device is reduced.

Further, in Japanese Patent Laid-Open No. 10-242992, an ATM switch determines whether input data is valid or invalid, and when the data is valid, a clock signal is given to a functional block for a time required for processing. , A technique for reducing noise and power consumption is disclosed.

[0005]

However, in any of the above-mentioned prior arts, the clock is supplied to a predetermined circuit or the like in the device only based on the result of the determination whether the incoming cell (ATM cell) is valid or invalid. To control
No consideration is given to the amount of data (cell flow rate) that passes through the accommodation line of the exchange, the switch, etc.

That is, in the above-mentioned conventional method, the clock control in the ATM switch is governed only by the validity of the data, and even if the clock control is executed while ignoring the amount of data, the unit time such as voice, etc. In addition to the small amount of data per unit, when dealing with data that does not occur continuously, there is a problem that efficient and effective reduction of power consumption in the exchange cannot be performed.

[0007] This means that, with the introduction of the VTOA technology described above, telephone calls are frequently made using the ATM network, and considering that demand and applications will continue to increase in the future, not only the ATM exchange itself, It is undeniable that even companies, hotels, telephone companies, etc. that use such exchanges will be disadvantageous (become a negative factor) in terms of maintenance and operation costs.

The present invention has been made in view of the above problems, and an object of the present invention is to achieve more effective reduction of power consumption in an ATM switch employing a technique such as VTOA. An object of the present invention is to provide an exchange and a power saving method thereof.

[0009]

In order to achieve the above object, the present invention is an AT which switches an ATM cell input from a line input section and outputs the ATM cell to a predetermined output buffer.
In the M switch, means for obtaining the number of ATM cells sent to the output buffer in a constant cycle, means for monitoring the flow rate of ATM cells from the number of ATM cells, and determining the operating frequency of the output buffer according to the flow rate. Means to do
There is provided an ATM switch having means for generating predetermined control information based on the operating frequency and clock control means for changing the cycle of the operating clock of the output buffer according to the control information.

Preferably, the clock control means divides the operation clock according to the number of ATM cells in the fixed cycle. Further, the clock control means performs control such that the frequency of the operation clock becomes lower as the number of ATM cells in the fixed period becomes smaller.

According to another aspect of the invention, in a power saving method for an ATM switch which switches an ATM cell input from a line input section and outputs it to a predetermined output buffer, the ATM cell is sent to the output buffer at a constant cycle. The step of obtaining the number of ATM cells,
Monitoring the flow rate of the cell, determining the operating frequency of the output buffer according to the flow rate, generating a predetermined control signal based on the operating frequency, the control signal of the output buffer And a step of changing the cycle of the operation clock, and the power saving method of the ATM exchange is provided which starts or stops a predetermined circuit in the ATM exchange according to the changed operation clock.

[0012]

DETAILED DESCRIPTION OF THE INVENTION Referring to the accompanying drawings,
Embodiments of the present invention will be described in detail. ATM in general
(Asynchronous Transfer Mode) The exchange accommodates a plurality of ATM lines, and as its functions, the function of extracting ATM cells propagating on these lines, the connection identifier of the extracted ATM cells,
It has a function of generating a connection identifier to be output and identifying a line to be output. Further, the ATM exchange has a buffer function for temporarily accumulating the input ATM cells in order to perform the quality assurance control necessary for the ATM.

FIG. 1 is a block diagram showing an outline of a main part of an ATM exchange according to this embodiment. A shown in the figure
The TM switch 10 accommodates a plurality of incoming lines 5a to 5n, has a function of converting connection identifiers of ATM cells, and has a function of switching and outputting ATM cells to predetermined outgoing lines 7a to 7n. .

Here, as will be described later, the ATM switch 10 dynamically suppresses the power consumption by dynamically starting / stopping an appropriate circuit in the apparatus according to the flow rate of ATM cells from each ATM line. To work.

In the ATM switch 10 according to the present embodiment, the line input units 1a to 1n are, as shown in FIG.
ATM cells that accommodate the TM lines 5a to 5n and are switched inside the ATM switch are extracted from these ATM lines, and the extracted cells are output to the ATM switch unit 2.

The ATM switch section 2 is provided with each line input section 1a.
The ATM cells input from 1 to 1n are output to predetermined line output units 3a to 3n. And each line output unit 3
a to 3n are ATMs input from the ATM switch unit 2.
The cells are multiplexed and output on the ATM lines 7a to 7n.

FIG. 2 is a block diagram showing in detail the configuration of the line input units 1a to 1n. PHY (input) 24 in the figure
Acts as the physical layer, from the accommodated ATM line,
ATM cells propagating there are extracted, and the extracted ATM cells are transferred to the ATM cell interface I1 through the ATM cell interface I1.
It is sent to the cell processing unit 25.

The ATM cell processing unit 25 uses the connection identifier (VPI (virtual path identifier) / VCI (virtual channel identifier)) of the ATM cell input in this way in the ATM switch unit 2 to determine the ATM cell. Add the information necessary to route. Then, the processed ATM cell is output to the ATM switch unit 2 through the ATM cell interface I2.

At this time, the ATM cell processing unit 25 does not send a signal to the ATM cell interface I2 when there is no ATM cell to be output, so
The receiving circuit of the switch unit 2 can be stopped. Further, the ATM cell processing unit 25 notifies the cell flow rate monitoring circuit 26 of the line number to be output via the output monitoring interface I5.

As a result, the cell flow rate monitoring circuit 26 notifies the ATM switch section 2 of the line number through the output monitoring interface I6 based on the information from the output monitoring interface I5.

FIG. 3 is a block diagram showing in detail the configuration of the line output units 3a to 3n. In the figure, the ATM cell processing unit 31 generates and gives the connection identifier of the ATM cell to be output based on the information received from the ATM switch unit 2 through the ATM cell interface I3. Then, the ATM cell interface I
4 to the PHY (output) 32.

The PHY 32 is the PHY (input) 24 described above.
Similarly to the above, it functions as a physical layer and multiplexes the ATM cells received from the ATM cell interface I4 onto the ATM line and sends out.

FIG. 4 is a block diagram showing the internal structure of the ATM switch section 2 in detail. In the figure, the input buffers 41a to 41n correspond to the line input units 1a to 1n described above.
The received ATM cells are temporarily stored. Then, the ATM cells are output to the corresponding output buffers 43a to 43n through the ATM cell interface I8 based on the routing information added to the ATM cells.

The output buffers 43a to 43n convert the ATM cells received from the ATM cell interface I8 to A
The line output unit 3 through the TM cell interface I3
a to 3n.

Here, each of the output buffers 43a to 43n has a function of making its operating frequency variable by a control signal I7 from the output port monitoring circuit 45. Also,
The output port monitoring circuit 45 uses the output monitoring interface I.
Based on the notification sent from the line input units 1a to 1n via 6, the flow rate of the ATM cells sent to the output buffers 43a to 43n is monitored. Then, according to the flow rate, the control signal I7 for suppressing the operating frequency of each of the output buffers 43a to 43n is generated.

FIG. 5 is a block diagram showing a detailed configuration of the output port monitoring circuit 45. The output port cycle monitoring unit 51 of the output port monitoring circuit 45 shown in the figure statistically monitors the output port based on the notification input from the line input units 1a to 1n via the output monitoring interface I6. Then, the number of ATM cells output from each output port is calculated in a certain fixed period.

The output port cycle monitoring unit 51 also outputs the output buffer 43a based on the information obtained by the above calculation.
Every 43n, a control signal for dividing the operation clock according to the number of ATM cells input in a fixed cycle is
It is sent to the frequency dividing circuits 53a to 53n. With this control signal, the frequency dividing circuits 53a to 53n divide the basic clock 52, and the divided clock is the control clock (control signal) I.
7 is supplied to each output buffer 43a to 43n.

Next, the operation of the ATM cell processing section 25 in the line input sections 1a-1n constituting the ATM switch according to the present embodiment will be described with reference to the timing charts shown in FIGS. .

A typical ATM cell interface is
As shown in FIG. 6, the clock 61 and A synchronized with it
Display the TM cell valid display 62 at the beginning of the ATM cell,
ATM cell data 63 is transmitted. On the other hand, the ATM cell processing unit 25 of the ATM exchange according to this embodiment operates as follows.

The ATM cell processing unit 25, as shown in FIG. 7, when there is no ATM cell data 73 to output (at this time, the ATM cell valid display 72 is not displayed.
In FIG. 7, a clock 71 is shown in a dotted line 75).
To stop. Then, when valid ATM cell data is output, the output of the clock 71 is restarted along with the ATM cell valid display (see timing "T" in FIG. 7).

FIG. 8 shows an ATM cell processing section 25, a cell flow rate monitoring circuit 26 (see FIG. 2), and an output port monitoring circuit 45.
6 is a timing chart showing the operation (see FIGS. 4 and 5). The ATM cell processing unit 25 is the connection identifier of the ATM cell input from the ATM cell interface 81 shown in FIG. 8 (the same as the ATM cell interface I1 in FIG. 2. The clock is omitted in FIG. 8). Then, the line number (= output buffer number) that outputs the cell is determined.

Further, in FIG. 8, the timing chart shown as the output monitoring interfaces 82 and 83 is AT
It is the operation timing in the output monitoring interface I5 when the M cell processing unit 25 outputs to the cell flow rate monitoring circuit 26. Here, #a, #b, etc. represent output port numbers.

The output monitoring interface I6 (see FIG. 2) located on the output side of the cell flow rate monitoring circuit 26 may be further processed based on the output monitoring interface I5, but in the present embodiment, Treat these interfaces as equivalent.

As described above, the output port monitoring circuit 45
Then, the number of ATM cells output during a fixed period is counted based on the notification sent from each of the line input units 1a to 1n via the output monitoring interface I6.

The example shown in FIG. 8 corresponds to the explanation of the operation when the output port monitoring circuit 45 monitors based on the notification sent from the two line input sections via the output monitoring interface. . In the output monitoring interface I6 in the case of two ports, the number of cells is counted with four cells transmitted as one cycle.

In the output monitoring interface I6, in the "monitoring cycle" shown in FIG. 8, there are 5 cells for the output port #a, 1 output cell for #b, and
Two output cells for #c are detected. As a result, the output port monitoring circuit 45 supplies the "clock a" shown in FIG. 8 as a control signal interface to the output buffer 43a, and supplies the basic clock as it is as its clock frequency.

On the other hand, for the output port #b, since only one cell is output in the above-mentioned one monitoring cycle, the clock divided by four with respect to the basic clock is "clock b".
And supplies it to the output buffer 43b. Similarly, since the output port #c has 2 cells per cycle, the clock obtained by dividing the basic clock by 2 is supplied to the output buffer 43c as "clock c".

As described above, according to the present embodiment, the control signal for suppressing the operating frequency of each output buffer is generated according to the flow rate of the ATM cell passing through the ATM switch, and the ATM signal is generated based on the signal. By lowering the operating frequency of the predetermined circuit in the exchange or stopping the operation, it is possible to reliably reduce the power consumption in the device.

In particular, when transmitting data such as voice and internet data using an ATM exchange, the data transmission time is often shorter than the connection time, so all circuits in the exchange are always used. It is inefficient to operate. Therefore, the power saving effect is large by controlling the operation clock frequency of the internal circuit of the exchange according to the flow rate of the ATM cells passing through the switch.

That is, in the ATM switch according to the present embodiment, the operation clock is stopped for each output port at the time when it is not necessary to process the ATM cell, so that the power consumption appropriate for the equipment condition can be obtained. Can be reduced.

Further, by controlling the clock frequency supplied to a predetermined circuit by counting the number of ATM cells that are output periodically, there is an effect that appropriate power control can be performed depending on the traffic situation in the exchange.

The present invention is not limited to the above-mentioned embodiments, and various modifications can be made without departing from the spirit of the present invention. For example, A shown in FIG.
The TM processing unit 25 and the cell flow rate monitoring circuit 26 may be degenerated. In addition to the signals shown in FIG. 6, the ATM cell interface generally
Although a control signal for congestion control is used, the clock control according to this embodiment described above can be executed in that case as well.

[0043]

As described above, according to the present invention,
The number of ATM cells to be sent to the output buffer is determined at a constant cycle, the flow rate of ATM cells is monitored based on the number of ATM cells, the operating frequency of the output buffer is determined according to the obtained flow rate, and the operation is performed. By changing the cycle of the operation clock of the output buffer based on the frequency, it is possible to appropriately reduce the power consumption of the ATM switch according to the throughput of the ATM cell.

Also, by controlling the frequency division of the operation clock of the circuit supplied to the circuit inside the ATM switch according to the number of ATM cells in a certain cycle, appropriate power control can be performed depending on the traffic situation in the switch. The effect is that you can do it.

[Brief description of drawings]

FIG. 1 is a block diagram showing an outline of a main part of an ATM exchange according to an embodiment of the present invention.

FIG. 2 is a block diagram showing in detail the configuration of line input units 1a to 1n.

FIG. 3 is a block diagram showing in detail the configuration of line output units 3a to 3n.

FIG. 4 is a block diagram showing an internal configuration of the ATM switch unit 2 in detail.

5 is a block diagram showing a detailed configuration of an output port monitoring circuit 45. FIG.

FIG. 6 is an ATM cell processing unit 2 in the line input units 1a to 1n.
6 is a timing chart showing the operation of FIG.

FIG. 7 is an ATM cell processing unit 2 in the line input units 1a to 1n.
6 is a timing chart showing the operation of FIG.

FIG. 8 is a timing chart showing operations of an ATM cell processing unit, a cell flow rate monitoring circuit, and an output port monitoring circuit.

[Explanation of symbols]

2 ATM switch section 3a to 3n line output section 5a-5n ATM line (incoming line) 7a-7n ATM line (outgoing line) 10 ATM switch 25 ATM cell processing unit 26-cell flow monitoring circuit 31 ATM cell processing unit 41a to 41n input buffer 43a to 43n output buffer 51 Output port cycle monitor 52 Basic clock 53a to 53n divider circuit 62 ATM cell valid display 71 clock

Claims (7)

[Claims] 1. ATM (Async) input from the line input section
hronous transfer mode) In an ATM switch that switches cells and outputs them to a predetermined output buffer, a means for determining the number of ATM cells sent to the output buffer at a constant cycle, and Means for monitoring the flow rate, means for determining the operating frequency of the output buffer according to the flow rate, means for generating predetermined control information based on the operating frequency, and an operation clock for the output buffer according to the control information And an clock switching means for changing the cycle of the ATM switch. 2. The ATM switch according to claim 1, wherein the number of ATM cells is obtained based on predetermined line information from the line input section. 3. The control information is statistical information about an output line of the ATM switch obtained from a connection identifier of the ATM cell.
ATM switch described. 4. The ATM switch according to claim 1, wherein the clock control means divides the operation clock in accordance with the number of ATM cells in the fixed cycle. 5. The clock control means controls to lower the frequency of the operation clock as the number of ATM cells in the fixed cycle decreases.
ATM switch described. 6. The ATM exchange according to claim 2, wherein when the number of ATM cells is zero, the operation clock is stopped by stopping the output of the line information. 7. The ATM (Async) input from the line input section
hronous transfer mode) In the power saving method of an ATM switch for switching cells to output to a predetermined output buffer, a step of obtaining the number of ATM cells to be sent to the output buffer in a constant cycle, and an ATM cell from the number of ATM cells Monitoring the flow rate of the output buffer, determining the operating frequency of the output buffer according to the flow rate, generating a predetermined control signal based on the operating frequency, and operating the output buffer according to the control signal. A step of changing a cycle of a clock, wherein a predetermined circuit in the ATM exchange is started or stopped by the changed operation clock.
Power saving method for TM switch.