JP2003069408A - Method and circuit for controlling output buffer to bus signal line - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method and circuit for controlling an output buffer to a bus signal line in a package circuit so as to reduce production of ground noise and to decrease the power consumption. SOLUTION: A control signal source validating an output buffer is given to flip-flop circuits 41 to 44, which produce a plurality of kinds of control signals with different timings. An n-bit bus data output buffer is classified into four groups, and control signals #1 to #4 outputted from the flip-flop circuits 41 to 44 are fed to output buffers 11 to 14 by each group with distribution. Controlling an application timing of the control signals to n-sets of the output buffers in time division and dividing the simultaneous operating signal can decrease number of simultaneous operating signals and divide the simultaneous operating signal so as to decrease number of the simultaneous operating signals, occurrence of ground noise and reduce power consumption.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output buffer control method and circuit for a bus signal line. The package circuits of bus data signal processing systems in various data transmission systems from low speed to high speed and equipment monitoring and control systems in which various digital or analog signals are input / output are mutually connected via a backboard, etc. And is configured as a rail-in type device or the like.

The present invention relates to a method and a circuit for controlling an output buffer to a bus signal line in a bus interface circuit or the like of such a device, which reduces ground noise when a data signal is transmitted and received between packages by the bus signal line. Moreover, it is intended to reduce power consumption.

[0003]

2. Description of the Related Art FIG. 3 shows a conventional package circuit including an output buffer for a bus signal line. As shown in the figure, from the transmitting side package circuit 100 to the receiving side package circuit 2
00, n bus signal lines 21 to 2n for sending n-bit bus data are connected by a connector via the backboard.

In the transmitting side package circuit 100, n
The bit bus data includes n output buffers 11 to 1n.
Entered in. The output of each of the output buffers 11 to 1n is open when no control signal is applied,
While the control signal is being applied, a valid high-level (power supply voltage level) or low-level (ground level) bus data signal is output to each bus signal line 21 to 2n in accordance with the input bus data.

A control signal is simultaneously applied to each of the n output buffers 11 to 1n at a predetermined data transmission timing.
The n output buffers 11 to 1n are simultaneously activated,
The circuit elements are driven so that all the n bus signal lines 21 to 2n output signals of a predetermined level.

[0006]

Conventionally, control signals for validating bus data output have been simultaneously applied to the n output buffers 11 to 1n to the bus signal line at the same time. All the data may change from a high level (power supply voltage level) to a low level (ground level) all at once. In this case, the output buffers 11 to 11
There are n simultaneous operation signal lines driven by 1n.

When a large number of simultaneous operation signal lines are generated as described above, if the number of ground lines near the simultaneous operation signal line region in the connector in which the bus signal lines are bundled is small, so-called ground noise in which the ground level fluctuates occurs. Occurs,
Reception error occurs in bus data transmission.

FIG. 4 shows an example of the simultaneous operation signal line area in the connector of the bus signal line. The figure shows a cross section of a 4 × 11 terminal connector. In the figure, the symbol Δ indicates a simultaneous operation signal line terminal, an area 31 surrounded by a dotted line indicates a simultaneous operation signal line area, and a solid area 32 indicates a ground line number calculation area.

In order not to generate ground noise,
A predetermined distance from the simultaneous operation signal line area 31 (for example,
The relationship between the number G of ground lines and the number S of simultaneously operating signal lines in the number-of-ground-lines calculation area 32 within 2.54 mm must satisfy the following expression (1).

Predetermined ratio R ≦ number of ground lines G / number of simultaneously operating signal lines S (1) Here, in the package circuit shown in FIG. 3, one ground layer is provided and the simultaneously operating circuit is provided with TTL (Transistor Transisto).
r Logic), the predetermined ratio R is 0.5,
The ratio of the number G of ground lines to the number S of simultaneously operating signal lines is
Must be 0.5 or greater. Note that the number S of simultaneously operating signal lines is the number of signal lines that simultaneously operate 9 or more within a phase difference of ± 5 ns.

In FIG. 4, the mark ● indicates a ground line, and in the example shown in the figure, the ratio of the number of ground lines according to the above formula (1) is 3 (the number of ground lines) / 16 (the number of simultaneously operating signal lines).
= 0.1875 <0.5, and ground noise is generated.

FIG. 5 shows how ground noise is generated, and FIG. 5A shows a control signal applied to the output buffer for the bus signal line, that is, a select signal for enabling the output to the bus signal line. . (B) of the figure shows one of the n-bit data output signals outputted from the output buffer, and (c) of the figure shows the voltage level of the ground line.

When n output buffers are simultaneously activated and operate in unison, and inrush current flows or is cut off, when the number of ground lines is small, the resistance load or inductive noise of the ground lines may cause an inrush current. As shown in, ground noise is generated at the start and end edge points of the operation.

In order to prevent the generation of such ground noise, the first method is to increase the number of ground lines in the area within 2.54 mm from the simultaneous operation signal line area in the connector, or as the second method, A possible method is to reduce the number of simultaneous operation signal lines that are sources of generation of ground noise.

In order to prevent the generation of ground noise by the first method of increasing the number of ground lines, it is necessary to remodel the package circuit and the backboard, and it is difficult to take immediate action. On the other hand, a second method for reducing the number of the simultaneous operation signal lines is a PLD circuit (Programmable Log).
ic Device: Semi-custom IC that can easily realize desired logic by program, or FPGA (Field Prog
rammable Gate Array: A semi-custom IC that can realize a logic circuit of thousands to tens of thousands of gates that can be programmed by the user at hand is incorporated, and by changing them, it is possible to easily cope with the first method.

According to the second method of the present invention, the number of simultaneously operating signal lines can be reduced, the generation of ground noise can be reduced, the reception error of bus data transmission can be prevented, and the power consumption can be reduced. It is an object of the present invention to provide a method and a circuit for controlling an output buffer for a bus signal line that can be used.

[0017]

An output buffer control method for a bus signal line according to the present invention is an output buffer corresponding to each bus signal line for outputting a valid data signal to a parallel bus signal line when a control signal is applied. In the control method for
A plurality of types of control signals having different timings are generated as control signals to be applied to the output buffer, the plurality of types of control signals having different timings are dispersed and added to the output buffer, and the output buffers corresponding to the respective bus signal lines are simultaneously operated. It is characterized by reducing the number of operations.

Further, (2) the number of kinds of control signals having different timings is set to a number which brings about reduction of ground noise caused by the number of simultaneous operations of the output buffer.

(3) The number of types of control signals having different timings is determined based on the power supply power required according to the number of simultaneous operations of the output buffer.

(4) A plurality of types of control signals having different timings are generated using the system clock of the bus data signal processing system or a clock generated based on the system clock.

Further, the output buffer control circuit for the bus signal line according to the present invention includes (5) an output buffer corresponding to each bus signal line which outputs a valid data signal to the parallel bus signal lines when the control signal is applied. Means for generating a plurality of types of control signals having different timings as control signals to be added to the output buffer, and adding the plurality of types of control signals having different timings to the output buffer in a distributed manner, corresponding to each bus signal line It is characterized by reducing the number of simultaneous operation of the output buffer of.

Further, (6) the number of types of control signals having different timings is set to a number that reduces the ground noise caused by the number of simultaneous operations of the output buffer.

(7) The number of types of control signals having different timings is determined based on the power supply power required according to the number of simultaneous operations of the output buffer.

(8) A means for generating a plurality of types of control signals having different timings by using a system clock of the bus data signal processing system or a clock generated based on the system clock is provided. And

[0025]

1 shows an output buffer control circuit for a bus signal line according to the present invention. The output buffer control circuit according to the present invention inputs an externally supplied control signal source for enabling the output buffer to one or a plurality of flip-flop circuits (four flip-flop circuits 41 to 44 in FIG. 1), and the flip-flop circuits are inputted. Control circuit generates a plurality of types of control signals having different timings, and applies the plurality of types of control signals having different timings to the output buffers 11 to 1n for n-bit data in a distributed manner.

That is, as shown in the embodiment of FIG. 1, the control signal source to the output buffers 11, 12, 13, 14, ... Is input to the first flip-flop circuit 41, and the first flip-flop circuit 41 is input. Is input to the second flip-flop circuit 42, the output of the second flip-flop circuit 42 is input to the third flip-flop circuit 43, and the output of the third flip-flop circuit 43 is input to the fourth flip-flop circuit. Input to the circuit 44. A system clock is supplied to the clock terminals of the first to fourth flip-flop circuits.

Then, the n output buffers are divided into four groups, the first control signal # 1 output from the first flip-flop circuit 41 is added to the output buffer 11 of the first group, and the second flip-flop circuit is added. The second control signal # 2 output from the second flip-flop circuit 42 to the output buffer 12 of the second group, and the third control signal # 3 output from the third flip-flop circuit 43 to the output buffer of the third group. In addition to 13, the fourth control signal # 4 output from the fourth flip-flop circuit 44 is applied to the output buffer 14 of the fourth group.

FIG. 2 shows a time chart of the output data waveform to the bus signal line according to the present invention. FIG. 3A shows the waveform of the system clock. FIG. 3B shows the waveform of the control signal source for each output buffer. FIG. 6C shows the waveform of the first control signal applied to the output buffers of the first group. FIG. 3D shows an output data waveform output from the output buffer of the first group.

Similarly, FIG. 6 (e) shows the waveform of the second control signal applied to the output buffers of the second group. FIG. 6F shows an output data waveform output from the output buffer of the second group. FIG. 7G shows the waveform of the third control signal applied to the output buffers of the third group. FIG. 6H shows an output data waveform output from the output buffer of the third group. FIG. 11I shows the waveform of the fourth control signal applied to the output buffers of the fourth group. FIG. 11J shows an output data waveform output from the output buffer of the fourth group.

FIG. 3 (k) shows the voltage level of the ground line, but the application timing of the control signal to the n output buffers is controlled in a time division manner so that the simultaneous operation signals of the n output buffers are controlled. By dividing into groups, the number of simultaneously operating signals is reduced, and it is possible to prevent generation of ground noise as shown in FIG.

In addition, each flip-flop circuit 41-44
A control signal having a highly accurate phase difference is obtained from each of the flip-flop circuits 41 to 44 by adding the system clock to the clock terminal of, and a highly reliable output buffer control circuit can be realized. The clock terminals of the flip-flop circuits 41 to 44 are provided with PLLs.
A divided clock signal synchronized with the system clock may be generated and added using a circuit or the like.

The division number of the control signal can be increased to any division number by increasing the number of stages of the flip-flop circuit. If the effect of ground noise reduction does not appear even if the number of divisions is two or four, the number of control signals is increased by increasing the number of flip-flop circuits to increase the number of divisions to 8 or 16. Decrease the operation signal. However, if the ground noise reduction effect can be obtained by the two-step division, it is not necessary to increase the number of division steps.

In the connector shown in FIG. 4, 1
When the six simultaneous operation signal lines are divided into four, the number of simultaneous operation signal lines becomes four, and the ratio of the number of ground lines according to the above equation (1) is as follows. 3 (number of ground lines) / 4 (simultaneous operation signal lines) = 0.
75> 0.5 Therefore, the condition of Expression (1) is satisfied, and the generation of ground noise can be prevented.

Further, in the case of a connector having nine ground lines and 64 simultaneous operation signal lines, in the conventional case in which a control signal is simultaneously applied, the above-mentioned formula (1) is 9 (ground lines). Number) / 64 (simultaneous operation signal line) =
Since the ratio of the number of ground lines is 0.14 and the ratio of the number of ground lines is 0.5 or less, the ground noise is generated. On the other hand, when the simultaneous operation signal line is divided into four by the present invention, 9 lines (the number of ground lines) / 16 lines (the simultaneous operation signals) ] = 0.56 and the ratio of the number of ground lines is 0.5 or more,
Generation of ground noise can be prevented.

Although the embodiment using the flip-flop circuit has been described as the circuit for generating a plurality of kinds of control signals with different timings, the present invention is not limited to this, and a shift register, a delay circuit, a memory or the like is used. Thus, it is possible to construct a circuit that generates a plurality of types of control signals with different timings, and various modifications can be made without departing from the spirit of the present invention.

[0036]

As described above, according to the present invention,
By reducing the application timing of the control signal that enables the output of the output buffer to each bus signal line and reducing the number of simultaneous operation signals, the generation of ground noise is reduced and the reception error of the bus data signal is prevented. You can

Further, by shifting the application timing of the control signal for operating the output buffer to each bus signal line, the number of simultaneously driving circuits of the output buffer to each bus signal line is reduced, and the rush current at the time of simultaneous driving is reduced. Therefore, the power supply circuit can have low power, and the power supply circuit can be downsized and power consumption can be reduced.

Further, by using the system clock when generating the control signals with different timings, it is possible to generate the control signals having a highly accurate phase difference,
A highly reliable bus data output buffer control can be performed.

[Brief description of drawings]

FIG. 1 is a diagram showing an output buffer control circuit for a bus signal line according to the present invention.

FIG. 2 is a time chart of output data waveforms to the bus signal line of the present invention.

FIG. 3 is a diagram showing a conventional package circuit including an output buffer for a bus signal line.

FIG. 4 is a diagram showing an example of a simultaneous operation signal line region of a bus data signal line connector.

FIG. 5 is a diagram showing how ground noise is generated.

[Explanation of symbols]

11 First group output buffer 12 Second group output buffer 13 Output buffer of the third group 14 Output buffer of the 4th group 21 Bus signal line of the output buffer of the first group 22 Bus signal line of the output buffer of the second group 23 Bus signal line of the output buffer of the third group 24 Bus signal line of the output buffer of the fourth group 41 First Flip-Flop Circuit 42 Second flip-flop circuit 43 Third Flip-Flop Circuit 44 Fourth Flip-Flop Circuit

Continued front page    F term (reference) 5J032 AA00 AB00 AC04 AC17                 5J056 AA04 BB17 BB24 CC14 FF01                       FF07 FF10 GG00 GG03 KK01                 5K029 AA02 DD02 DD13 DD23

Claims (8)

[Claims] 1. A control method for an output buffer corresponding to each bus signal line, which outputs a valid data signal to a parallel bus signal line when a control signal is applied, wherein a plurality of types of control signals to be added to the output buffer have different timings. Bus signal line for reducing the number of simultaneous operation of the output buffers corresponding to the respective bus signal lines by generating a control signal of a plurality of types and distributing a plurality of types of control signals having different timings to the output buffers. To control the output buffer to the. 2. The bus signal line according to claim 1, wherein the number of types of control signals having different timings is set to a number that reduces ground noise caused by the number of simultaneous operations of the output buffers. Output buffer control method. 3. The number of kinds of control signals having different timings is set to a number determined based on the power supply power required according to the number of simultaneous operations of the output buffer. Output buffer control method for bus signal line. 4. The plurality of types of control signals having different timings are generated using a system clock of a bus data signal processing system or a clock generated based on the system clock. An output buffer control method for a bus signal line according to any one of claims. 5. An output buffer corresponding to each bus signal line that outputs a valid data signal to a parallel bus signal line when a control signal is applied, and a plurality of types of control signals with different timings as control signals to be added to the output buffer. And a means for generating a plurality of types of control signals having different timings dispersedly added to the output buffer to reduce the number of simultaneous operations of the output buffer corresponding to each bus signal line. Output buffer control circuit to line. 6. The bus signal line according to claim 5, wherein the number of types of control signals having different timings is a number that reduces ground noise caused by the number of simultaneous operations of the output buffers. Output buffer control circuit. 7. The number of types of control signals having different timings is set to a number determined based on a power supply power required according to the number of simultaneous operations of the output buffer. Output buffer control circuit for bus signal lines. 8. A means for generating a plurality of types of control signals having different timings by using a system clock of a bus data signal processing system or a clock generated based on the system clock. Item 5
8. An output buffer control circuit for the bus signal line according to any one of 7 to 7.