JP2003067440A - スタティックゲートの入力におけるノイズをシミュレートして出力におけるノイズを求めるための方法 - Google Patents

スタティックゲートの入力におけるノイズをシミュレートして出力におけるノイズを求めるための方法

Info

Publication number
JP2003067440A
JP2003067440A JP2002126588A JP2002126588A JP2003067440A JP 2003067440 A JP2003067440 A JP 2003067440A JP 2002126588 A JP2002126588 A JP 2002126588A JP 2002126588 A JP2002126588 A JP 2002126588A JP 2003067440 A JP2003067440 A JP 2003067440A
Authority
JP
Japan
Prior art keywords
output
noise
gate
branch
node
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002126588A
Other languages
English (en)
Japanese (ja)
Other versions
JP2003067440A5 (https=
Inventor
S Brandon Keller
エス・ブランドン・ケラー
Gregory D Rogers
グレゴリー・ディー・ロジャース
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HP Inc
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of JP2003067440A publication Critical patent/JP2003067440A/ja
Publication of JP2003067440A5 publication Critical patent/JP2003067440A5/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/36—Circuit design at the analogue level
    • G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
JP2002126588A 2001-04-30 2002-04-26 スタティックゲートの入力におけるノイズをシミュレートして出力におけるノイズを求めるための方法 Pending JP2003067440A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/845,437 US6502223B1 (en) 2001-04-30 2001-04-30 Method for simulating noise on the input of a static gate and determining noise on the output
US09/845437 2001-04-30

Publications (2)

Publication Number Publication Date
JP2003067440A true JP2003067440A (ja) 2003-03-07
JP2003067440A5 JP2003067440A5 (https=) 2005-04-07

Family

ID=25295234

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002126588A Pending JP2003067440A (ja) 2001-04-30 2002-04-26 スタティックゲートの入力におけるノイズをシミュレートして出力におけるノイズを求めるための方法

Country Status (2)

Country Link
US (1) US6502223B1 (https=)
JP (1) JP2003067440A (https=)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7552040B2 (en) * 2003-02-13 2009-06-23 International Business Machines Corporation Method and system for modeling logical circuit blocks including transistor gate capacitance loading effects
US7107552B2 (en) * 2003-06-10 2006-09-12 Intel Corporation Method and apparatus to analyze noise in a pulse logic digital circuit design
EP1577801A1 (en) * 2004-03-15 2005-09-21 Infineon Technologies AG Device characterization concept
US7400167B2 (en) * 2005-08-16 2008-07-15 Altera Corporation Apparatus and methods for optimizing the performance of programmable logic devices
US7269809B2 (en) * 2004-06-23 2007-09-11 Sioptical, Inc. Integrated approach for design, simulation and verification of monolithic, silicon-based opto-electronic circuits

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6253351B1 (en) * 1998-03-24 2001-06-26 Matsushita Electric Industrial Co., Ltd. Circuit optimization system
JP3068065B2 (ja) * 1998-09-25 2000-07-24 日本電気株式会社 回路設計方法
US6405347B1 (en) * 1999-06-30 2002-06-11 Hewlett-Packard Company Method and apparatus for determining the maximum permitted and minimum required width of a feedback FET on a precharge node

Also Published As

Publication number Publication date
US6502223B1 (en) 2002-12-31
US20020194573A1 (en) 2002-12-19

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