JP2003067439A - Method for system simulation - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent an overall simulation speed from being lowered due to a decreased transfer rate becoming a bottleneck when data transferred between simulators and between hardware emulators are voluminous, when carrying out verification of a system architecture and simulation for performance analysis by coordinating a simulator on a computer with a hardware emulator. SOLUTION: The present invention analyzes a volume of communication between functional blocks utilizing result of operational simulation of the operation model in a high level of designing and assigns a simulation means so that a volume of communication in the boundary communication channel between a group of blocks to which a simulator is assigned and a group of blocks to which an emulator is assigned becomes minimal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a simulation method for verifying or evaluating the system architecture of a digital system such as an LSI system or a computer system with cycle accuracy, and more particularly to a measure for speeding up the simulation speed.

[0002]

2. Description of the Related Art In recent years, it has become possible to realize a large-scale digital system using a one-chip LSI due to the miniaturization of LSI and the progress of integration technology. In the development of such a system, it is necessary to design in a short period of time, from system specifications / operation design to function, logic, and layout, which are executed top-down while verifying in stages, and to achieve early commercialization. There is.

In particular, in the system level specifications / operations and the basic design of the realization architecture on the premise of the LSI implementation, since the architecture change after the chip manufacturing entails a great cost, before the detailed design is advanced. It is required to analyze the processing performance of the system LSI and its bottleneck portion. Therefore, after the functional behavioral description of the system is confirmed by using the C program and the specifications / functions are confirmed, the architecture that realizes the function is simulated, for example, by simulating the operation / data flow of the system with transaction accuracy, or by synchronizing. By performing simulation with the cycle accuracy of the clock signal and modeling with appropriate accuracy, the function of the system architecture is verified, and the performance that can be achieved with the target system architecture is estimated and the performance constraining point is analyzed. Is done like this.

At that time, in order to improve the accuracy of function verification and the accuracy of performance analysis so that an appropriate design selection can be made from a plurality of architecture plans, finally, cycle accuracy such as HDL simulation based on RTL description is required. It is necessary to perform the simulation of. However, in such a simulation, the simulation speed is slow in inverse proportion to the simulation accuracy, and for example, it is 1/1000 of the case of the design upper specification / operational simulation.
Therefore, it is difficult to verify / analyze the operation of a large-scale system or a complicated and long pattern within a realistic period.

For this reason, at present, it is called a "simulation accelerator" such as a hardware emulator composed of programmable devices, or a "cycle-based simulator" which limits the cycle accuracy to improve the simulation processing efficiency. By simulating a partial block of the system or the entire system by using a simulation means, the simulation speed is accelerated.

[0006]

By the way, when the "simulation accelerator" is executed in cooperation with the simulator on the computer to execute the simulation, the communication speed between the accelerator and the computer is generally slower than the processing speed of each computer. Therefore, when a large amount of data exchange is required between the two parties, conventionally, there is a problem that the communication speed becomes a bottleneck and the simulation speed decreases.

Further, when the "cycle-based simulator" is used, it is effective for speeding up the simulation for a block having a high data activity and a large amount of operation, but the active portion is small and the amount of operation is small. Since the processing overhead is large for a small number of blocks, there is a problem that the simulation speed cannot be increased conventionally.

The present invention has been made in view of the above points, and a main object thereof is to assign a simulation means to each constituent block of an architecture that embodies a system and perform a cycle-accurate simulation. By using the result of the higher-level system simulation, the simulation speed can be increased.

[0009]

In order to achieve the above object, the present invention focuses on a communication amount of data exchange in a system configuration block obtained by a system simulation of a design upper level, and a simulation accelerator and a simulator on a computer. When the simulations are performed in cooperation with each other, the simulation means are assigned so that the communication amount between the two simulator means is minimized. Further, when the cycle-based simulator is used as the simulator means, the operation amount of each block is estimated from the above communication amount, and the cycle-based simulator is assigned only to the block having a large operation amount.

Specifically, the invention of claim 1 is premised on a system simulation method for simulating the architecture of a digital system with cycle accuracy.

Then, an operation simulation process for simulating a system operation model of a design upper level,
Based on the simulation result of this operation simulation process, a communication amount analysis process of analyzing the communication amount of data exchange in each component block of the system, and embodying in the lower design stage based on the analysis result of this communication amount analysis process And a simulation means assigning step of assigning a simulation means to each constituent block of the system. It should be noted that the data transmission / reception in each component block may be performed by each component block with another component block, or may be performed by each component block with the simulation test bench. Good. In that case, in the simulation means allocation step, not only the constituent blocks but also the simulation test bench can be allocated. Further, the communication amount may be simply the data amount,
It may be given by an arbitrary evaluation function having the access count, the access count and the data amount as arguments.

According to a second aspect of the present invention, in the first aspect of the present invention, in the simulation means assigning step, when the constituent block has a limitation in assigning the simulation means, the constraint and the analysis result in the communication amount analyzing step are displayed. Try to arbitrate.

According to a third aspect of the invention, in the second aspect of the invention, the simulation means allocating step allocates the plurality of simulation means so that the communication amount between the plurality of simulation means becomes small.

According to a fourth aspect of the present invention, in the third aspect of the present invention, in the simulation means assigning step, a hardware simulator on a computer and a hardware emulator using a programmable device are assigned as the simulation means.

According to the present invention, in the simulation means allocation step, based on the analysis result in the communication amount analysis step,
In each component block of the system embodied in the lower design stage, a hardware simulator on a computer,
When allocating the hardware emulator using the programmable device, the hardware simulator and the hardware emulator on the computer are allocated so that the communication volume between them becomes small, so that the data communication volume between them can be suppressed. Therefore, it is possible to avoid a decrease in system simulation speed due to a low communication speed between the two, and the processing speed of the entire simulation can be improved accordingly.

According to the invention of claim 5, in the invention of claim 1, in the operation simulation step, an operation model in which the system is divided into a plurality of functional blocks is used.

According to a sixth aspect of the present invention, in the first aspect of the present invention, the communication amount analyzing step analyzes the temporal transition of the communication amount, and the simulation means allocating step comprises:
A hardware simulator using a computer and a hardware emulator using a programmable device are assigned according to the temporal change of the communication amount.

According to the present invention, the communication traffic analysis step analyzes the temporal transition of the communication traffic. Then, in the simulation means allocating step, the simulation means is allocated according to the temporal transition of the communication amount. Therefore,
Even when the communication volume in each constituent block changes as the simulation progresses, high-speed co-simulation with the average communication volume between the simulation means is executed. can do.

According to a seventh aspect of the present invention, in the first aspect of the invention, in the simulation means allocation step, the operation amount of the constituent block is estimated based on the analysis result of the communication amount of each constituent block, and based on the operation amount. To allocate simulation means.

According to the invention of claim 8, in the invention of claim 7, in the operation simulation step, an input signal for controlling an operation mode of each constituent block is observed to generate operation mode information of each constituent block. In the simulation means allocation step, the operation amount of each constituent block is estimated based on the operation mode information and the analysis result in the communication amount analysis step.

According to a ninth aspect of the invention, in the seventh or eighth aspect of the invention, in the simulation means assigning step, the cycle-based simulation means and the event-driven simulation means are assigned as the simulation means.

According to the present invention, the operation amount of each constituent block is estimated based on the communication amount of each constituent block of the system operation model, and the cycle-based simulation means and the event driven simulation means are selected according to the operation amount. By allocating the constituent blocks, a relatively small amount of operation can be simulated by event driven simulation, and the overall simulation can be speeded up.

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. The present invention is not limited to this embodiment, and may be implemented in various modes without departing from the scope of the invention.

(Embodiment 1) FIG. 1 shows all steps of a system simulation method according to Embodiment 1 of the present invention. This system simulation method uses an architecture that realizes a system operation model of a design upper level with cycle accuracy. It is used when simulating in.
As a simulation means at that time, a hardware simulator on a computer and a hardware emulator made of a programmable device are used together.

In the operation simulation process of step S1, the system operation model 100 of the design upper level shown in FIG.
A motion simulation is carried out using. This behavior model 100 includes N (N> 1) functional blocks 100.
, 1001, ... Execute the system operation by exchanging data via each communication path 1002. In this step, a record of data exchange between the functional blocks 1001 and 1001 generated as the simulation progresses is left, and the record content of the data exchange is as shown in FIG. The road identifier and the amount of data.

Regarding the operation execution and data transfer of each functional block 1001, there are a calculation model executed assuming a specific synchronization, a calculation model executed by an asynchronous trigger from a system input as a starting point, and the like. Can be taken. In the operation model 100, the functional blocks 1001, 1001, ... Correspond to specific system architecture constituent elements (eg, CPU, memory, etc.), and the communication path 1002 between the functional blocks 1001, 1001 is 4, the system bus 10
It may be assigned to the communication path 10021 passing through 020. Furthermore, the operation simulation may be executed based on data exchange in transaction units.

In the communication amount analyzing step of step S2, the process shown in FIG.
As shown in FIG. 7, in step Sa1, communication paths 1002, 1002, ... Between the functional blocks 1001, 1001.
To list. In step Sa2, the communication path 1002 is searched from the list. In step Sa3,
The data transfer records created in step S1 are totaled, and the data amount of communication (hereinafter, referred to as communication amount) performed via the searched communication path 1002 is calculated. Then, when the determination in step Sa4 is NO, that is, when the calculation of the communication amount in all the communication paths 1002, 1002, ... Is completed, the process proceeds to step S3.

In the simulation means allocation step of step S3, steps Sb1 to Sb7 shown in FIG.
By the processing of FIG.
The simulation means (hardware simulator and hardware emulator on the computer) assigned to the cycle accuracy model corresponding to 01 is determined. Note that, here, the behavior model 100 includes six functional blocks 1001 to 1001 of A to F as shown in FIG.
Shall have ... Also, A and B function block 1
For 001, only a simulator on a computer can be applied as a simulation means, for the E and F function blocks 1001, only a hardware emulator can be assigned as a simulation means, and for the C and D function blocks 1001, a simulation can be performed. It is assumed that both a hardware emulator and a simulator on a computer can be applied as means.

First, in step Sb1, the six function blocks 1001, 1001, ... Of A to F are set as an initial group 3001 of function blocks 1001, 1001 ,. Functional blocks 1001,1
001, ... and an initial group 3002. Specifically, an initial group 3001 composed of E and F function blocks 1001 and 1001 and an A and B function block 1001 to which only a simulator on a computer can be assigned.
The subgroup 3003 of 1001 is divided into an initial group 3002 in which C and D functional blocks 1001 and 1001 to which both a hardware emulator and a simulator on a computer can be assigned are added. And
Based on the communication traffic for each communication path 1002 collected in step S2, the boundary communication traffic X, which is the communication traffic on the boundary communication path composed of the two communication paths 1002 and 1002 crossing between the initial groups 3001 and 3002, is calculated. .

In step Sb2, the A to D function blocks 100 of the initial group 3002 to which both the simulator on the computer and the hardware emulator can be assigned.
A list of combinations that divide 1,1001, ... into two groups is listed. Then, in step Sb3, a combination is selected from the list to select all the functional blocks 100.
A new grouping candidate for 1,1001, ... Is created, and in step Sb4, the border traffic Y of the created grouping candidate is calculated.

In step Sb5, it is determined whether or not the boundary communication amount X of the current grouping is larger than the boundary communication amount Y of the current grouping candidate (X> Y). If the determination is YES, the process moves to step Sb6, the grouping and the boundary traffic are both changed from the current one to the current one, and then the process moves to step Sb7. On the other hand, when the determination is NO, the process proceeds to step Sb7 while maintaining the current grouping and border traffic. In step Sb7, it is determined whether or not there is another grouping candidate that can be combined. When the determination is YES,
It returns to step Sb3. On the other hand, when the determination is NO, the process ends. In this way, as long as there are possible grouping candidates that can be combined, the processing of steps Sb3 to Sb6 is repeated, whereby the E and F functional groups 1 to which only the hardware emulator can be assigned.
The initial group 3001 of 001, 1001, ... Is included, a group to which a hardware emulator is assigned, a group to which a simulation on a computer is assigned, and a grouping having a minimum boundary communication amount is obtained.

In the simulation means assigning step of step S4, the simulation means assigned according to the grouping obtained in step S3 executes the simulation of the corresponding cycle accuracy model.

Next, the specific procedure of the simulation method configured as described above will be described with reference to the system operation model 100 shown in FIG. 8A, and the architecture 102 shown in FIG. 8B for realizing this operation model 100. It will be explained using and.

Here, the behavior model 100 is 3 of A to C.
., And the architecture 102 includes an A function block 1001.
CPU 1021 for realizing the above, and B functional block 1001
1022 for realizing the above, and C functional block 1001
And a specific function hardware block 1023 for realizing the above. In executing the simulation with cycle accuracy of the architecture 102, the CPU 10
21 is executable only by the simulator on the computer, the specific function hardware block 1023 is executable only by the emulator, and the memory 1022 is executable by both.

First, in the operation simulation step of step S1, a simulation of the operation model 100 is executed in synchronization with a cycle of a predetermined unit time T based on the scenario shown in FIG. With the progress of this simulation, as shown by a dashed arrow in FIG.
Data is transmitted and received between 01, 1001, ... As a result, as shown in FIG. 10, data transmission and reception including a time when communication is performed, a communication path 1002 through which the communication is performed, and the communication amount thereof. The record of is obtained.

Next, in the communication amount analyzing step of step S2, the total communication amount in each communication path 1002 as shown in FIG. 11 is obtained based on the data transfer record.

Thereafter, in the simulation means allocating step of step S3, initial grouping and calculation of the boundary traffic X in the initial grouping are performed, and then grouping candidates are created and the grouping candidates are grouped. Boundary communication amount Y in is calculated. In this example, only the B functional block 1001 has no allocation constraint of the simulation means, so the grouping is performed by the initial grouping shown in FIG. 12A and one grouping candidate shown in FIG. There are only two ways. Then, the boundary traffic X is X = 20 in the initial grouping.
It is Mbyte, and X = 34 Mbyte in the grouping candidate
Since it is (> 20 Mbyte), the initial grouping is selected. As a result, as shown in FIG.
21 and the memory 1022 are assigned a simulator on a computer, and the specific function block 1023 is assigned a hardware emulator.

Then, in the simulation execution step of step S4, the simulation means assigned in the step S3 executes a cycle-accurate simulation.

Therefore, according to this embodiment, the architecture 1 for realizing the system after performing the operation simulation of the system operation model 100 of the upper design level
When performing the simulation with the cycle accuracy of 02, the functional block 1001,
The amount of communication between 1001 is recorded, and the amount of communication between the simulator on the computer and the hardware emulator assigned to the functional components of the system architecture 102 corresponding to the functional blocks 1001, 1001, ... Is minimized. As described above, since the simulation means are assigned and the simulation is performed by the assigned simulation means, the communication amount between the simulator on the computer and the hardware emulator can be minimized. Therefore,
Under the condition that the communication speed between the computer side and the emulator side is a bottleneck, it is possible to suppress the decrease in simulation speed due to such communication speed, and as a result, design verification and performance analysis of the system architecture. It is possible to shorten the design period required for the above.

In the above embodiment, the amount of communication is given by the amount of data.
It is also possible to give it by the above-mentioned number of times of access or an arbitrary evaluation function having the number of times of access and the amount of data as arguments.

(Embodiment 2) FIGS. 14 and 15 show details of the communication amount analysis step (step S2) and the simulation means allocation step (step S3) in the system simulation method according to the second embodiment of the present invention, respectively. ing. The same parts as those in the first embodiment are designated by the same reference numerals.

In the present embodiment, the allocation of the simulator and the hardware emulator on the computer as the simulation means is changed for each period divided by a predetermined unit time in order to cope with the change in the communication amount accompanying the progress of the simulation. Done

Specifically, in the communication amount analysis step of step 2, as shown in FIG. 14, the processing of step Sc3 is different from the processing of step Sa3 (see FIG. 5) in the first embodiment, and this step Sc3 Then, step S1
Each communication channel 100 based on the record of data transfer created in
It is configured to perform the aggregation for each 2 for every predetermined unit period, and let it be the corresponding communication amount.

Further, in the simulation means allocation step of step S3, as shown in FIG.
And the processing of step Sd9 is added to the processing of step S3 in the first embodiment.
In d8 and step Sd9, the simulation means is assigned for each period, and thereby the schedule for assigning the computer simulator and the hardware emulator for each period is obtained. The rest of the configuration is the same as that of the first embodiment, and therefore the description is omitted.

The system simulation method configured as described above will be specifically described using the same operation simulation as in the first embodiment. The predetermined unit period is 10T period. In the operation simulation process of step S1, the first simulation as shown in FIG.
It is assumed that the aggregated amount of communication for each communication channel 1002 in the 10T period and the aggregated amount of communication for each communication channel 1002 in the second 10T period are obtained.

In this case, in the first 10T period, the CPU 1021 of the system architecture 102 (see FIG. 8B) in the operation model 100 (see FIG. 8A).
A functional block 1001 corresponding to
2 corresponding to the B functional block 1001 and the C functional block 100 corresponding to the specific functional hardware block 1023.
1 is a group of A and B functional blocks 1001,
At the time of dividing the group into the group of the C function block 1001, the boundary communication amount X becomes X = 0, so that grouping is selected. On the other hand, in the second 10T period, the group of A function block 1001 and B and C
In the case of dividing into groups of the functional block 1001), the boundary communication amount X becomes X = 0, so that grouping is selected.

As a result, when allocating the first 10T period, as shown in FIG. 17A, a simulator on a computer is allocated to the CPU 1021 and the memory 1022, and a hardware emulator is allocated to the specific function block 1023. On the other hand, when allocating the second 10T period, as shown in FIG.
A simulator on a computer and a hardware emulator to the specific function block 1023 are successively assigned, and the simulation means assigned to the memory 1022 is changed from the simulator on the computer to the hardware emulator.

Therefore, according to the present embodiment, when the operation simulation of the system operation model 100 of the upper design level is performed, each communication path 1002 is executed every predetermined unit period 10T.
Communication is calculated, a schedule is created in which the allocation of the simulator and the hardware emulator on the computer is changed every 10T of the unit period, and the simulation is performed while allocating the system simulation means based on this schedule. As a result, even if the traffic volume changes significantly over time, the traffic volume between the simulator on the computer and the hardware emulator can be suppressed on average,
High-speed co-simulation can be executed.

(Embodiment 3) FIG. 18 shows a simulation means allocation step in a system simulation method according to Embodiment 3 of the present invention. The same parts as those in the first embodiment are designated by the same reference numerals.

In this embodiment, the system operation model 10
The operation amount of each functional block 0 of 0 is analyzed, and the cycle-based simulation means and the event driven simulation means are assigned as the simulation means based on the operation amount.

Specifically, in this embodiment, step S
The simulation means allocation process of 3 is different from that of the first and second embodiments.

First, in step Se1, the behavior model 1
The functional blocks 1001, 1001, ... Of 00 are listed up, and in step Se2, the functional block 1001 is searched from the list. Next, in step Se3, the motion amount Z of the searched functional block 1001 is calculated. Here, the movement amount Z is obtained based on the communication amount obtained in the communication amount analysis step of step S2, and is the sum of the communication amounts input and output in the function block 1001, that is, the function block. Each communication path 100 between 1001 and other functional blocks 1001, 1001, ...
It is the sum of the communication traffic in 2. After that, step Se
At 4, it is determined whether the motion amount Z of the functional block 1001 exceeds the reference value (motion amount Z> reference value).

Then, the determination in step Se4 is YES.
If so, the process proceeds to step Se5 and the cycle-based simulation means is assigned. On the other hand, when the determination is NO, the process moves to step Se6 and the event driven simulation means is assigned. The above processing is performed for all the functional blocks 1001, 1001, ..., And simulation means is assigned to each functional block 1001.

The system simulation method configured as described above is applied to the system operation model 100 and system architecture 102 of FIG. 8 and the communication path 10 of FIG.
A detailed description will be given by using the summation of communication amount for each 02. The reference value of the motion amount Z, that is, the reference value of the input / output data amount is 50 Mbytes.

In this case, the A function block 1001, B function block 1001, C of the system operation model 100
As shown in FIG. 19, the respective operation amounts Z of the functional block 1101 are Z = 34 Mbyte (<50 Mbyte) and Z, respectively.
= 54 Mbyte (> 50 Mbyte), Z = 20 Mbyte (<5
0 Mbyte). Therefore, the operation amount Z exceeds the reference value only in the B functional block 1001, that is, in the memory 1022 of the system architecture 102. As a result, the cycle-based simulation means is assigned only to the memory 1022 having a large operation amount Z, while the event-driven simulation means is assigned to the CPU 1021 and the specific function hard block 1023 having a small operation amount Z. The processing overhead can be reduced, and the simulation speed can be increased accordingly.

Therefore, according to the present embodiment, the operation amount Z is calculated from the communication amount of each functional block 1001,
Since the cycle-based simulation means is assigned only to the functional hard block corresponding to the functional block 1001 whose operation amount Z is equal to or larger than the reference value, the event-driven simulation means is assigned to the other functional hard blocks. It is possible to avoid the processing overhead that occurs when the functional hard block is simulated by the cycle-based simulation means, and the period required for the simulation can be shortened accordingly.

In the third embodiment described above, the amount of input / output data is used as the communication amount, and the operation amount Z is determined based on this communication amount. However, as a calculation formula for obtaining the operation amount Z, Can also use the average amount of data per access, the number of accesses, etc.

In the third embodiment, the operation amount Z is obtained only based on the communication amount.
In order to allocate the event driven simulation means to the functional hard block corresponding to the functional block 1001 that is not enabled, the operation of the functional block 1001 is observed by observing the control signal such as the operation enable signal for each functional block 1001 in the operation simulation process. The mode information may be generated, and the operation amount Z may be estimated based on the operation mode information and the communication amount in the simulation means allocation step.

[0059]

As described above, according to the first aspect of the present invention, the communication amount in each constituent block of the system is analyzed from the result of the operation simulation of the system operation model of the design upper level performed in advance, and based on the communication amount, Since the simulation means is assigned to the embodied system configuration block, for example, when a simulator and a hardware emulator on a computer are used as the simulation means, the simulation means can reduce the communication traffic between the simulation means. By allocating as described above, it is possible to prevent a decrease in simulation speed due to a slow communication speed between both simulation means, and shorten the design period such as design verification and performance analysis.

According to the ninth aspect of the present invention, the operation amount of each constituent block is estimated from the communication amount of each constituent block of the system operation model of the design upper level, and the cycle-based simulation means and the event driven simulation are performed according to the operation amount. I decided to assign means and
It is possible to reduce the overhead of the cycle-based simulation means so that the entire simulation can be performed in a short period of time, and as a result, it is possible to contribute to shortening the design period.

[Brief description of drawings]

FIG. 1 is a flowchart showing an overall configuration of a system simulation method according to a first embodiment of the present invention.

FIG. 2 is a diagram showing an example of a system operation model.

FIG. 3 is a diagram showing an example of record items of data exchange between functional blocks in an operation simulation.

FIG. 4 is a diagram showing an example of a system architecture.

FIG. 5 is a flowchart showing details of a communication amount analysis process.

FIG. 6 is a flowchart showing details of a simulation means allocation step.

FIG. 7 is a diagram showing grouping of functional blocks.

FIG. 8 is a diagram additionally showing an operation model (a) and an architecture (b) used for specific description.

FIG. 9 is a diagram showing a scenario of data exchange between functional blocks as the operation simulation progresses.

FIG. 10 is a diagram showing recording of data exchange between functional blocks.

FIG. 11 is a diagram showing a communication amount for each communication path between functional blocks.

FIG. 12 is a diagram collectively showing an initial groove division (a) and a groove division candidate (b) of a functional block.

FIG. 13 is a diagram showing allocation of a simulator and a hardware emulator on a computer.

FIG. 14 is a flowchart showing details of a communication amount analysis step in the system simulation method according to the second embodiment of the present invention.

FIG. 15 is a flowchart showing details of a simulation means allocation step.

FIG. 16 is a diagram showing a communication amount for each communication path between the functional blocks in each of the first and second periods.

FIG. 17 is a diagram showing the allocation of simulation means in the first period (a) and the second period (b) together.

FIG. 18 is a flowchart showing details of a simulation means allocation step in the system simulation method according to the third embodiment of the present invention.

FIG. 19 is a diagram showing an operation amount of each functional block.

[Explanation of symbols]

100 system operation model 1001 function block (configuration block of operation model) 102 system architecture 1021 CPU (architecture configuration block) 1022 memory (architecture configuration block) 1023 specific function hard block (architecture configuration block) Z operation amount

Claims (9)

[Claims] 1. A system simulation method for simulating the architecture of a digital system with cycle accuracy, comprising: an operation simulation step of simulating a system operation model of a design upper layer; and a simulation result of the operation simulation step. A communication amount analyzing step of analyzing a communication amount of data exchange in each constituent block of the system, and a simulation means for each constituent block of the system embodied in a lower design stage based on an analysis result in the communication amount analyzing step. And a simulation means allocating step for allocating. 2. The system simulation method according to claim 1, wherein, in the simulation means allocation step, when there is a restriction on allocation of the simulation means in the constituent block, the restriction and the analysis result in the communication amount analysis step are arbitrated. A system simulation method characterized by the above. 3. The system simulation method according to claim 2, wherein in the simulation means allocating step, a plurality of simulation means are allocated so that a communication amount between the plurality of simulation means becomes small. 4. The system simulation method according to claim 3, wherein in the simulation means allocation step, a hardware simulator on a computer and a hardware emulator using a programmable device are allocated as the simulation means. Simulation method. 5. The system simulation method according to claim 1, wherein in the operation simulation step, the system is divided into a plurality of functional blocks to perform a simulation. 6. The system simulation method according to claim 1, wherein the communication amount analyzing step analyzes a temporal transition of the communication amount, and the simulation means assigning step analyzes the communication amount analyzed in the communication amount analyzing step. A system simulation method characterized by allocating simulation means in accordance with the temporal transition of. 7. The system simulation method according to claim 1, wherein in the simulation means allocating step, the operation amount of the constituent block is estimated based on the analysis result of the communication amount of each constituent block, and the simulation is performed based on the operation amount. A system simulation method characterized by allocating means. 8. The system simulation method according to claim 7, wherein in the operation simulation step, an input signal for controlling an operation mode of each constituent block is observed to generate operation mode information of each constituent block, and the simulation means allocation is performed. In the step, the operation amount of each constituent block is estimated based on the operation mode information and the analysis result in the communication amount analysis step. 9. The system simulation method according to claim 7, wherein in the simulation means allocation step, cycle-based simulation means and event-driven simulation means are allocated as the simulation means.