JP2003061345A - Artificial resonance system switching power circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent generation of abnormal oscillation with an insufficiently charged capacitor of an oscillation circuit. SOLUTION: A trigger signal is detected from a trigger detection circuit 6 relating to turning off of the power MOSFET1. Logical operation of the rigger signal and an oscillation frequency limiting signal is performed in a fix circuit 4 to generate a set signal. A charge signal of fixed pulse width or more is generated by the set signal from the fix circuit 4 from a charge signal generating circuit 7. A switching element 5 is turned on. A capacitor C of an oscillation circuit 3 is charged.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a quasi-resonant switching power supply circuit used in electronic equipment such as televisions and audio equipment.

[0002]

2. Description of the Related Art In a quasi-resonant switching power supply circuit, a power MOSFET connected to a primary winding of a transformer is used.
The fall of the counter electromotive voltage that occurs when T is turned off is detected from the auxiliary winding, and the capacitor in the oscillation circuit of the IC is rapidly charged to accelerate the oscillation frequency.

FIG. 8 is a block diagram of an integrated circuit portion used in a conventional quasi-resonant switching power supply circuit. The frame of the broken line is the integrated circuit Q alone, Vcc terminal, TRG terminal, F
It has a B terminal, a SENSE terminal, a GATE terminal and a GND terminal. The integrated circuit Q is incorporated in the package P. The package P has a Vcc terminal, a TRG terminal, an FB terminal, a SOURCE terminal, and a DRAIN terminal.

The Vcc terminal and the Vcc terminal, the TRG terminal and the TRG terminal, the FB terminal and the FB terminal are connected, and the source / drain of the power MOSFET 1 is connected between the SOURCE terminal and the DRAIN terminal. The drain electrode of the sensor MOSFET 2 is connected to the drain of the power MOSFET 1.

The oscillating circuit 3 is an oscillator for generating a sawtooth wave signal. When the charging signal is applied from the fix circuit 4, the oscillating circuit 3 is a MOS.
The FET 5 is turned on, and the capacitor C in the oscillation circuit 3 is also charged through the MOSFET 5 to accelerate the charging speed. The oscillated sawtooth wave signal is converted into a pulse signal by the oscillating edge circuit 8 and applied to the latch circuit 9.

The charging signal can be obtained by logically operating the trigger signal TRG and the frequency limiting signal in the fix circuit 4. The trigger signal TRG generates a trigger terminal signal at the trigger terminal TRG in association with a signal generated from the auxiliary winding of the transformer described later when the power MOSFET 1 is turned off. Then, the trigger detection circuit 6 can detect the trigger terminal signal. In the frequency limiting signal, the signal from the oscillating circuit 3 is fed back to the fix circuit 4, and a certain period of time elapses after the oscillating signal is switched from H (high) to L (low) or from L to H. Generate with.

Reference voltage generating circuit 10 generates reference voltage Vref from power supply voltage Vcc applied to the Vcc terminal. The low voltage detection circuit 11 compares the power supply voltage Vcc with a predetermined voltage, generates a stop signal when the power supply voltage Vcc is equal to or lower than a predetermined voltage, and generates a stop release signal when the power supply voltage Vcc is equal to or higher than the predetermined voltage. The oscillator circuit 3 is oscillated.

On the contrary, the high-voltage detection circuit 12 has the power supply voltage V
When cc is higher than the specified voltage, a stop signal is detected and applied to the latch circuit 9 for latching. The abnormal overheat detection circuit 13 detects an abnormal temperature rise of the chip. When the chip rises to an abnormal temperature, a stop signal is applied to the latch circuit 9 and latched.

The oscillation level comparison circuit 15 is supplied with the reference voltage Vref from the reference voltage generation circuit 10 and the load voltage from the FB terminal and the sensor MOSF.
The sum voltage is compared with the voltage applied via ET2, and when the reference voltage is high, the signal generated is low level. However, when the voltage supplied according to the load voltage or the like becomes higher than the reference voltage, the oscillation level comparison circuit 15
Generates a high level signal from.

The pulse width modulation circuit 16 is composed of an RS flip-flop, and the pulse signal passing through the latch circuit 9 is applied to the SET terminal S via the inverter circuit 17. Further, the RSET terminal R has an oscillation level comparison circuit 39
The signal from is added. The signal from the Q bar terminal of the pulse width modulation circuit 16 is applied to the gates of the power MOSFET 1 and the sensor MOSFET 2 via the driver 18.

FIG. 2 is a circuit diagram of a quasi-resonant switching power supply circuit using the integrated circuit Q. A commercial power supply Vin for terminals X and Y is applied to the full-wave rectifier circuit 20 via a choke coil 21. The transformer 22 includes a primary winding 23, a secondary winding 24 for extracting an output voltage, and an auxiliary winding 25. One end of the primary winding 23 is connected to the terminal S of the full-wave rectifier circuit 20, and the other end is connected to the package P.
Connected to the terminal T of the full-wave rectifier circuit 20 via the drain / source electrode of the MOSFET 1.

The smoothing circuit 27 smoothes the DC voltage rectified by the full-wave rectifying circuit 20. The rectified and smoothed DC voltage is applied to the VCC terminal of the package P via the starting resistor 28 and becomes the power supply voltage Vcc of the integrated circuit. Further, one end of the auxiliary winding 25 is connected to the Vcc via the diode 30.
Connected to the terminal. Further, it is also connected to the TRG terminal via the resistor 45.

A diode 31 and a capacitor 32 are connected to the secondary winding 24 of the transformer 22. The photocoupler 33 includes a light emitting diode 34 and a phototransistor 35, and a resistor 36 and a resistor 37 are connected to one end of the phototransistor 35.

The transistor 40 detects a change in the load voltage taken out from the terminals M and N, and has dividing resistors 41 and 42 connected to the base and a Zener diode 43 connected to the emitter.

Next, the operation will be described. The commercial power supply now applied between terminals X and Y is rectified by the full-wave rectifier circuit 20,
After being smoothed by the smoothing circuit 27, it is applied as a power supply voltage Vcc to the Vcc terminal of the package P via the starting resistor 28.

When the power supply voltage Vcc is applied to the Vcc terminal, the reference voltage generating circuit 10 generates the reference voltage Vref. When the power supply voltage Vcc becomes equal to or higher than the set voltage, the stop release signal from the low voltage detection circuit 11 is applied to the oscillation circuit 3, and the oscillation circuit 3 generates a sawtooth wave signal.

The sawtooth wave signal is applied to the oscillation edge circuit 8, converted into a pulse signal and applied to the latch circuit 9. At this time, since the stop signal is not detected from the high voltage detection circuit 12, the pulse signal is transmitted through the latch circuit 9 and the inverter circuit 17 to the SET terminal S of the pulse width modulation circuit 15.
Join in.

As shown in FIG. 3, the pulse width modulation circuit 16
When a pulse signal is applied to the SET terminal S of, the pulse width modulation circuit 16 is inverted and the signal at the Q bar terminal becomes low level. At this time, the driver 18 has the low voltage detection circuit 1
Since the stop release signal from 1 is applied, the driver circuit 18 is in the operating state. The low level signal at the Q bar terminal of the pulse width modulation circuit 16 is inverted to a high level signal by the driver circuit 18, and the power MOS
It is added to the respective gates of FET1 and sensor MOSFET2.

The power MOSFET 1 and the sensor M
When a high level signal inverted by the driver circuit 18 is applied to the gate of the OSFET 2, these power MOS
The FET1 and the sensor MOSFET2 are turned on. Then, the rectified and smoothed DC voltage is applied to the primary winding of the transformer via the drain / source of the power MOSFET 1.

The secondary winding 24 of the transformer 22 is responsive to the DC voltage applied to the primary winding 23 of the transformer 22.
Then, a predetermined secondary voltage is obtained. The obtained secondary voltage is rectified and smoothed by the diode 31 and the capacitor 32, taken out from the terminals M and N, and supplied to the load as a load voltage.

Therefore, a rectified current from the commercial power source flows through the primary winding 23 of the transformer 22 in the device via the drain / source of the power MOSFET 1. A current flows through the secondary winding 24 of the transformer 22 according to the current flowing through the primary winding 22 of the transformer 22 to obtain a predetermined load voltage.

When the load voltage is equal to or lower than the predetermined voltage and the drain current value of the power MOSFET 1 is equal to or lower than the reference value, the pulse width modulation circuit 16 continues to set, so that the signal at the Q bar terminal of the pulse width modulation circuit 16 is at a low level. The power MOSFET 1 continues to be turned on as it is.

The change in the load voltage taken out from the terminals M and N is detected by the dividing resistors 41 and 42, and the base voltage of the transistor 40 is changed. That is, when the load voltage rises, the base voltage of the transistor 40 rises, and the current I flowing through the light emitting diode 34 through the transistor 40.
D increases and light emission also increases. As a result, the resistance value of the phototransistor 35 decreases, and the feedback voltage FB applied to the terminal increases.

The feedback voltage FB corresponding to the load voltage applied to the oscillation level comparison circuit 15 and the sensor M
When the sum voltage with the voltage applied through the OSFET 2 becomes slightly larger than the reference voltage Vref from the reference voltage generation circuit 10, the oscillation level comparison circuit 15 generates a high level signal and the pulse width modulation circuit 16 outputs RS
A reset signal is applied to the ET terminal R to bring the signal at the Q bar terminal of the pulse width modulation circuit 16 to a high level.

Therefore, since the signal applied to the gate of the power MOSFET 1 via the driver circuit 18 becomes low level, the power MOSFET 1 is turned off, and the current from the commercial power source is supplied to the primary side winding 23 of the transformer 22 in the equipment. Does not flow.

As shown in FIG. 4, the power MOSFET
1 Drain-source voltage VDS is power MOSFET
At the moment when 1 is turned off, the primary winding 23 of the transformer 22
The voltage once rises due to the counter electromotive voltage generated by the energy stored in the capacitor and then decreases at the same time when the release of the energy is completed. At this time, the voltage of the auxiliary winding 25 generated according to the primary winding 23 is changed by the resistor 45. And TRG terminal and GN
TRG is integrated by the capacitor CO provided between D and
A terminal signal is generated and added to the TRG terminal. The TRG
The TRG terminal signal applied to the terminal is applied to the trigger detection circuit 6 to generate a trigger signal.

The generated trigger signal TRG is applied to the fix circuit 4. As shown in FIG. 5, the fix circuit 4 logically operates the internally generated oscillation limiting signal and the trigger signal, and generates a charging signal when both are at a low level. Then, the MOSFET 5 is turned on and the MOS
Since the capacitor C is also charged through the FET 5, the charging of the capacitor C is accelerated to generate a sawtooth wave signal.

The sawtooth wave signal oscillated from the oscillating circuit 3 is converted into a pulse signal by the oscillating edge circuit 8 and applied to the SET terminal of the pulse width modulating circuit 16, and the Q bar terminal of the pulse width modulating circuit 16 is connected. The signal goes low again. The low level signal at the Q bar terminal of the pulse width modulation circuit 16 is passed through the driver circuit 18 to the power MOSF
The power MOSFET 1 and the sensor M are added to the respective gates of the ET1 and the sensor MOSFET2.
Turn on OSFET2.

Therefore, a rectified current from the commercial power source flows through the primary winding 23 of the transformer 22 in the device via the drain / source of the power MOSFET 1. A current flows through the secondary winding 24 of the transformer 22 according to the current flowing through the primary winding 22 of the transformer 22 to obtain a predetermined load voltage.

[0030]

In the above quasi-resonant switching power supply circuit, the trigger signal is detected based on the TRG terminal signal generated when the power MOSFET connected to the primary winding of the transformer is turned off. Then, the trigger signal rapidly charges the capacitor of the oscillator circuit to accelerate the oscillation frequency. In order to prevent the oscillation frequency from becoming too fast, a frequency limiting signal is generated in association with a feedback signal from the oscillation circuit, and a charge signal is generated by performing a logical operation of the trigger signal and the frequency limiting signal. , To determine whether to charge the capacitor.

By the way, as shown in FIG. 4, when the load is light, the load voltage is high, and the feedback voltage FB becomes a predetermined voltage or more with a small current ID. Therefore, the sum voltage of the feedback voltage FB applied to the oscillation level comparison circuit and the voltage applied via the sensor MOSFET becomes larger than the reference voltage Vref from the reference voltage generation circuit, and the oscillation power MOSFET is turned off quickly. Therefore, the ON / OFF cycle of the power MOSFET becomes short.

On the other hand, as shown in FIG. 5, a power MOSFET
When the ON / OFF cycle of is shortened and the oscillation frequency is close to the limit value, the trigger signal and the frequency limit signal are displaced from each other, and the pulse width of the charging signal is reduced.

As shown in FIG. 7, when the pulse width of the charging signal becomes small, the capacitor is not sufficiently charged and the gate is turned on when the drain-source voltage is at the minimum value, causing abnormal oscillation that does not result in zero-cross oscillation operation. .

[0034]

According to the present invention, a pulse modulation circuit is set by an oscillation signal oscillated from an oscillation circuit, a power switching element connected between a primary winding of a transformer and a ground is turned on, and a load voltage In a quasi-resonant switching power supply circuit that resets the pulse modulation circuit and turns off the power switching element with a signal generated when the feedback voltage fed back according to the magnitude exceeds a predetermined voltage, the switching element is OF
A trigger detection circuit for detecting a trigger signal based on a signal generated in relation to the F, and an oscillation frequency limiting signal generated based on the trigger signal and a signal fed back from the oscillation circuit are logically operated and set. It comprises a fix circuit for generating a signal and a charge signal generating circuit for generating a charge signal having a fixed pulse width or more by a set signal from the fix circuit, and the switching element is turned on by the charge signal.
Provided is a quasi-resonant switching power supply circuit, which is characterized in that a capacitor of an oscillation circuit is sufficiently charged.

In the present invention, the charging signal generating circuit is RS-F.
A quasi-resonant switching power supply circuit that is F is provided.

The present invention provides a quasi-resonant switching power supply circuit in which the RS-FF is set by a pulse signal from a fix circuit and reset by a reset signal generated at the end of charging of the capacitor by an oscillation circuit.

[0037]

DETAILED DESCRIPTION OF THE INVENTION The present invention will be described with reference to FIGS.

FIG. 1 is a block diagram of an integrated circuit used in the switching power supply circuit of the present invention. The basic operating principle and the circuit configuration are the same as those described in the section of the related art, and thus will be briefly described.

DRAIN terminal of package P and SOU
The source electrode / drain electrode of the power MOSFET 1 is connected between the RCE terminals. Also power MOSF
The drain electrode of the sensor MOSFET 2 is connected to the drain electrode of ET1.

The oscillating circuit 3 is an oscillator which generates a sawtooth wave signal, and when the charging signal J is applied from the fix circuit 4, the oscillator circuit 3
The SFET 5 is turned on, and the capacitor C in the oscillation circuit 3 is also charged through the MOSFET 5 to accelerate the charging speed. The oscillated sawtooth wave signal is converted into a pulse signal by the oscillating edge circuit 8 and applied to the latch circuit 9.

The fix circuit 4 logically operates the trigger signal TRG detected by the trigger detection circuit 6 and the frequency limiting signal to generate a set signal. RS-FF7
Is reset by applying the set signal to the set terminal S to generate the charge signal J, and applying the reset signal generated when the capacitor C is fully charged from the oscillator circuit 3 to the reset terminal.

As shown in FIG. 4, the trigger signal TR
G rises once due to the counter electromotive voltage generated by the energy stored in the primary winding 23 of the transformer 22 at the moment when the power MOSFET 1 is turned off, and then decreases at the same time when the energy release is completed. The voltage of the auxiliary winding 25 generated according to the winding 22 is integrated by the resistor 45 and the capacitor CO provided between the TRG terminal and GND to generate a TRG terminal signal, which is applied to the TRG terminal.

As for the frequency limiting signal, the signal from the oscillation circuit 3 is fed back to the fix circuit 4, and the fixed frequency period is passed after a certain period from the moment when the oscillation signal is switched from H (high) to L (low) or from L to H. Generated within 4.

Next, the operation will be described. The commercial power source applied between the terminals X and Y shown in FIG. 2 is rectified by the full-wave rectifier circuit 20, smoothed by the smoothing circuit 27, and then is supplied to the Vcc terminal of the package P as the power source voltage Vcc via the starting resistor 28. Added.

When the power supply voltage Vcc is applied to the Vcc terminal, the reference voltage generating circuit 10 generates the reference voltage Vref. When the power supply voltage Vcc becomes equal to or higher than the set voltage, the stop release signal from the low voltage detection circuit 10 is applied to the oscillation circuit 3, and the oscillation circuit 3 generates a sawtooth wave signal.

The sawtooth wave signal is applied to the oscillation edge circuit 8, converted into a pulse signal and applied to the latch circuit 9. At this time, since the stop signal is not detected from the high voltage detection circuit 12, the pulse signal is transmitted through the latch circuit 9 and the inverter circuit 17 to the SET terminal S of the pulse width modulation circuit 16.
Join in.

As shown in FIG. 3, the pulse width modulation circuit 16
When a pulse signal is applied to the SET terminal S of, the pulse width modulation circuit 16 is inverted and the signal at the Q bar terminal becomes low level. At this time, the driver 18 has the low voltage detection circuit 1
Since the stop signal from 1 is applied, the driver circuit 11 is in the operating state. The low level signal at the Q bar terminal of the pulse width modulation circuit 16 is inverted to a high level signal by the driver circuit 18, and the power MOSFE
Add to the respective gates of T1 and sensor MOSFET2.

The power MOSFET 1 and the sensor M
When a high level signal inverted by the driver circuit 18 is applied to the gate of the OSFET 2, these power MOS
The FET1 and the sensor MOSFET2 are turned on. Then, the rectified and smoothed DC voltage is applied to the primary winding of the transformer via the drain / source of the power MOSFET 1.

The secondary winding 24 of the transformer 22 is responsive to the DC voltage applied to the primary winding 24 of the transformer 22.
Then, a predetermined secondary voltage is obtained. The obtained secondary voltage is rectified and smoothed by the diode 31 and the capacitor 32,
It is taken out from the terminals M and N and supplied to the load as a load voltage.

Therefore, a rectified current from the commercial power source flows through the primary winding 23 of the transformer 22 in the device via the drain / source of the power MOSFET 1. A current flows through the secondary winding 24 of the transformer 22 according to the current flowing through the primary winding 22 of the transformer 22 to obtain a predetermined load voltage.

When the load voltage is below a predetermined voltage and the drain current value of the power MOSFET 1 is below a reference value,
Since the pulse width modulation circuit 16 continues to set, the signal at the Q bar terminal of the pulse width modulation circuit 16 remains low level and the power MOSFET 1 continues to be turned on.

The change in the load voltage taken out from the terminals M and N is detected by the dividing resistors 41 and 42, and the base voltage of the transistor 40 is changed. That is, when the load voltage rises, the base voltage of the transistor 40 rises, and the current I flowing through the light emitting diode 34 through the transistor 40.
D increases and light emission also increases. As a result, the resistance value of the phototransistor 35 decreases, and the feedback voltage FB applied to the terminal increases.

The feedback voltage FB corresponding to the load voltage applied to the oscillation level comparison circuit 15 and the sensor M
When the sum voltage with the voltage applied through the OSFET 2 becomes slightly larger than the reference voltage Vref from the reference voltage generation circuit 10, the oscillation level comparison circuit 15 generates a high level signal and the pulse width modulation circuit 16 outputs RS
A reset signal is applied to the ET terminal R to bring the signal at the Q bar terminal of the pulse width modulation circuit 16 to a high level.

Therefore, since the signal applied to the gate of the power MOSFET 1 via the driver circuit 18 becomes low level, the power MOSFET 1 is turned off, and the current from the commercial power source is supplied to the primary winding 23 of the transformer 22 in the equipment. Does not flow.

As shown in FIG. 4, the power MOSFET 1
At the moment when is turned off, the voltage temporarily rises due to the counter electromotive voltage generated by the energy stored in the primary winding 23 of the transformer 22 and then decreases at the same time when the release of the energy is finished. The voltage of the auxiliary winding 25 generated according to the
The TRG terminal signal is generated by integration with the capacitor CO provided between them, and is added to the TRG terminal.

The TRG terminal signal is the trigger detection circuit 6
To generate a trigger signal TRG. The generated trigger signal TRG is applied to the fix circuit 4. The fix circuit 4 logically operates the internally generated oscillation limiting signal and the trigger signal, and generates a set signal when both are negative.

The set signal is added to RS-FF7,
The RS-FF7 is set and a charging signal is generated. As a result, the MOSFET 5 is turned on, and the capacitor C is charged also via the MOSFET 5, so that the sawtooth wave signal in which the charging of the capacitor C is accelerated is oscillated.

The sawtooth wave signal oscillated from the oscillation circuit 3 is converted into a pulse signal by the oscillation edge circuit 8,
It is added to the SET terminal of the pulse width modulation circuit 16, and the signal at the Q bar terminal of the pulse width modulation circuit 16 becomes low level again. The low level signal at the Q bar terminal of the pulse width modulation circuit 16 is the power MOSFET 1 and the sensor MOS.
These power M added to each gate of FET2
The OSFET1 and the sensor MOSFET2 are turned on.

Therefore, a rectified current from the commercial power supply flows through the primary winding 23 of the transformer 22 in the device via the drain / source of the power MOSFET 1. A current flows through the secondary winding 24 of the transformer 22 according to the current flowing through the primary winding 22 of the transformer 22 to obtain a predetermined load voltage.

As shown in FIG. 4, when the load is heavy, the voltage on the secondary side is slightly low, so the light emitting diode 34 is weak, and the resistance value of the phototransistor 35 is high, so the feedback voltage FB is low, and the drain of the power MOSFET 1 is low. Current I
Even if D flows, feedback voltage FB and sensor MOS
The sum voltage with the voltage applied via the FET2 does not immediately become higher than the reference voltage Vref from the reference voltage generation circuit 10.

However, when the load is light, the voltage on the secondary side is slightly high, so that the light emitting diode 34 emits light strongly, the resistance value of the phototransistor 35 decreases, the feedback voltage FB increases, and the drain current ID of the power MOSFET 1 increases.
The sum of the feedback voltage FB and the voltage applied via the sensor MOSFET 2 becomes larger than the reference voltage Vref from the reference voltage generation circuit 10, and a high level signal is output from the oscillation level comparison circuit 15. Occurs, the power MOSFET 1 is turned off.

When the power MOSFET 1 is turned off, as described above, the TRG terminal signal is generated from the voltage generated in the auxiliary winding 25, and the trigger signal TRG is generated from the trigger detection circuit 6 after being applied to the TRG terminal. To do. The generated trigger signal TRG is the fix circuit 4
Join in. Therefore, the fix circuit 4 includes an oscillator circuit 3
When the oscillation limit signal from is added, a set signal is generated.

The set signal is added to RS-FF7,
The RS-FF7 is set and the charging signal J is generated. As a result, the MOSFET 5 is turned on, and the capacitor C is also charged through the MOSFET 5, so that the charging of the capacitor C is accelerated and the oscillation frequency of the sawtooth wave signal is accelerated.

As described above, when the power MOSFET 1 is turned off earlier, the capacitor C is charged earlier, and when the oscillation frequency becomes higher and the oscillation frequency becomes close to the limit value, the cycle of the trigger signal TRG and the frequency limit signal is increased. The trigger circuit TR from the fix circuit 4
The pulse width of the set signal obtained by logically operating G and the frequency limiting signal becomes small, and the capacitor C may not be charged to 100%.

However, as shown in FIG. 6, in the present invention, the set signal is added to the RS-FF7, the RS-FF7 is set, and the charging signal J is generated. Therefore, fix circuit 4
The capacitor C is always charged 100% even if the pulse width of the set signal generated from is small. Therefore, the oscillator circuit 3 always oscillates a normal sawtooth wave signal signal.

[0066]

According to the quasi-resonant switching power supply circuit of the present invention, the switching element for controlling the load voltage is OF.
The trigger signal is detected by the trigger detection circuit in relation to the operation of F, and the set signal is generated by logically operating the trigger signal and the oscillation frequency limiting signal by the fix circuit, and the set signal is set by the charge signal generating circuit from the fix circuit. Since a charging signal with a certain pulse width or more is generated by the signal, even if the oscillation frequency increases at light load and the pulse width of the set signal detected from the fix circuit becomes small near the limit value, the oscillation circuit Can fully charge the capacitor.

Therefore, it can be prevented that the capacitor is not sufficiently charged, does not become a zero cross and causes abnormal oscillation, and noise is generated.

[Brief description of drawings]

FIG. 1 is a block diagram of an integrated circuit used in a quasi-resonant switching power supply circuit of the present invention.

FIG. 2 is a circuit diagram of a quasi-resonant switching power supply circuit using the present invention and a conventional integrated circuit.

FIG. 3 is a waveform diagram of a pulse width modulation circuit portion used in the present invention and the conventional quasi-resonant switching power supply circuit.

FIG. 4 is a signal waveform diagram of each part of a quasi-resonant switching power supply circuit according to the present invention.

FIG. 5 is a signal waveform diagram of a fix circuit portion of the present invention and the conventional quasi-resonant switching power supply circuit.

FIG. 6 is a waveform diagram showing a relationship between a charging signal and a charging voltage of a capacitor in the quasi-resonant switching power supply circuit of the present invention and the related art.

FIG. 7 is a waveform diagram showing a relationship between a charging voltage of a capacitor and a drain-source voltage of a power MOSFET of a conventional quasi-resonant switching power supply circuit.

FIG. 8 is a block diagram of an integrated circuit used in a conventional quasi-resonant switching power supply circuit.

[Explanation of symbols]

1 power MOSFET 3 oscillator circuits 4 fixed circuit 5 MOSFET 6 Trigger detection circuit 7 RS-FF 10 Reference voltage generation circuit 15 Oscillation level comparison circuit 16 pulse width modulation circuit 22 transformer 23 Primary winding 24 Secondary winding 25 auxiliary winding

Claims (3)

[Claims] 1. A pulse modulating circuit is set by an oscillating signal oscillated from an oscillating circuit, a power switching element connected between a primary winding of a transformer and a ground is turned on, and the power is fed back according to the magnitude of a load voltage. In a switching power supply circuit for resetting the pulse modulation circuit and turning off the power switching element with a signal generated when the feedback voltage exceeds a predetermined voltage, a signal generated in association with the turning off of the power switching element. A trigger detection circuit for detecting a trigger signal based on the above, a fix circuit for performing a logical operation of the trigger signal and an oscillation frequency limiting signal generated based on a signal fed back from the oscillator circuit to generate a set signal, and the fix circuit Charge signal that generates a charge signal with a certain pulse width or more by the set signal from the circuit A quasi-resonant switching power supply circuit comprising a generating circuit, wherein a switching element is turned on by the charging signal to sufficiently charge a capacitor of the oscillation circuit. 2. The quasi-resonant switching power supply circuit according to claim 1, wherein the charge signal generating circuit is an RS-FF. 3. The quasi-resonant switching method according to claim 2, wherein the RS-FF is set by a pulse signal from a fix circuit and reset by a reset signal generated at the end of charging of the capacitor by an oscillating circuit. Power supply circuit.