JP2003060693A - Data transfer unit and supervisory control method of buffer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To guarantee the quality of communication for each application by controlling a buffer while recognizing an application on packet data being transferred. SOLUTION: The data transfer unit being disposed in a network comprises a plurality of input circuits 211-21n, a switch circuit 20, a plurality of output circuits 221-22m, and a unit control circuit 23. The switch circuit comprises an application identifying circuit, an RED parameter setting circuit, and a buffer and controls disuse and delay of packet within the allowable range of each application by controlling the buffer using parameters prestored in a parameter management table in correspondence with the application.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer device and a buffer monitoring control method, and more particularly, to a data transfer device in protocol layer 2 or 3 and to guarantee communication quality in the data transfer device. The present invention relates to a buffer monitoring control method for performing traffic control according to the buffer usage status.

[0002]

2. Description of the Related Art In recent years, ATM (Asynchronous Transfer M
ode) cell, Ethernet (registered trademark) frame, IP (Inter
net Protocol) Data communication using packets is widely used. Then, due to the increase in data communication volume accompanying the spread of such data communication, congestion occurs in a data transfer device such as a router provided in the network, packet discard and delay occur, and such communication quality Are affecting the application.

Conventionally, as a buffer control method in a data transfer apparatus for suppressing packet discard due to congestion, a FIFO (Fast In Fast) for reading data in the order in which the data is written
Out) method is commonly used. But the FIFO
In the case of the method, the data of the buffer capacity is not discarded, but when the data amount exceeding the buffer capacity is received, the excess data is discarded. Increasing the buffer capacity in order to suppress the discarding of data causes a problem of increasing the delay time.

As a conventional technique for suppressing data discard and delay, packets are gradually discarded according to the congestion state of the packets, and TCP (Transemission Control P
The RED (Random) layer reduces the amount of data in the network by suppressing the packet transmission rate by the rotocol) layer.
m Early Discard) method has been proposed. The RED method does not discard data up to a certain buffer usage amount, and a data guarantee buffer minimum value (min-th: minimum-threshold),
When the buffer usage exceeds a certain value, the data discard buffer maximum value (max-t
h: maximum-threshold) and set min-th and max-th
In the state of the buffer usage amount between and, the data is discarded according to the buffer usage amount. But,
This RED method has a problem that the setting conditions become complicated when various kinds of applications are assumed.

Another conventional technique for suppressing packet discard and delay is, for example, Japanese Patent Laid-Open No. 2000-498.
The technology described in Japanese Patent No. 53, etc. is known. This conventional technique relates to a buffer management method for guaranteeing a minimum data communication amount required by an application. However, this conventional technique has a problem that a bandwidth management control function for guaranteeing the minimum rate is required, and that a buffer capacity for guaranteeing the minimum rate for the line needs to be secured.

[0006]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention As mentioned above, RE
The conventional technique of the D method has a problem that setting conditions become complicated when a variety of applications are assumed. In addition, the prior art described in the publication is
There is a problem in that a bandwidth management control function for guaranteeing the minimum rate is required, and a buffer capacity for guaranteeing the minimum rate for the line must be secured.

An object of the present invention is to solve the above-mentioned problems of the prior art, and in a data transfer device in a certain network, when congestion occurs due to increased traffic and when the buffer usage rate is high, random or uniform. Instead of discarding packets dynamically and causing packet delays to suppress packet discards and delays, each application has a buffer monitoring control function that recognizes the application on the packet data and controls the buffer. It is an object of the present invention to provide a data transfer device and a buffer monitoring control method that can guarantee communication quality conditions by performing packet discard and packet delay control within an allowable range.

[0008]

According to the present invention, the above object is to provide a buffer, a buffer monitoring control circuit, and a parameter management table in a data transfer device provided in a network and having a function of transferring data. The buffer monitoring control circuit monitors the usage rate of the buffer to satisfy a preset quality condition,
This is achieved by controlling the buffer according to the application for each data transfer, based on the buffer control parameter preset for each application in the parameter management table.

Further, in the buffer monitoring control method of a data transfer device provided with a buffer provided in a network and having a function of transferring data, the use of the buffer in order to satisfy a preset quality condition. This is achieved by monitoring the rate, recognizing the application from the packet data input to the buffer, and controlling the optimum buffer for the application.

A basic feature of the present invention is that a buffer monitoring control function is provided for controlling a buffer in a data transfer device, an application on packet data input to the buffer is recognized, and each application is preset. The buffer control is performed on the basis of the buffer control parameter and the packet discard and packet delay conditions within the allowable range, whereby the communication quality of packet data can be guaranteed and the efficiency of use of the buffer can be improved.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a data transfer device and a buffer monitoring control method according to the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram showing a configuration example of an internet network having a data transfer device according to an embodiment of the present invention. In FIG. 1, 1 is an Internet network, 2a
2d are data transfer devices, 3a and 3b are internet terminals, 4a to 4d are VoIP terminals, and 5 and 6 are servers.

The Internet network 1 is constructed by connecting a plurality of data transfer devices 2a to 2d. And
Connected to the Internet network 1 are Internet terminals 3a and 3b for displaying mails and homepages, VoIP terminals 4a to 4d for communicating by voice, and servers 5 and 6 for managing mails and the like, and between each terminal-terminal. Or each terminal-
Communication is performed between the servers. In FIG. 1, data transfer devices 2a and 2c perform data transfer 101 between the Internet terminal 3a and the server 5, and also VoIP terminals 4a and 4c.
The figure shows a state in which the VoIP packet transfer 102 between and is performed.

FIG. 2 is a block diagram showing a configuration example of the data transfer device. In FIG. 2, 2 is a data transfer device, and 7
Is a setting terminal, 20 is a switch circuit, 211-21n are input circuits 1-n, 221-21m are output circuits 1-m, 23
Is a device control circuit.

The data transfer device 2 shown in FIG. 2 corresponds to the data transfer devices 2a to 2d shown in FIG. 1, and is referred to as the data transfer device 2 here. The data transfer device 2 includes a plurality of input circuits 211 to 21n, a plurality of output circuits 221 to 21m, a switch circuit 20, and a device control circuit 23, and is connected to the setting terminal 7. Since the data transfer device 2 enables input from n routes and output to m routes, the n input circuits 211 to 21
It has n and m output circuits 221 to 22m, and a switch circuit 20 for connecting and switching between an input circuit and an output circuit. In addition, the device control circuit 2
The control unit 3 controls the inside of the data transfer device 2 according to the setting information from the setting terminal 7, collects alarms and statistical information, and notifies the setting terminal 7 of the state of the data transfer device 2.

FIG. 3 is a block diagram showing a configuration example of the device control circuit 23 in FIG. 2, and FIG. 4 is a block diagram showing a configuration of the switch circuit 20 in FIG. 3 and 4, 231 is a CPU, 232 is a memory, 233 is a non-volatile memory, 234 is a control bus I / O, 235 is a setting terminal I / O, 201 is a distribution circuit, and 2021 to 202m.
Are application identification circuits 1 to m and 2031 to 203
m is the RED parameter setting circuits 1 to m and 2041 to 20
4m is a RED control buffer 1-m, 205 is a switch control circuit.

The device control circuit 23, as shown in FIG.
CPU 231, memory 232, non-volatile memory 233,
It is composed of a control bus I / O 234 for controlling the device and a setting terminal I / O 235 which is a connection interface with the setting terminal 7. The CPU 231 has the nonvolatile memory 2 at the initial stage.
The device control circuit 23 is set by the data from 33 and each circuit in the data transfer device 2 is set via the control bus I / O 234. The CPU 231 also sets the setting terminal I / O in order to enable communication with the setting terminal 7.
The setting of 235 is also performed. The CPU 231 stores the setting information from the setting terminal 7 in the memory 231, converts the setting information into internal control information, and controls each circuit via the control bus I / O 234. Further, the CPU 231 handles reading from the setting terminal 7 by collecting alarms and statistical information of each circuit and storing them in the memory.

The switch circuit 20, as shown in FIG.
Distribution circuit 201, m application identification circuits 2021 to 202m, m RED parameter setting circuits 2031 to 203m, and m RED control buffers 204
1 to 204 m and a switch control circuit 205.

In the above description, the distribution circuit 201 is the IP of the IP packet input from the input circuits 211 to 21n.
It has a function of distributing IP packets to the output circuits 221 to 22m based on the address. Distribution circuit 2
The IP packet distributed by 01 is transferred to the application identification circuit 2021, for example, when distributed by the output circuit 221. The application identification circuit 2021 recognizes the protocol type of the IP packet and notifies the RED parameter setting circuit 2031 by the protocol notification signal 2021c. The RED parameter setting circuit 2031 uses the protocol notification signal 2021c.
The registered RED parameter is searched from the protocol type notified by
The parameters are notified to the RED control buffer 2041 by the RED parameter notification signal 2031c.

The RED control buffer 2041 compares the RED parameter notified by the RED parameter notification signal 2031c with the current usage rate of the buffer,
IP transferred from the application identification circuit 2021
It is determined whether the packet is received or discarded. If the packet is receivable, the IP packet is written to the buffer. If the packet is discarded, the IP packet is treated as discarded without writing to the buffer.

The switch control circuit 205 communicates with the device control circuit 23 and performs various processes such as initial setting, reading of alarm information, and reading of statistical information in the switch circuit 20 based on control signals. This is performed via the switch control bus 205c for each of the above circuits.

FIG. 5 is a block diagram showing a circuit configuration example of the application identification circuit 2021 in FIG. 4, which will be described below. In the configuration example shown in FIG. 5, UDP, TCP and others are used as the protocol types, but the identification types of the protocol types may be variable, such as UDP, TCP, ICMP, IGMP and others.

The application identification circuit 2021 uses the I
P header bit counter circuit 20211, IP header protocol type identification circuit 20212, UDP header bit counter circuit 20213, UDP header destination port recognition circuit 20214, TCP header bit counter circuit 2
0215, TCP header destination port recognition circuit 2021
6. Other packet buffer circuit 20217 and output selection circuit 20218 are provided.

The application identification circuit 2021 sends the IP packet transferred from the distribution circuit 201 to the
It is received by the IP header bit counter circuit 20211 and the IP header protocol type identification circuit 20211.
Upon recognizing the beginning of the IP packet, the IP header bit counter circuit 20211 recognizes IPv4 or IPv6, generates timing information of the protocol field in the IP header, and notifies the IP header protocol identification circuit 20212 of the timing information.

IP header protocol identification circuit 20212
Extracts the information of the protocol field from the IP packet based on the timing information from the IP header bit counter circuit 20211, and identifies and distributes the protocol type such as UDP, TCP, or the like. After the identification of the protocol type, if the IP packet is UDP, the IP header protocol identification circuit 20212 sends the IP packet to the UDP header bit counter circuit 20213 and the UD.
P header destination port recognition circuit 20214
When the packet is TCP, TCP header bit counter circuit 20215 and TCP header destination port recognition circuit 2
0216. In addition, the IP header protocol identification circuit 20212, if the IP packet is other, Othe
r Transfer to the packet buffer circuit 20217.

UDP header bit counter circuit 2021
3 is an IP header protocol type identification circuit 20212
When the beginning of the IP packet transferred from is recognized,
The timing information from the IP header bit counter circuit 20211 is used to generate timing information of the destination port field in the UDP header, and the timing information is notified to the UDP header destination port recognition circuit 20214. The UDP header destination port recognition circuit 20214 uses the timing information from the UDP header bit counter circuit 20213 to determine the IP address.
Information on the destination port in UDP is extracted from the packet. The UDP header destination port recognition circuit 20214 transfers the IP packet to the output selection circuit 20218 after extracting the destination port information. Similarly, when the TCP header bit counter circuit 20215 recognizes the beginning of the IP packet transferred from the IP header protocol type identification circuit 20212, the timing information from the IP header bit counter circuit 20211 causes the TCP header bit counter circuit 20215 to change the destination port field of the TCP header. The timing information is generated and notified to the TCP header destination port recognition circuit 20216. The TCP header destination port recognition circuit 20216 is
Based on the timing information from the TCP header bit counter circuit 20215, the destination port information in TCP is extracted from the IP packet. The TCP header destination port recognition circuit 20216 transfers the IP packet to the output selection circuit 20218 after extracting the destination port information. Further, when the Other packet buffer circuit 20217 recognizes the head of the IP packet transferred from the IP header protocol type identification circuit 20212, the UDP and T
Information for notifying that the protocol type is other than CP is set, and the IP packet is transferred to the output selection circuit 20218.

The output selection circuit 20218 uses the output selection signal from the IP header protocol type identification circuit 20212 to determine the UDP header bit counter recognition circuit 2021.
4. The IP packet processed by the TCP header bit counter recognition circuit 20216 or the Other packet buffer circuit 20217 is transferred to the RED control buffer 2041, and the protocol type and the destination port information recognized from the IP packet are sent to the protocol / port notification signal. The RED parameter setting circuit 2031 is notified by 2021c. The IP header protocol identification circuit 202
12 is controlled by the switch control circuit 205 via the switch control bus 205c.

FIG. 6 shows a RED parameter setting circuit 2031.
FIG. 7 is a block diagram showing an example of the configuration of FIG. 2 and a flow chart for explaining the operation thereof. FIG.
12 is a diagram for explaining RED parameters stored in No. 12, and these will be described next. FIG.

The RED parameter setting circuit 2031 is, as shown in FIG.
311, a RED parameter storage memory 20312, and a storage memory access circuit 20313. RE
The D parameter search circuit 20311 receives the protocol / port notification signal 20 from the application identification circuit 2021.
21c receives the protocol type and the destination port information, and based on the received protocol type and the destination port information, the RED parameter storage memory 20312
Search for the RED parameter information registered in
When the RED parameter is registered, the parameter is read. RED parameter search circuit 20
After reading the parameters, 311 REDs the read RED parameters to the RED control buffer 2041.
This is notified as a parameter notification signal 2031c.

Next, the above-mentioned processing operation will be described with reference to the flow chart shown in FIG. 6 (b).

(1) RED parameter search circuit 2031
1 receives the protocol type and the destination port information transferred by the protocol / port notification signal 2021c from the application identification circuit 2021, and is registered in the RED parameter storage memory 20312 from the received protocol type and the destination port information. The RED parameter information that is present is searched (step F201).

(2) When the setting parameters differ depending on the application, RED according to each application
In order to select the parameter, it is determined whether the input data is mail data, and if it is mail data, the RED parameter corresponding to the protocol type of the mail data and the destination port information is selected (step F202, F203).

(3) If it is determined in step F202 that the input data is not mail data, it is determined whether the input data is VoIP data. If it is VoIP data, the VoIP data is determined. The RED parameter corresponding to the protocol type and the destination port information is selected (steps F204 and F205).

(4) If it is determined in step F204 that the input data is not VoIP data, it is determined whether the input data belongs to another registered application n, and the application n If it is, the RED parameter corresponding to the protocol type of the application n and the destination port information is selected (steps F206 and F207).

(5) If it is determined in step F204 that the input data is not for the application n, it is determined that the data is for an application not registered in the RED parameter management table, and the corresponding RED
A parameter is selected (step F208).

(6) Steps F203, F205, F2
07, R the RED parameter selected by F208
The ED control buffer 2041 is notified as a RED parameter notification signal 2031c, and the process ends (F step 209).

As shown in FIG. 7, management of the corresponding data stored in the RED parameter storage memory 20312 is performed by maximizing the RED parameter corresponding to each protocol type and destination port for each application and each priority in the application. By registering -th and min-th and associating them with each other, reading by data search from the RED parameter search circuit 20311 is supported. Further, the RED parameter storage memory 20312 is
The default setting is performed at the time of initial setting, and the RED parameter setting circuit 20 is provided so that the switch control circuit 205 can access the RED parameter storage memory 20312 via the switch control bus 205c.
A storage memory access circuit 20313 is provided in 31. As a result, for example, it is possible to realize a function of reading out the registered information managed as shown in FIG. 7, performing additional registration, and deleting registration.

The RED parameter search circuit 2031
There are several methods for reading the corresponding data stored in the RED parameter storage memory 20312 from 1 to 1. For example, the protocol information and the code information of the destination port are decoded and the corresponding decoded signal is used. A method of reading data, a method of generating address information from the protocol type and code information of the destination port and reading the corresponding data, or the like can be used.

FIG. 8 shows the RED control buffer 2 in FIG.
041 is a block diagram showing a configuration example of 041, FIG. 9 is a block diagram showing a configuration example of the RED parameter comparison setting circuit 20411 in FIG. 8, and FIG. 10 is a relationship between the buffer usage amount and the discard rate for determining the discard rate P. FIG. 3 is a diagram for explaining the above, and these will be described next.

As shown in FIG. 8, the RED buffer 2041 comprises a RED parameter comparison setting circuit 20411, a buffer monitoring circuit 20312, a discard control circuit 20413, and a buffer 20414.

RED parameter comparison setting circuit 20411
Is a buffer monitoring circuit 2 for monitoring the RED parameters max-th and min-th notified by the RED parameter notification signal 2031c from the RED parameter setting circuit 2031 and the current usage amount and usage rate of the buffer 20414.
0412 is compared with the buffer usage amount, and the discard control circuit 20413 determines whether to discard or transfer the IP packet based on the discard determination condition set from the switch control circuit 205 via the switch control bus 205c. Then, the application identification circuit 2021 notifies the discard control circuit 20413 of the instruction to discard or transfer the IP packet transferred.

The discard control circuit 20413 performs the primary buffering of the IP packet transferred from the application identification circuit 2021, and the discarding or transfer instruction from the RED parameter comparison setting circuit 20411 causes the buffering in the case of the discard instruction. In the case of a transfer instruction without transferring the stored IP packet to the buffer 20414, control is performed to transfer the buffered IP packet to the buffer 20414.

RED parameter comparison setting circuit 2 described above
0411 is configured as shown in FIG. 9 and performs packet discard control by the RED method.
Is larger than max-th, the IP packet is discarded with a probability of 100%, and when the buffer usage Q is smaller than min-th, the IP packet is transferred with a probability of 100%.
The discard control circuit 20413 is instructed. Also, R
When the buffer usage amount Q is min-th <Q <max-th, the ED parameter comparison / setting circuit 20411 controls the discarding of IP packets with the probability P shown in the following equation (1).

P = (Q- “min-th”) / (“max-th”-“min-th”) = ΔQ / ΔX (1) The RED parameter comparison / setting circuit 20411 has the aforementioned R
In order to realize the function for controlling the discarding of the IP packet by the ED method, as shown in FIG. 9, a decoder circuit A110, a max-th register A111, a min-th register A are provided.
112, buffer usage rate Q register A113, max-th <
A Q determination circuit A114, a Q <min-th determination circuit A115, a discard determination circuit A116, a discard instruction circuit A117, a passing packet number count register A118, and a discard packet number count register A119.

The Decoder circuit A110 receives the RED parameter notification signal 20 from the RED parameter setting circuit 2031.
While receiving the RED parameter notified by 31c, the RED parameters max-th and min-th are recognized, and the recognized max-th is stored in the max-th register A111. Control to write to the min-th register A112 is performed. Also, the buffer usage rate Q register A11
3 receives the buffer usage amount information notified from the buffer monitoring circuit 20412, and sets the buffer usage amount to the max-th <Q determination circuit A114, Q <min-th determination circuit A115 and the discard determination circuit A116. Bus A113
The buffer usage rate Q is notified via a.

The max-th <Q judgment circuit A114 judges whether or not the buffer usage amount Q is a value larger than max-th, and if it is larger, the signal Y instructs the discard instruction circuit A117 to discard the IP packet. Notification of. Also, max-th <
When the buffer usage amount Q is smaller than max-th, the Q determination circuit A 114 uses the signal N to notify the max-th condition violation notification signal A.
116a is notified to the discard determination circuit A116.

The Q <min-th judging circuit A115 judges whether or not the buffer usage amount Q is smaller than the min-th value. If the buffer usage amount Q is smaller than the min-th value, the signal Y indicates the IP packet to the passing packet number count register A118. Notify you of passing. In addition, Q <min-th determination circuit A115 determines the buffer usage Q
Is greater than min-th, the signal N is used to notify the discard determination circuit A116 of the min-th condition violation notification signal A116b.

The discard determination circuit A116 outputs a signal notified by the max-th <Q determination circuit A114 by the max-th condition violation notification signal A116a and a signal issued by the Q <min-th determination circuit A115 by the min-th condition violation notification signal A116b. And the information of the buffer usage amount Q notified by the buffer usage amount setting bus A113a from the buffer usage rate Q register A113 performs the calculation or determination of the discard rate P shown in the above equation (1). .

In order to determine the discard rate P, the contents of the equation (1) are determined as the relationship between the buffer usage amount and the discard rate as shown in FIG. It is also possible to realize a function of quickly obtaining the discard rate P according to the buffer usage amount by hardware processing. Further, it is possible to make it possible to variably set the division number of ΔX of the buffer usage amount Q from the switch control circuit 205 via the switch control bus signal, thereby flexibly setting the discard determination condition according to the usage status. It can be variably set. The example shown in FIG. 10 is an example in which the number of divisions is set to 8, and the number of divisions of ΔX is set to 8 and Δ1 to Δ8. Therefore, the number of divisions of ΔX is n
When set to, Δ1 to Δn.

When the discard determination circuit A116 determines to discard the IP packet by the above-described processing, it notifies the discard instruction circuit A117 of the discard instruction by the discard instruction notification signal A116c. When it is determined that the packet is transferred or passed instead of being discarded, the discard determination circuit A116 notifies the passing packet number count register A118 of the passing of the IP packet by the passage instruction notification signal A116d.

The discard instruction circuit A117 has a discard instruction signal from the max-th <Q determination circuit A114 and the discard determination circuit A1.
The discard instruction signal from the discard instruction notification signal A116c from 16 notifies the discard control circuit 20413 of the discard instruction of the IP packet, and also notifies the discard packet number count register A119 of the discard of the IP packet. To do.

Passing packet number count register A118
Is a passage instruction signal from the Q <min-th determination circuit A115,
And a passage instruction notification signal A from the discard determination circuit A116.
116d is received and the counter of the number of passing IP packets is increased. The counter can count not only the number of passing IP packets but also the number of bytes thereof. The discard packet number count register A119 receives the discard instruction signal from the discard instruction circuit A117, and increments the counter of the discard IP packet number. Counter is discarded IP
Not only the number of packets but also the number of bytes can be counted. The passing packet number count register A118 and the discarded packet number count register A11 described above.
The control unit 9 controls reading, writing, clearing, resetting, and the like of each counter from the switch control circuit 205 via the switch control bus.

FIG. 11 shows the discard decision circuit A11 in FIG.
6 is a block diagram showing an example of the configuration of No. 6 shown in FIG.
In this example, the number of divisions of ΔX of the buffer usage amount Q shown in FIG.

As shown in FIG. 11, the discard decision circuit A116 has a min-th <Q <max-th decision circuit A1161, ΔQ = Q.
-"Min-th" arithmetic circuit A1162, division number = n Δ
X = “max-th” − “min-th” arithmetic circuit A1163, ΔX
1 arithmetic circuit to ΔXn arithmetic circuit A11641 to A1164
n, comparison circuit A1165, discard condition storage register A11
66, random number generation circuit A1167, discard determination calculation circuit A1
168 is provided.

Min-th <Q <max-th determination circuit A1161
Is the max-th <Q information notified from the max-th <Q determination circuit A114 by the max-th condition violation notification signal A116a and
While receiving max-th information, Q <min-th determination circuit A1
15 receives the min-th <Q information and the min-th information notified by the min-th condition violation notification signal A116b. min-
The th <Q <max-th determination circuit A1161 is a circuit for determining that min-th <Q <max-th from the above information. This determination circuit A1161 is, for example, a min-th
When <Q, there is a case of max-th <Q in some cases. Therefore, each combination of such conditions is confirmed and min-th <Q <max-th is determined. If the conditions match from the judgment result, min-th <
The Q <max-th determination circuit A1161 has ΔQ = Q− “min-t
The min-th information is notified to the h "arithmetic circuit A1162, and the max-th information is notified to the ΔX =" max-th "-" min-th "arithmetic circuit A1163 with the division number = n.

ΔQ = Q- "min-th" arithmetic circuit A1162
Is calculated from the min-th information notified from the min-th <Q <max-th determination circuit A1161 and the buffer usage rate Q notified from the buffer usage rate Q register A113 via the buffer usage rate setting bus A113a. The value is notified to the comparison circuit A1165.

Number of divisions = ΔX = n = “max-th” − “min-t”
The h ″ arithmetic circuit A1163 obtains ΔX based on the information of max-th and min-th notified from the min-th <Q <max-th determination circuit A1161. Also, the switch control circuit 205 to the switch control bus 205c. The value of ΔXα is obtained by using the following expression (2) with the value of the number of divisions n set via
641 to ΔXn arithmetic circuit A1164n, min-th
And information of ΔXα.

ΔXα = ΔX / n (2) ΔX1 arithmetic circuit to ΔXn arithmetic circuit A11641 to A11
64n is the number of divisions = n ΔX = “max-th” − “min-th”
The respective ranges of ΔX1 to ΔXn are obtained from the information of min-th and ΔXα notified from the arithmetic circuit A1163.

For each range of ΔX1 to ΔXn, for example, the calculation of the following equations (3) and (4) is performed to obtain ΔX
It can be obtained by obtaining (n-1) and ΔXn and further calculating them.

ΔX (n−1) = “min-th” + {ΔXα × (n−1)} (3) ΔXn = “min-th” + (ΔXα × n) (4) Then, When obtaining ΔX1, Δx (1-1) = “min-th” + {ΔXα × (1-
1)}, that is, ΔX0 = “min-th” Further, assuming that n in the equation (4) is 1, ΔX1 = “min-th” + (ΔXα × 1), that is, ΔX1 = “min-th” + ΔXα As a result, the range of ΔX1 can be calculated as ΔX0 to ΔX1, that is, “min-th” to “min-th” + ΔXα.

When obtaining ΔXn, n in equation (3)
Where n is ΔX (n−1) = “min-th” + {ΔXα × (n−
1)}, that is, ΔX (n−1) = “min-th” + (n−1) ΔXα, where ΔXn = “min-th” + (ΔXα × n), where n in Expression (4) is n. That is, ΔXn = “min-th” + nΔXα As a result, the range of ΔXn is ΔX (n−1) to ΔXn, that is, “min-th” + (n−1) ΔXα to “min-th” + n
It can be calculated as ΔXα.

By performing the same calculation as described above, ΔX
2 to ΔX (n-1) can be obtained. Also, ΔX1
Arithmetic Circuit to ΔXn Arithmetic Circuit A11641 to A1164n
Are the discard rates P1 to P for ΔX1 to ΔXn, respectively.
n is calculated. In determining the discard rates P1 to Pn,
Each arithmetic circuit obtains the discard rate Pβ in ΔXβ by performing the arithmetic operation using the equation (5) shown below. In addition, ΔXβ indicates any one of ΔX1 to ΔXn. Here, since it is not uniquely shown as any of ΔX1 to ΔXn, ΔXβ
Notated as

Pβ = β × 100 / n (5) Taking the case of ΔX1 as an example, P1 = 1 × 100 / n
= 100 / n (%). In the case of ΔXn, Pn = n × 100 / n = 100 (%) is obtained.

By performing the same calculation as described above, ΔX
2 to ΔX (n-1) can be obtained.

The configuration according to the embodiment of the present invention described above is
The discard determination circuit A116 is divided by ΔX = “max-t
Although the circuit configuration is divided into the h "-" min-th "operation circuit A1163 and the [Delta] X1 operation circuits to [Delta] Xn operation circuits A11641 to A1164n, one circuit configuration is provided by reducing the circuit scale, speeding up the processing time, and the like. Further, the above-described arithmetic processing can be configured not only by software but also by hardware.

Further, in the configuration of the above-described embodiment of the present invention, the discard determination circuit A116 is controlled so as to perform the above-described calculation. However, the discard determination circuit A116 is controlled in advance in each range of ΔX1 to ΔXn corresponding to each condition. The value of can be registered and the value can be read and set.

ΔX1 arithmetic circuit to ΔXn arithmetic circuit A116
41 to A1164n compares the ranges ΔX1 to ΔXn and the discard rates P1 to Pn obtained by the above-described arithmetic processing with the comparison circuit A.
Notify 1165.

The comparison circuit A1165 has a function of ΔQ = Q- "min-."
th "receives the ΔQ notified from the arithmetic circuit A1162,
This ΔQ and ΔX1 arithmetic circuit to ΔXn arithmetic circuit A116
Based on ΔX1 to ΔXn and the discard rates P1 to Pn notified from 41 to A1164n, the range of ΔX to ΔX1 to ΔXn is compared. Then, the comparison circuit A1
165 is ΔXβ from ΔXβ which is compared and the condition is matched.
And Pβ to the discard condition storage register A1166.

The comparison circuit A1165 has a division number n.
Is notified from the switch control circuit 205 via the switch control bus 205c, the comparison is performed based on the results notified from the ΔX1 arithmetic circuit to the ΔXn arithmetic circuits A11641 to A1164n, and the arithmetic circuit out of the range. It has a function to prevent erroneous processing when comparing with information from.

Upon receiving ΔXβ and Pβ notified from the comparison circuit A1165, the discard condition storage register A1166 instructs the discard determination arithmetic circuit A1168 to discard rate Pβ.
And the instruction for the discard determination calculation is given. In addition,
Instead of providing the discard condition storage register A1166, the comparison circuit may directly notify the discard determination calculation circuit A1168 of ΔXβ and Pβ, and may also issue the discard determination calculation instruction.

The discard determination calculation circuit A1168 receives the discard rate Pβ from the discard condition storage register A1166 and performs the discard determination calculation according to the instruction of the discard determination calculation. The discard determination operation, for example, receives a random number from the random number generation circuit A1167, divides the received value by the number of divisions n notified from the switch control circuit 205 via the switch control bus 205c, calculates the remainder, and determines the discard rate. This can be realized by making a discard decision based on the above. In the case of discard determination, the discard determination calculation circuit A1168 notifies the discard control circuit 20413 of the discard instruction by the discard instruction notification signal A116c, and in the case of transfer determination, the pass instruction notification signal A116d transmits the passing packet number count register. The A118 is notified of the passage instruction.

FIG. 12 shows the discard decision circuit A11 shown in FIG.
11 is a block diagram showing another configuration example of No. 6, and this example is an example in which the number of divisions of ΔX of the buffer usage amount Q shown in FIG. 10 is eight. That is, the example shown in FIG. 12 is an example when the number of divisions of ΔX in the discard determination circuit A116 shown in FIG. 11 is 8, and the difference between FIGS. 11 and 12 is only the difference in the number of divisions of ΔX. Other functions are common. By setting the number of divisions to 8, in the example shown in FIG.
X1 arithmetic circuit to ΔX8 arithmetic circuit A11641 to A116
48 will be provided.

Further, each value can be obtained from the equations (2) to (5) shown in the explanation of FIG. First, assuming that n = 8 in equation (2), ΔXα = ΔX
/ 8. Taking the case of ΔX8 with n = 8 as an example, ΔX (8-1) = “min-th” + {ΔXα × (8−
1)}, that is, ΔX7 = “min-th” + 7ΔXα = “min-th” + (7ΔX
/ 8) Further, according to the equation (4), ΔX8 = “min-th” + (ΔXα × 8), that is, ΔX8 = “min-th” +8 ΔXα = “min-th” + ΔX As a result, the range of ΔX8 is ΔX7 to ΔX8, that is, “min-th” + (7ΔX / 8) to “min-th” + ΔX can be obtained.

Next, if equation (5) = 8, then P
β = β × 100/8 = 12.5β, and in the case of ΔX1, P1 = 1 × 12.5 = 12.5 (%) is obtained.
Further, in the case of ΔX8, P8 = 8 × 12.5 = 100
(%) Can be obtained.

In the above description, for example, min-th, max-th,
An example of calculation and an example of comparison and determination when the value of Q is set is as follows.

When min-th = 1 Mbytes, max-th = 5 Mbytes, Q = 2.3 Mbytes, and the number of divisions = 8, ΔX
1 arithmetic circuit to ΔX8 arithmetic circuit A11641 to A1164
8 is ΔXα = ΔX / 8 = (5 MB-1 MB) / 8 =
0.5M bytes, the range of ΔX1 is 1M bytes to less than 1.5M bytes, the range of ΔX2 is 1.5M bytes to less than 2M bytes, and the range of ΔX3 is 2M bytes to less than 2.5M bytes. Each range can be determined.

Further, the discarding rate is ΔX1, P1 = 12.5 (%), ΔX2 is P2 = 25.0 (%), and ΔX3 is P3 = 37.5 (%). And ΔQ = 3.3 Mbytes-1 Mbytes = 2.3 Mbytes.

The comparison circuit A1165 outputs Δ from the above result.
Q = 2.3 Mbytes is within the range ΔXβ is determined, and therefore ΔX1 to ΔX8 are compared. Since ΔQ is within the range of ΔX3 according to the comparison result, the discard rate P3 = 37.
5 (%) can be obtained, and the discard condition storage register (A1166) is notified.

FIG. 13 is a block diagram showing an example of the configuration of the discard determination arithmetic circuit A1168, and FIG. 14 is a diagram showing the configuration of a correspondence table for making the discard / transfer determination. Note that FIG.
FIG. 14 shows an example in which the number of divisions is eight.

The discard judgment operation circuit A1168 includes a discard condition receiving circuit A11681 and a random number reading circuit A1168.
2, a ran / 8 arithmetic circuit A11683, a remainder storage register A11684, a discard condition determination circuit A11685, and a discard / transfer determination register A11686.

In the above description, the discard condition receiving circuit A116
81 receives the discard conditions ΔXβ and Pβ from the discard condition storage register A1168, and transfers the received ΔXβ and Pβ to the discard condition determination circuit A11685. The random number reading circuit A11682 reads the random number generated from the random number generating circuit A1167 and sets the read value as ra.
The data is transferred to the n / 8 arithmetic circuit A11683. Here, ran = aaa is set as an example of the read value.

The ran / 8 arithmetic circuit A11683 has a value read from the random number read circuit A11682, ran = a.
The aaa is divided by 8 and the remainder information is notified to the remainder storage register A11684. Discard condition determination circuit A116
85 recognizes .DELTA.X.beta. And P.beta. From the discard condition receiving circuit A11681 and the discard condition from the remainder storage register A11684, and determines discard or transfer. Discarding and transferring based on ΔXβ and Pβ and the residual information is performed by presetting a correspondence table as shown in FIG. 14 or by calculating. When using the correspondence table as shown in FIG. 14, ΔX
Discard and transfer can be determined by the value that is the remainder from β and Pβ.

When the correspondence table according to FIG. 14 is used, for example, when the discard rate is 37.5% from the discard conditions ΔX3 and P3, it is determined from FIG. 14 that the remainder is 0 to 2, and the remainder = In the case of 3 to 7, the transfer is determined. Therefore, the discard condition determination circuit A11685 is aa
When the remainder is 1 in the calculation result of aa / 8, the discard / transfer determination register A11686 is notified of the discard instruction, and when the remainder is 6, the discard / transfer determination register A116 is discarded.
The transfer instruction is sent to 86.

The discard / transfer determination register A11686 is
In the case of the discard determination, the discard instruction notification signal A116c notifies the discard instruction circuit A117 of the discard instruction, and in the case of the transfer determination, the passage instruction notification signal A116d issues the passage instruction to the passing packet number count register A118. Notice.

The discard determination circuit A116 is configured to make the discard / transfer determination from the remainder resulting from the division of the random number, but it is also possible to make the discard / transfer determination based on conditions other than the random number and the remainder.

FIG. 15 shows the discard control circuit 204 shown in FIG.
13 is a block diagram showing a configuration example of 13. The discard control circuit 20413 includes a discard instruction signal receiving circuit A131, a transfer buffer writing circuit A132, and a transfer instruction / discard circuit A.
133, a transfer buffer A134, and a transfer buffer reading circuit A135.

In the above description, the discard instruction signal receiving circuit A1
31 receives the discard instruction signal notified from the RED parameter comparison setting circuit 20411, and controls the transfer instruction / discard circuit A133. Transfer buffer writing circuit A132
Controls the writing of the IP packet transferred from the application identification circuit 2021 into the transfer buffer A134, and also transfers a write end signal to the transfer buffer A134, a packet start address, and a packet byte number. / Notify the discard circuit A133.

The transfer instruction / discard circuit A133, when the discard instruction signal is not sent from the discard instruction signal receiving circuit A131 within a certain period of time, or when the transfer instruction is received, the transfer instruction / discard circuit A135 instructs the transfer buffer reading circuit A135. The transfer processing of the IP packet is performed by notifying the information such as the packet start address and the packet byte number notified from the transfer buffer writing circuit A132. In addition, the transfer instruction / discard circuit A133 has a discard instruction signal receiving circuit A13.
When the discard instruction signal comes from 1, the transfer buffer reading circuit A135 is instructed to the transfer buffer writing circuit A1.
By not notifying the information such as the packet start address and the number of packet bytes notified from 32, the IP packet is discarded.

The transfer buffer A134 is a primary buffer for absorbing the processing time of each of the RED parameter setting circuit 2031 and the RED buffer comparison setting circuit 20411 in the RED control buffer 2041. As an example of the buffer configuration, when DPRAM is used and the ring buffer configuration is used, the configuration is such that a capacity of several packets can be used. The transfer buffer reading circuit A135
The IP packet is transferred from the transfer buffer A134 to the buffer 20414 according to the information such as the packet start address and the packet byte number notified from the transfer instruction / discard circuit A133. In the case of a discard instruction, the transfer buffer reading circuit A135 does not receive a notification from the transfer instruction / discard circuit A133, and therefore the transfer buffer A134 to the buffer 204
The IP packet is not transferred to 14.

FIG. 16 shows the buffer monitoring circuit 2 in FIG.
It is a block diagram which shows the structural example of 0412. The illustrated buffer monitoring circuit 20412 includes a buffer usage rate calculation circuit A1.
21, a write counter register A122, a read counter register A123, and a control circuit A124.

In the above description, the buffer usage rate calculation circuit A
The 121 calculates the usage rate and the usage amount of the buffer based on the values from the write counter register A 122 and the read counter register A 123, and RED the result.
Notify the parameter comparison circuit 20411. The write counter register A122 reads out information such as a write address in the buffer 20414 from the control circuit A124 and stores it. In addition, the read counter register A123 is the buffer circuit 204 from the control circuit A124.
Information such as the read address in 14 is read and stored.

FIG. 17 shows the buffer 20414 shown in FIG.
3 is a block diagram showing a configuration example of FIG. Illustrated buffer 204
14 is a FIFO control monitoring circuit A 141, a FIFO write control circuit A 142, a FIFO buffer A 143, F
It is composed of an IFO read control circuit A144.

In the above description, the FIFO control monitoring circuit A1
41 is a FIFO write control circuit A 142 and FIF
Each state of the O read control circuit A144 is monitored and access control with the control circuit A124 is performed. FI
The FO write control circuit A142 performs control for writing the IP packet transferred from the discard control circuit into the FIFO buffer A143. FIFO buffer A143
Is a buffer memory having a FIFO structure and capable of reading data in the written order. The FIFO read control circuit A 144 performs control for reading the IP packet written in the FIFO and transferring it to the output circuit 221.

FIG. 18 is a diagram for explaining an example of the operation outline of the IP packet transfer / discard determination in the transfer of the IP packet to the output circuit, which will be described below. FIG.
The example shown in (1) is an example showing the operation when the IP packets P1a to P1e are IP packets of protocol type: UDP, destination port: 2222, and application: Voice. Further, the IP packets P1a to P1e are transferred from the distribution circuit 201 to the application identification circuit 202.
1, RED control buffer 2041 and output circuit 221)
The position in each process up to is shown.

In FIG. 18, the IP packet P1a distributed to the output circuit 221 by the distribution circuit 201.
Is transferred to the application identification circuit 2021 and I
At the position of the P packet P1b, each information of the protocol type and the destination port is extracted as PH1a and transferred to the position of the IP packet P1c. After that, the IP packet is transferred to the transfer buffer A1 of the RED control buffer 2041.
It is transferred to the position of the IP packet P1d in 34.
The extracted information PH1a is transferred to the position of PH1b in the RED parameter setting circuit 2031, and UDP,
The information 2222 is searched from the registration information shown in FIG. 7, and the RED parameter information TH1 of max-th = Xn, min-th = X5 is read.

The information of TH1 is the RED parameter comparison circuit 20 in the RED parameter control buffer 2041.
411 is notified. RED parameter comparison circuit 204
11 compares the buffer usage amount Q from the buffer monitoring circuit 20412 with the TH1 information, and as a result, when it is determined to discard, a discard instruction signal is sent to the discard transfer control circuit A133.
In the case of transfer determination, the discard instruction signal is not notified to the discard transfer control circuit A133.

When the discard transfer control circuit A133 receives the notification of the discard instruction signal, the discard transfer control circuit A133 sends data to the transfer buffers A134 to F.
The transfer processing of the IP packet to the IFO buffer A143 is stopped. Therefore, in the case of discard processing, the IP packet is
The transfer ends at the position of the IP packet P1d. When the notification of the discard instruction signal is not received within a certain time, or when the notification of the transfer instruction signal is received, the discard transfer control circuit A133 causes the discard transfer control circuit A133 to transfer the IP packet from the transfer buffer A134 to the FIFO buffer A143. Of the IP packet P1e to the output circuit 221.

FIG. 19 shows an application identification circuit 202.
2 is a diagram for explaining an outline of the operation of application identification in FIG. 1, which will be described below. The example illustrated in FIG. 19 illustrates an operation example when the IP packets P11 to P16 are transferred in time series. Therefore, the IP packets P11 to P16 include the protocol type, destination port,
Applications are different.

In FIG. 19, IP packets P11 to P
16 indicates that the respective states are as follows. That is, since the protocol type of the IP packet P11 is UDP, the UDP header destination port identification circuit 20214 determines that the protocol type is UD.
The information PH11 of P and destination port: 3000 is extracted and transferred to the RED parameter setting circuit. Since the protocol type of the IP packet P12 is TCP,
By the TCP header destination port identification circuit 20216, information PH of protocol type: TCP, destination port: 101
Twelve extractions have been made. The IP packet P13 is I
By the P header protocol type identification circuit 20212,
The protocol type is recognized as UDP and is being transferred to the UDP header destination port identification circuit 20214.

The IP packet P14 is being identified by the IP header protocol type identification circuit 20212 as 9l and the protocol type: Other. The IP packet P15 and the IP packet P16 are distributed by the distribution circuit 20.
It is being transferred to the application identification circuit 2021 by distribution from 1 to the output circuit 221.

20 to 25 show the RED control buffer 20.
FIG. 4 is a diagram illustrating a schematic example of an operation in 41. Figure 20
25 shows an operation example in which the IP packets P101 to P109 are transferred / discarded in time series. Therefore, the IP packets P11 to P16 are
Destination port, application, etc. are different.

The state shown in FIG. 20 is in the transfer buffer A13.
For the IP packet P103 transferred to
The D parameter comparison circuit 20411 determines that the buffer usage Q
20 and the RED parameters Xn and X5 of the IP packet P103 notified from the RED parameter setting circuit, and the discard determination calculation circuit A1168 determines that X5> Q and the transfer is determined to be the transfer buffer A13.
4 is an instruction to transfer the IP packet P103 to the packet No. At this time, the FIFO buffer A143
The preceding IP packets P101 and P102 are stored therein.

The state shown in FIG. 21 is the transfer buffer A13.
For the IP packet P104 transferred to
The D parameter comparison circuit 20411 determines that the buffer usage Q
21 is compared with the RED parameters Xx and X1 of the IP packet P104 notified from the RED parameter setting circuit, it is determined that Q is within the range of ΔX1, and the discard rate condition of ΔX1 is sent to the discard determination calculation circuit A1168. Is informed. Then, the discard determination calculation circuit A1168 determines that the discard rate is 12.5% and discards it, and instructs the transfer buffer A134 to discard the IP packet P104. At this time, the preceding IP packet P101 stored in the state of FIG. 20 is output in the FIFO buffer A143, and the IP packet P102.
And the IP packet P103 transferred from the state of FIG. 20 are stored.

The state shown in FIG. 22 is in the transfer buffer A13.
For the IP packet P105 transferred to
The D parameter comparison circuit 20411 determines that the buffer usage Q
22 is compared with the RED parameters Xp and X5 of the IP packet P105 notified from the RED parameter setting circuit, and the discard determination operation circuit A1168 determines that X5> Q and transfers, and thus the transfer buffer A13.
In this state, the transfer instruction of the IP packet P105 is given to the packet No. At this time, the preceding IP packet P102 stored in the state of FIG. 21 is output in the FIFO buffer A143, and only the IP packet P103 is stored.

The state shown in FIG. 23 is in the transfer buffer A13.
For the IP packet P106 transferred to
The D parameter comparison circuit 20411 determines that the buffer usage Q
23 and the RED parameter Xk, 0 of the IP packet P106 notified from the RED parameter setting circuit, it is determined that Q is within the range of ΔX2, and the discarding rate condition of ΔX2 is sent to the discarding determination calculating circuit A1168. Is informed. Then, the discard determination arithmetic circuit A1168 determines that the transfer is to be performed based on the determination of the transfer rate of 75% (discard rate of 25%), and instructs the transfer buffer A134 to transfer the IP packet P106. At this time, the FIFO buffer A
In 143, the preceding IP packet P103 stored in the state of FIG. 22 and the I transferred from the state of FIG.
A P packet P105 is stored.

The state shown in FIG. 24 is in the transfer buffer A13.
4 for the IP packet P107 transferred to
The D parameter comparison circuit 20411 determines that the buffer usage Q
24 is compared with the RED parameter Xk, 0 of the IP packet P107 notified from the RED parameter setting circuit, it is determined that Q is within the range of ΔX2, and the discarding rate condition of ΔX2 is sent to the discarding determination arithmetic circuit A1168. Is informed. Then, the discard determination calculation circuit A1168 determines that the discard rate is 25%, and determines that the discard rate is 25%.
4 is instructed to discard the IP packet P107. At this time, the preceding IP packet P1 stored in the state shown in FIG. 23 is stored in the FIFO buffer A143.
03 is output, and the IP packet P105 and FIG.
The IP packet P106 transferred from the above state is stored.

The state shown in FIG. 25 is in the transfer buffer A13.
For the IP packet P108 transferred to
The D parameter comparison circuit 20411 determines that the buffer usage Q
25 and the RED parameters Xn and X5 of the IP packet P108 notified from the RED parameter setting circuit, and the discard determination operation circuit A1168 determines that X5> Q and determines that the transfer is performed, and thus the transfer buffer A134.
To the IP packet P108. At this time, the FIFO buffer A 143 stores the data in FIG.
The preceding IP packet P10 stored in state 4
5 and the IP packet P106 are still stored.

[0108]

As described above, according to the present invention, the application on the packet data can be recognized and the buffer control can be performed. Therefore, the buffer monitoring control function is provided so that each application is within the allowable range. It is possible to guarantee the communication quality condition by discarding the packet and controlling the packet delay and improve the use efficiency of the buffer.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration example of an Internet network having a data transfer device according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration example of a data transfer device.

3 is a block diagram showing a configuration example of a device control circuit in FIG.

FIG. 4 is a block diagram showing a configuration of a switch circuit in FIG.

5 is a block diagram showing a circuit configuration example of an application identification circuit in FIG.

FIG. 6 is a block diagram showing a configuration example of a RED parameter setting circuit and a flowchart for explaining its operation.

FIG. 7 is a diagram illustrating RED parameters stored in a RED parameter storage memory.

8 is a block diagram showing a configuration example of a RED control buffer in FIG.

9 is a block diagram showing a configuration example of a RED parameter comparison setting circuit in FIG.

FIG. 10 is a diagram illustrating a relationship between a buffer usage amount and a discard rate for determining a discard rate P.

11 is a block diagram showing a configuration example of a discard determination circuit in FIG.

12 is a block diagram showing another configuration example of the discard determination circuit in FIG.

FIG. 13 is a block diagram illustrating a configuration example of a discard determination calculation circuit.

FIG. 14 is a diagram showing a configuration of a correspondence table for determining discard and transfer.

15 is a block diagram showing a configuration example of a discard control circuit in FIG.

16 is a block diagram showing a configuration example of a buffer monitoring circuit in FIG.

17 is a block diagram showing a configuration example of a buffer in FIG.

FIG. 18 shows the I in the transfer of the IP packet to the output circuit.
It is a figure explaining the operation outline example of P packet transfer / drop judgment.

FIG. 19 is a diagram illustrating an outline of an operation of application identification in an application identification circuit.

FIG. 20 is a diagram (No. 1) explaining an outline example of the operation in the RED control buffer.

FIG. 21 is a diagram (part 2) explaining an outline example of the operation in the RED control buffer.

FIG. 22 is a diagram (No. 3) for explaining an example of an outline of the operation in the RED control buffer.

FIG. 23 is a diagram (No. 4) for explaining an outline example of the operation of the RED control buffer.

FIG. 24 is a diagram (No. 5) explaining an outline example of the operation in the RED control buffer.

FIG. 25 is a diagram (No. 6) explaining an outline example of the operation of the RED control buffer.

[Explanation of symbols]

1 Internet network 2, 2a-2d data transfer device 3a, 3b Internet terminal 4a-4d VoIP terminal 5, 6 server 7 Setting terminal 20 switch circuits 211-21n Input circuits 1-n 221 to 21m Output circuit 1 to m 23 Device control circuit 231 CPU 232 memory 233 Non-volatile memory 234 Control bus I / O 235 Setting terminal I / O 201 Distribution circuit 2021 to 202m Application identification circuits 1 to m 2031 to 203m RED parameter setting circuits 1 to m 2041 to 204m RED control buffers 1 to m 205 switch control circuit

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 5K030 GA11 HA08 HC01 HD05 JA07                       KX12 KX19 LC01 LC18                 5K034 AA03 DD03 EE11 HH50 HH64

Claims (5)

[Claims] 1. A data transfer device provided in a network and having a function of transferring data, comprising a buffer, a buffer monitoring circuit, and a parameter storage memory, wherein the buffer monitoring circuit sets quality conditions set in advance. In order to satisfy the above, the usage rate of the buffer is monitored, and the buffer is controlled according to the application for each data transfer based on the buffer control parameter for each application preset in the parameter storage memory. Characteristic data transfer device. 2. The data transfer device according to claim 1, wherein the buffer monitoring circuit recognizes an application from the packet data input to the buffer. 3. The data transfer apparatus according to claim 1, wherein the buffer monitoring circuit controls the buffer so as to perform packet discard and packet delay within a range allowed by an application. 4. A buffer monitoring control method for a data transfer device, which is provided in a network and has a buffer having a function of transferring data, wherein a buffer utilization rate is monitored to meet a preset quality condition. A buffer monitoring control method, characterized in that the application is recognized from the packet data input to the buffer, and the optimum buffer control for the application is performed. 5. The buffer monitoring control method according to claim 4, wherein the buffer is controlled so that the packet is discarded and the packet is delayed within a range allowed by the application.