JP2003046484A5 - - Google Patents

Description

[0014]
The receiving circuit 24 receives a low noise amplifier (LNA) 26 to which a received signal output from the transmission / reception switching circuit 23 is input, and an output signal of the low noise amplifier 26 from a frequency synthesizer 15 for frequency hopping described later via a buffer amplifier 27. Mixer 28 for mixing with a local oscillation signal to be input and converting it into an intermediate frequency signal, and a band pass filter 29 for removing an image signal generated when the intermediate frequency signal output from this mixer 28 is input and mixed An intermediate frequency (IF) amplifier 30 for amplifying the filter output of the band pass filter 29; a limiter amplifier 32 connected to the intermediate frequency amplifier 30 via the low pass filter 31 for providing constant amplitude; And a detection circuit 33 to which the amplified output of the amplifier 32 is input. The receiver data output from the detection circuit 33 is input to the baseband processing device 50, and the RSSI (Receiver Signal Strength Indicator) signal representing the reception signal level output from the intermediate frequency amplifier 30 and the limiter amplifier 32 is also baseband. The signal is input to the signal processing device 50.

[0015]
On the other hand, the transmission circuit 25 has a power amplifier 35 to which the transmission signal output from the frequency synthesizer 15 is input, and the transmission signal output from the power amplifier 35 is supplied to the transmission side input terminal of the transmission / reception switching circuit 23. Ru.
Furthermore, the frequency synthesizer 15 receives a phase locked loop (PLL) circuit 41 to which a setting signal for setting frequency hopping output from the baseband signal processing device 50 is input, and an output signal of the phase locked loop circuit 41. Low-pass filter 42, a filter output of the low-pass filter 42, and transmission data from the baseband signal processing device 50 are input through the amplifier 43 and the low-pass filter 44 to form a frequency-controlled transmission signal VCO 45 and a doubling circuit 46 that doubles the transmission signal output from voltage control oscillator 45, and the transmission signal output from voltage control oscillator 45 is fed back to phase locked loop circuit 41. Together with the output of the doubler circuit 46 It supplies a signal to the power amplifier 35 of the transmission circuit 25, and supplies a local oscillation signal to the mixer 28 of the receiving circuit 24 via the buffer amplifier 27.

[0016]
Further, the baseband signal processing device 50 has a reception data processing unit 51 that processes reception data input from the reception circuit 24 and an ISM (Industrial Scientific Medical) band having a frequency of 2.4 GHz with respect to the frequency synthesizer 15. The frequency hopping control unit 52 controls frequency hopping in a predetermined pattern, the transmission data processing unit 53 transmits and processes input user data, and the intermediate frequency amplifier 30 and the limiter amplifier 32 of the reception circuit 24 Communication state detection unit 54 that detects the communication state based on the RSSI signal input by adding the RSSI signal representing the received signal level, and outputs the detection result to the reception data processing unit 51; And a communication control unit 55 for establishing a distance wireless communication network.

[0019]
Thereafter, both switches SW1 and SW2 are switched to the normally open contact NO side, then 3-bit data stored in each shift register SR0 to SR2 is output to form a total of 7-bit transmission data, which is then amplified. The signal is supplied to the frequency synthesizer 15 through the low pass filter 44 and the low pass filter 44, and transmission from the antenna 21 through the transmission circuit 25 and the transmission / reception switching circuit 23 is repeated to transmit transmission data every 4 bits.

[0021]
Here, as shown in FIG. 4, hard decision decoding circuit 51A has 6 stages of buffer registers BR0 to BR5 to which reception data is input, and gate circuits G and 3 to which reception data constituting a divider are input. It has a division circuit DV configured of stage shift registers SRA0 to SRA2, adders AD1 to AD3, NOT circuits NT1 and NT2, and an AND circuit AN.

[0022]
In the hard decision decoding circuit 51A, when the 7-bit reception sequence is sequentially inputted to the buffer registers BR0 to BR5 and the divider DV simultaneously in a state where the gate circuit G is open, the 7-bit reception sequence is input. When finished, a syndrome is obtained in the divider DV. At this time, the input gate circuit G of the divider DV is turned off, the data is read from the buffer registers BR0 to BR5, and at the same time the contents of the divider DV are shifted to the right, and the NOT circuits NT1 and NT2 and the AND circuit When “001” is detected by AN, “1” is supplied to the adder AD3 so that the operation of mod 2 is performed by the adder AD3 to correct an error bit and correct the error bit as received data. The print data processor 61 outputs the print data.

[0026]
Next, the operation of the first embodiment will be described.
Now, when the portable information terminal 2 or the notebook personal computer 3 as the slave wireless communication device does not exist around the printer 1 as the master wireless communication device, the communication state in the baseband signal processing device 50 of the printer 1 The detection unit 54 periodically performs authentication work of the slave wireless communication devices present in the periphery, and when the slave wireless communication devices do not exist, the short distance wireless communication network is not constructed, but as shown in FIG. When the portable information terminal 2 and the notebook personal computer 3 exist within the communication range of the printer 1, the portable information terminal 2 and the notebook personal computer 3 recognizing the existence are started when the authentication work is started. Of the slave radio communication devices to which the address of the predetermined bit is assigned, and the address is assigned. Assigning an address range wireless communication network of a predetermined bit to the slave wireless communication devices for performing communication.

[0027]
Thereafter, after authentication with the encryption key is performed, the slave wireless communication device participates in the short distance wireless network, and data can be transmitted / received to / from the master wireless communication device.
In this state, for example, when print data to be printed by the printer 1 is generated in the portable information terminal 2, the print data is transmitted from the portable information terminal 2 to the printer 1. At this time, in the error correction coding circuit 53a of the transmission data processing unit 53 in the baseband signal processing device 50, the transmission data is divided into 4 bits each, which are used as information bits, to which 3 redundant bits are added. (7, 4) The encoding process is performed to create a total of 7 bits of transmission data, which is supplied to the voltage control starter 45 of the frequency synthesizer 15 so that the transmission data is switched by the transmission circuit 25 with the frequency hopping pattern. The signal is transmitted from the antenna 21 through the circuit 23.

[0036]
On the other hand, when the received data is subjected to Viterbi decoding by soft decision decoding circuit 51 B, branch metric operation unit 55 obtains a metric (branch metric) of the reception code pattern of each reception code in the reception sequence. The likelihood of the path is determined in combination with the time metric (path metric) to select the surviving path, and the path metric for the next time is stored and held in the path metric storage unit 58. Then, the path selection signal data is read from the path selection signal storage unit 59 by the traceback operation unit 60, and the path selection signal extracted from the path selection signal storage unit 59 performs traceback processing to update the shift register in the next cycle. Then, the Viterbi decoding is performed, and the decoded received data is supplied to the print data processing device 61 to perform the printing process.

[0040]
After that, the switches SW1 and SW2 are both switched to the normally open contact NO side, and then 5 bits of data stored in each of the shift registers SR0 to SR4 are output to form transmission data of a total of 15 bits. The signal is supplied to the frequency synthesizer 15 through the low pass filter 44 and the low pass filter 44, and transmission from the antenna 21 is repeated through the transmission circuit 25 and the transmission / reception switching circuit 23 to transmit transmission data 10 bits at a time.

[0041]
Similarly, the hard decision decoding circuit 51A and the soft decision decoding circuit 51B of the reception data processing unit 51 are also configured to be able to decode the (15, 10) shortened Hamming code.
Even when this (15, 10) shortened Hamming code is used, the parity check matrix H can be expressed by the following equation (3), and the generator matrix G can be expressed by the following equation (4).

[0048]
Also, as shown in FIG. 13, the baseband signal processing device 50 of the printer 1 as the master wireless communication device receives the (15, 10) shortened Hamming code that the received data processing unit 51 receives from the receiving circuit 24. A soft decision decoding unit 51B that performs soft decision decoding of data, a bit error rate measurement unit 51E that measures a bit error rate BER by calculating, for example, a syndrome in hard decision of received data, and the bit error rate measurement unit 51E. A transmission power control unit 51F instructs the slave wireless communication device of transmission power based on the measured bit error rate BER.

[0054]
At this time, in the notebook personal computer 3 serving as a slave wireless communication device, the transmission data is divided into 10 bits and input to the encoding circuit 53a shown in FIG. 8 so that the switches SW1 and SW2 are normally closed contacts As the NC side, 10 bits as the first information bit are output as they are, then switches SW1 and SW2 are switched to the normally open contact NO side, and then each bit stored in each shift register SR0 to SR4 is sequentially redundant By outputting as a bit, transmission data consisting of a total of 15 bits (15, 10) shortened Hamming code is formed, this transmission data is supplied to the frequency synthesizer 15, and the transmission circuit 25, the switching circuit 23 and the antenna filter 22 are The signal is transmitted from the antenna 21 to the printer 1 serving as the master side wireless communication device.

[0057]
The transmission data processing unit 53 supplies transmission power reduction request data to the frequency synthesizer 41 when reception of reception data of one frame is completed, and the transmission circuit 25 and the transmission / reception switching circuit 23 and the antenna filter 22 The transmission power reduction request data is wirelessly transmitted from the antenna 21 to the notebook personal computer 3.

[0059]
Thereafter, when the bit error rate BER measured by the bit error rate measurement unit 51E in the reception data processing unit 51 of the printer 1 becomes equal to or higher than the set value THb at time t1, it is determined that the communication quality has deteriorated, and from step S2 The process proceeds to step S5, and since the bit error rate BER was less than the set value THb last time, the process proceeds to step S7. Since the state change flag F is reset to "0", the process proceeds to step S10. By supplying the increase request data to the transmission processing unit 53 and transmitting it to the notebook personal computer 3, the transmission power of the notebook personal computer 3 is increased by one step.

[0062]
Further, when print data is transmitted to the printer 1 by the notebook personal computer 3 and the bit error rate BER greatly exceeds the set value THb as shown by a dotted line in FIG. 15, step S10 in the process of FIG. The transmission power of the notebook personal computer 3 is increased by outputting the transmission power increase request data to the transmission data processing unit 53, and the bit error rate BER of the transmission power increase process falls below the set value THb. Until the bit error rate BER falls below the set value, the same processing as at the time t2 described above is performed to continue the state where the bit error rate BER is slightly lower than the set value THb. Maintain the transmission power of 3 at the minimum necessary state.

Images