JP2003046352A - Variable gain amplifier - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a variable gain amplifier that can dramatically widen a variable gain range. SOLUTION: The variable gain amplifier is provided with: an input differential pair circuit 61 that has a plurality of differential pair FETs (N1 to N4) each comprising a couple of FETs and acts like a V/I converter that converts an input voltage (Vin) into a current; an output differential pair circuit 62 that has a plurality of differential pair FETs (N5 to N8) each comprising a couple of FETs and acts like an I/V converter for converting the converted current into an output voltage (Vo); a control bias generating circuit K1 that control currents flowing through the differential pair FETs by using bias voltages Bias 1, Bias 2; selector switches SW1 to SW4 that select whether a current may be supplied to the input and output differential pair circuits via current source FETs N9 to N12; and a differential pair size switching control circuit K2 that selects the switches to control the size of the input differential pairs and the size of the output differential pairs.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable gain amplifier having a wide variable gain range.

[0002]

2. Description of the Related Art A variable gain amplifier is shown in FIG.
, The conductance of converting voltage to current is given by Gi
It is composed of a V / I converter 1 having an n value and an I / V converter 2 having a conductance Gout that converts a current into a voltage.

The input voltage Vin of the variable gain amplifier is V / I
It is converted into a current of I = Gin · Vin by the converter 1,
The current I is Vout = I / Gou by the I / V converter 2.
It is converted into the output voltage Vout of t.

Therefore, the gain Vout of the variable gain amplifier
/ Vin is as follows: Gain = Vout / Vin = Gin / Gout (1)

If Gin and Gout are variably controlled, the gain can be varied and the function of the variable gain amplifier can be realized.

As a conventional variable gain amplifier, for example, a differential pair FET (field effect transistor) for converting an input voltage into a current and a differential pair FET for converting the current into an output voltage.
An amplifier that has a variable gain by controlling only the current flowing through the differential pair FET is introduced in the following documents.

Literature Po-Chin Huang, Li-Yu Chio
u, Chong-Kuang Wang, "A3.
3 _- V CMOS WIDEBAND EXPONEN
TIAL CONTROL VARIABLE _- GAI
N _- AMPLIFIER "circuits and
Systems, 1998. ISCAS '98. Pr
ocedings of the 1998 IEEE
E International Symposium
on Volume; 1, 1998, Page
_(S): 285 - 288vol. 1.

Variable gain amplifier introduced in this document
A circuit diagram of the above is shown in FIG. In FIG. 3, the constant current source circuit 1
The power supply voltage is applied to one end of each of FETP5 and FETP6 of 0.
Power bus 12 connected to terminal 11_PConnected to each other
The ends are common connection points 50a and 50b, and a FETN forming a differential pair.
Ground line 12 via 31, N32 and FET N35 _N
It is connected to the.

Input voltages Vin having different polarities are applied to the respective gates of the FETs N31 and N32 forming the differential pair.

The common connection points 50a and 50b and the ground wire 1
The FETs N33, N34 and the FET N36, which are diode-connected and form a differential pair, are connected in series between 2 _N , and output voltages (Vo) having different polarities are output to the common connection points 50a, 50b. To be done.

In the constant current source circuit 10, the common connection point 5
Amplifier A based on the deviation between the reference voltage Vcm and the midpoint voltage of FETs P3 and P4 connected in series between 0a and 50b.
1 controls the FETs P5 and P6 so that the currents of the FETs P5 and P6 are constant.

One end of the current source S is connected to the power source bus 12 _P, and the other end of the current source S is connected to the sources of the pair of FETs P1 and P2. The drains of the FETs P1 and P2 are connected to the ground line 12 _N via diode-connected FETs N13 and N14.

A reference voltage Vr is applied to the gate of the FET P1.
ef is supplied with the control voltage Vct1 to the gate of the FET P2, and a current according to the difference between the voltages Vref and Vct1 flows through the FETs P1 and P2. This current is FET
Converted to bias voltage by N13 and N14,
The bias voltage controls the FETs N35, N36, and thereby the differential pair FETs N31, N32,
The current flowing through N33 and N34 is variable.

FIG. 4 is a schematic diagram for explaining the operating principle of the circuit of FIG. That is, the differential pair FET
N31 and N32 form a V / I converter D1, and differential pair FETs N33 and N34 form an I / V converter D2.
The constant current source circuit 10 constitutes constant current sources S3 and S4, and the FETs N35 and N36 make variable current sources S1 and S4.
2 are configured.

The V / I converter D1 has a differential input,
The I / V converter D2 has a differential output. Current source S
A variable gain amplifier is realized by controlling S1 and S2, varying the current flowing through the differential pair FET, and controlling the conductances Gmi and Gmo of the differential pair FET.

The general formula of the differential pair FET conductance Gm is represented by the following formula (2).

Gm = {2μCox (W / L) (Is / 2)} ^1/2 = {μCox (W / L) Is} ^1/2 (2) where μ is the carrier mobility of the FET and Cox is Gate oxide film capacitance per unit area of FET, W / L is FET channel width / FET channel length (hereinafter referred to as size), Is is a current flowing through the differential pair FET (two FETs).
Is the sum of currents).

Here, the differential pair FET sizes (W / L) i and (W / L) of the V / I converter D1 and the I / V converter D2 are set.
o are M and N respectively, and V / I converters D1 and I /
The currents Ii and Io flowing through the differential pair FET of the V converter D2 are M (Ibias + Ict1) and N (Ibias), respectively.
-Ictl), the gain of this circuit is given by the following equation (3).
Can be expressed as

Gain = Gmi / Gmo = {μCox (W / L) i · Ii / μCox (W / L) o · Io} ^1/2 = (M / N) · {(Ibias + Ictl) / (Ibias-Ictl) } ^1/2 (3) Ibias is a bias current per unit size of the differential pair FET, and Ictl is a control current per unit size of the differential pair FET for controlling the gain. Ic
By adding tl from Ibias to the V / I converter D1 (input differential pair) and the I / V converter D2 (output differential pair) in opposite directions, the gain can be changed from the equation (3). .

At this time, the gain offset is the size ratio (M / N) of the V / I converter D1 (input differential pair) and the I / V converter D2 (output differential pair). The variable gain range of the variable gain amplifier is determined by how much the control current Ictl can be added to or subtracted from the bias current Ibias.

[0021]

In the above-mentioned variable gain amplifier, the control current Ictl can be changed only ± 70% in actual circuit with respect to the bias current Ibias, and in fact, this variable gain amplifier can be changed. Gain range is 15d
It becomes very narrow, about B.

The present invention has been made in view of the above points, and an object thereof is to provide a variable gain amplifier capable of remarkably widening the variable gain range.

[0023]

A variable gain amplifier according to the present invention for solving the above problems has a plurality of differential pair field effect transistors each including a pair of field effect transistors and converts an input voltage into a current. A voltage / current converter, a plurality of differential field effect transistors each including a pair of field effect transistors, a current / voltage converter for converting the converted current into an output voltage, and each of the differential field effect transistors. Current control means for controlling the current flowing through the effect transistor,
In the voltage / current converter, the size of the differential pair field effect transistor determined by the ratio of the channel width and the channel length of the differential pair field effect transistor, and in the current / voltage converter, the differential pair field effect transistor A differential pair size control means for controlling the size of the differential pair field effect transistor determined by the ratio of the channel width and the channel length is provided.

Further, the differential pair size control means causes the current flowing through the plurality of differential pair field effect transistors to flow.
It is characterized by having a control circuit for switching each non-flow.

Further, the current control means has a control element inserted in a current flow path of each of the differential pair field effect transistors, and a control bias generation circuit for supplying a control voltage to each of the control elements. It is characterized by doing.

Further, the control circuit is characterized by controlling ON / OFF of the control element.

[0027]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. According to the equation (3) indicating the gain, not only the control current Ictl but also the V / I converter D1
It is understood that a variable gain amplifier with a wide variable range can be realized by variably controlling the size ratio (M / N) of the (input differential pair) and the I / V converter D2 (output differential pair) as well. This has been achieved by configuring as in the following example embodiments.

In FIG. 1, the same parts as those in FIG. 3 are designated by the same reference numerals. FETP5, F of the constant current source circuit 10
One end of the ETP 6 is connected to a power supply bus 12 _P connected to the power supply voltage applying terminal 11, and the other end is connected to a common connection point 10.
0a, 100b. This constant current source circuit 1
0 controls the currents of the FETs P5 and P6 to be constant, as in FIG.

Reference numeral 61 is an input differential pair circuit which operates as a V / I converter, and includes a plurality of differential pair FETs each consisting of a pair of FETs, two in this embodiment (differential pair FETs N1, N.
2 and a differential pair FET N3, N4) are arranged in parallel, and each FET N1,
The drain of N3 is connected to the common connection point 100a and each FET is
The drains of N2 and N4 are connected to the common connection point 100b, respectively.

Reference numeral 62 denotes an output differential pair circuit which operates as an I / V converter, and includes a plurality of differential pair FETs each consisting of a pair of FETs, two in the present embodiment (diode-connected differential pair FETs N5, N5). N6 and diode-connected differential pair FET N
7 and N8) are arranged in parallel, and the drains of the FETs N5 and N7 are connected to the common connection point 100a, and the drains of the FETs N6 and N8 are connected to the common connection point 100b.

A common source connection point of the differential pair FETs N1 and N2, a common source connection point of the differential pair FETs N3 and N4,
Source common connection point of differential pair FETs N5 and N6, differential pair F
The common source connection point of ETN7 and N8 is the current source FETN
The drains and sources of 9, N10, N11 and N12 are connected to the ground line 12 _N , respectively.

The FETs N1 and N3 and the FETs N2 and N4
Input voltages Vin having different polarities are applied to the respective gates. Output voltages (Vo) having different polarities are output to the common connection points 100a and 100b.

One end of the current source S is connected to the power source bus 12 _P, and the other end of the current source S is connected to the sources of the pair of FETs P1 and P2. The drains of the FETs P1 and P2 are connected to the ground line 12 _N via diode-connected FETs N13 and N14.

A reference voltage Vr is applied to the gate of the FET P1.
ef is a differential current control voltage Vc at the gate of the FET P2.
tl is supplied to the FETs P1 and P2, and the voltage V
Currents I1 and I2 corresponding to the difference between ref and Vct1 flow. The currents I1 and I2 are converted into bias voltages Bias1 and Bias2 by the FETs N13 and N14, respectively.

The current source S, FETs P1, P2 and F
Control bias generation circuit K1 by ETN13 and N14
(Current control means).

The current source FETs N9, N10, N11,
Selection switches SW1, SW2, S are provided on each gate of N12.
The terminals a of W3 and SW4 are connected to each other. One contact b of the selection switches SW1 and SW2 is the FET N
13 is connected to the bias generation point 200b (Bias2), and one contact point b of the selection switches SW3 and SW4 is the bias generation point 200a (Bias1) of the FET N14.
It is connected to the. Selection switches SW1, SW2, SW
The other contact c of SW3 and SW4 is connected to the ground line 12 _N.

K2 is the selection switch SW based on the control signal input to the differential pair size control terminal Sctl.
By switching 1, SW2, SW3, SW4 to the b or c contact, the current source FETs N9, N10, N11,
It is a differential pair size switching control circuit that selects whether to apply the signal level of Bias1 or Bias2 or the ground level (GND level) to each gate terminal of N12.

In the circuit configured as described above, the size ratio of the current source FETs N9 to N12 is equal to the ratio of the differential pair connected to each of them. When the sizes of the FETs N1 to N12 are SN1 to SN12, respectively, the following relationship is established.

SN9: SN10: SN11: SN12 = (SN1 = SN2) :( SN3 = SN4) :( SN5 = SN6) :( SN7 = SN8) (4) Among the current source FETs N9 to N12, the ground level is FE selected (selection switch was switched to contact c side)
No current flows through the differential pair FETs (FETs N1 to N8) connected to T, so that they do not function as a differential pair.

Among the current source FETs N9 to N12, the differential pair FETs (FETs N1 to N8) connected to the FET whose level of the bias voltage Bias1 or Bias2 is selected (the selection switch is switched to the contact b side) are , A current corresponding to the level is passed, and it functions as a differential pair.

Thus, the size of the input differential pair and the size of the output differential pair can be controlled by selecting whether or not to supply a current to the input / output differential pair composed of the FETs N1 to N8.

Of the current source FETs N9 to N12, the bias voltage Bia is selected by the selection switches SW1 to SW4.
Currents corresponding to the bias voltages Bias1 and Bias2 flow through the FETs for which s1 and Bias2 are selected.

Input differential pair FET (input differential pair circuit 61)
The ratio of the current Ii = I3 + I4 flowing to the output differential current Io = I5 + I6 flowing to the output differential pair FET (output differential pair circuit 62) is Ii: Io = M (Ibias + Ictl): N (I
(bias-Ictl).

Here, Ibias is a bias current per unit size when the reference voltage Vref and the differential current control voltage Vct1 are equal (when the Bias1 voltage and the Bias2 voltage are equal). Ictl is a control current per differential pair unit size, which is generated by the difference voltage between the reference voltage Vref and the differential current control voltage Vctl.

The control current Ictl acts as a current in the opposite direction between the input differential pair current and the output differential pair current.

The control current Ictl is a parameter that can be variably controlled by the differential current control terminal Vctl.

Here, if the size of the input differential pair arbitrarily selected is defined as M and the size of the output differential pair is defined as N, the gain equation of the variable gain amplifier of FIG. 1 completely matches the above equation (3). To do. The size ratio M / N in the equation (3) is a parameter that can be variably controlled by the differential pair size control terminal Sctl.

Therefore, by controlling the input differential pair size M and the output differential pair size N, the respective conductances Gmi and Gmo are varied, and the function of the variable gain amplifier is realized. The variable gain range is wider than that of the conventional example because the size of the differential pair can be controlled.

Although the number of the differential pair FETs is two in the present embodiment, the number is not limited to this and the number can be arbitrarily determined to another number. Also, the size of each differential pair can be arbitrarily determined.

The current control means of the present invention is not limited to the circuit configuration shown in FIG. 1 and may be any other circuit as long as it controls the current flowing through each differential pair FET.

Further, the differential pair size control means of the present invention is not limited to the circuit configuration of FIG. 1, but may be configured by other circuits as long as it controls the size of each differential pair FET.

[0052]

As described above, according to the present invention, not only the control current but also the sizes of the input differential pair FET as the V / I converter and the output differential pair FET as the I / V converter are set. Since it is configured to variably control, the variable gain range of the variable gain amplifier can be remarkably widened.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram illustrating the principle of a variable gain amplifier.

FIG. 3 is a circuit diagram showing an example of a conventional variable gain amplifier.

FIG. 4 is a circuit configuration diagram schematically showing the circuit of FIG.

[Explanation of symbols]

10 ... Constant current source circuit, 11 ... Power supply voltage applying terminal, 12 _P
… Power bus, 12 _N … Ground wire, 61… Input differential pair circuit,
62 ... Output differential pair circuit, K1 ... Control bias generation circuit,
K2 ... Differential pair size switching control circuit, N1 to N8 ... F
ET, N9 to N12 ... Current source FET, SW1 to SW4 ...
Select switch.

Claims (5)

[Claims] 1. A voltage / current converter having a plurality of differential pair field effect transistors each composed of a pair of field effect transistors and converting an input voltage into a current, and a differential pair field effect transistor consisting of a pair of field effect transistors. A current / voltage converter having a plurality of transistors for converting the converted current into an output voltage; current control means for controlling a current flowing through each of the differential pair field effect transistors; and the voltage / current converter. Of the differential pair field effect transistor size determined by the ratio of the channel width and the channel length of the differential pair field effect transistor in, and the channel width and the channel length of the differential pair field effect transistor in the current / voltage converter. A variable gain amplifier including differential pair size control means for controlling the differential pair field effect transistor size determined by the ratio. . 2. The differential pair size control means includes a control circuit for switching between conduction and non-conduction of a current flowing through the plurality of differential pair field effect transistors. 1. The variable gain amplifier according to 1. 3. The current control means includes a control element inserted in a current flow path of each of the differential pair field effect transistors, and a control bias generation circuit for supplying a control voltage to each of the control elements. The variable gain amplifier according to claim 1, wherein the variable gain amplifier comprises: 4. The current control means includes a control element inserted in a current flow path of each of the differential pair field effect transistors, and a control bias generation circuit for supplying a control voltage to each of the control elements. The variable gain amplifier according to claim 2, wherein the variable gain amplifier comprises: 5. The control circuit turns on the control element,
The variable gain amplifier according to claim 4, wherein the variable gain amplifier is controlled to be turned off.