JP2003046026A - Semiconductor device and manufacturing method therefor - Google Patents

Semiconductor device and manufacturing method therefor

Info

Publication number
JP2003046026A
JP2003046026A JP2001226172A JP2001226172A JP2003046026A JP 2003046026 A JP2003046026 A JP 2003046026A JP 2001226172 A JP2001226172 A JP 2001226172A JP 2001226172 A JP2001226172 A JP 2001226172A JP 2003046026 A JP2003046026 A JP 2003046026A
Authority
JP
Japan
Prior art keywords
semiconductor device
manufacturing
semiconductor
pad
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2001226172A
Other languages
Japanese (ja)
Other versions
JP4122143B2 (en
Inventor
Toshio Kato
俊夫 加藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiyo Yuden Co Ltd
Original Assignee
Taiyo Yuden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiyo Yuden Co Ltd filed Critical Taiyo Yuden Co Ltd
Priority to JP2001226172A priority Critical patent/JP4122143B2/en
Publication of JP2003046026A publication Critical patent/JP2003046026A/en
Application granted granted Critical
Publication of JP4122143B2 publication Critical patent/JP4122143B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0237Disposition of the redistribution layers
    • H01L2224/02375Top view
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0237Disposition of the redistribution layers
    • H01L2224/02381Side view
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05541Structure
    • H01L2224/05548Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16135Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19041Component type being a capacitor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19043Component type being a resistor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19102Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • H01L2924/19104Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device on the semiconductor or solid-state device, i.e. passive-on-chip

Landscapes

  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide the manufacturing method of a semiconductor device which can follow up the demands for high-density mounting. SOLUTION: Passive parts, such as a capacitor part 24 and resistance parts 25 and a different semiconductor device SC3, are loaded on a semiconductor device SC2 by using the connection pads 22a of wiring patterns 22 formed in the semiconductor device SC2. By making the other circuit element connected to the semiconductor element of the semiconductor device SC2 and a compound circuit which is three-dimensionally constituted can easily be constituted, the semiconductor device which can follow the demands for high density mounting can be supplied.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、再配置配線を施し
た半導体装置とその製造方法、及び、半導体基板上に回
路素子を搭載した半導体装置とその製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having rearranged wiring, a method of manufacturing the same, a semiconductor device having a circuit element mounted on a semiconductor substrate, and a method of manufacturing the same.

【0002】[0002]

【従来の技術】再配置配線を施した半導体装置の製造方
法の一例を以下に説明する。
2. Description of the Related Art An example of a method of manufacturing a semiconductor device having relocated wiring will be described below.

【0003】まず、IC製造工程内で形成されたオリジ
ナルパッドを有するシリコンウエハーの表面全面に感光
性ポリイミド樹脂層を形成し、露光現像処理によってオ
リジナルパッド部分を露出させた後、ポリイミド樹脂層
を加熱硬化させる。次に薄膜形成装置内でパッド表面に
形成されている酸化膜を除去した後、ウエハーの表面全
面にCr層とCu層から成る2層膜を形成する。次に2
層膜の表面全面にメッキレジスト膜を形成し、露光現像
処理によって再配置配線部分を露出させ、メッキレジス
トの硬化処理後、露出部分にCuメッキを行う。次にメ
ッキレジスト膜を剥離し、2層膜上のCuメッキ部分以
外のCu層とCr層をエッチングで除去する。次にウエ
ハー表面全面に感光性ポリイミド樹脂層を形成し、露光
現像処理によって再配置配線の一部を露出させた後、ポ
リイミド樹脂層を加熱硬化させる。次に再配置配線の露
出部分にバンプを形成する。
First, a photosensitive polyimide resin layer is formed on the entire surface of a silicon wafer having an original pad formed in the IC manufacturing process, the original pad portion is exposed by exposure and development, and then the polyimide resin layer is heated. Let it harden. Next, after removing the oxide film formed on the pad surface in the thin film forming apparatus, a two-layer film including a Cr layer and a Cu layer is formed on the entire surface of the wafer. Then 2
A plating resist film is formed on the entire surface of the layer film, the rearranged wiring portion is exposed by exposure and development processing, and after the plating resist is cured, Cu plating is performed on the exposed portion. Next, the plating resist film is peeled off, and the Cu layer and the Cr layer other than the Cu plated portion on the two-layer film are removed by etching. Next, a photosensitive polyimide resin layer is formed on the entire surface of the wafer, a part of the rearranged wiring is exposed by an exposure and development process, and then the polyimide resin layer is cured by heating. Next, a bump is formed on the exposed portion of the relocation wiring.

【0004】[0004]

【発明が解決しようとする課題】前述の従来方法では、
再配置配線を施すために高価な薄膜形成装置や露光現像
装置が必要となると共に処理ステップが多いために間接
費用も嵩んでしまうことから、製造コストを低減するこ
とが難しく、安価な半導体装置を得ることが極めて難し
い。
In the above-mentioned conventional method,
An expensive thin film forming apparatus and an exposure / development apparatus are required to perform the rearrangement wiring, and indirect costs are increased due to the large number of processing steps. Therefore, it is difficult to reduce the manufacturing cost, and an inexpensive semiconductor device is provided. Extremely difficult to obtain.

【0005】また、各種電子機器はICだけで構成され
るわけではなく、ICの周辺には数多くの受動部品が配
置接続されることで電気回路が形成され、所定の機能が
実現している。半導体装置の小型化要求に対してはリア
ルサイズCSPや複数のICを一つのパッケージに組み
込む手法が提案されているが、より高度な実装を実現す
るには、IC部分を小型化するだけでなく回路を構成し
ている受動部品をも含めた対策が必要となる。
Further, various electronic devices are not composed only of ICs, and many passive components are arranged and connected in the periphery of the ICs to form electric circuits and realize predetermined functions. In response to the demand for miniaturization of semiconductor devices, a method of incorporating a real size CSP or a plurality of ICs into one package has been proposed. However, in order to realize more advanced mounting, not only the IC portion must be miniaturized It is necessary to take measures including the passive components that make up the circuit.

【0006】本発明は前記事情に鑑みて創作されたもの
で、第1の目的とするところは、安価な半導体装置とそ
の製造方法を提供することにある。また、第2の目的と
するところは、高密度実装の要求に追従できる半導体装
置とその製造方法を提供することにある。
The present invention has been made in view of the above circumstances. A first object of the present invention is to provide an inexpensive semiconductor device and a manufacturing method thereof. A second object is to provide a semiconductor device and a manufacturing method thereof that can follow the demand for high-density packaging.

【0007】[0007]

【課題を解決するための手段】前記第1の目的を達成す
るため、本発明に係る半導体装置は、請求項1に記載の
ように、半導体素子を備えた半導体基板に、オリジナル
パッドと接続し、且つ、その一部が接続用パッドとして
露出する再配置配線を設けた半導体装置において、前記
再配置配線が厚膜形成法によって形成された厚膜から成
る、ことをその主たる特徴とする。また、本発明に係る
半導体装置の製造方法は、請求項2に記載のように、半
導体素子を備えた半導体基板に、オリジナルパッドと接
続し、且つ、その一部が接続用パッドとして露出する再
配置配線を設ける半導体装置の製造方法において、前記
再配置配線を厚膜形成法によって形成する、ことをその
主たる特徴とする。
In order to achieve the first object, a semiconductor device according to the present invention has a semiconductor substrate having a semiconductor element connected to an original pad as described in claim 1. Further, in the semiconductor device provided with the rearrangement wiring, a part of which is exposed as a connection pad, the main feature is that the rearrangement wiring is made of a thick film formed by a thick film forming method. Further, according to the method of manufacturing a semiconductor device of the present invention, as described in claim 2, a semiconductor substrate provided with a semiconductor element is connected to an original pad, and a part thereof is exposed as a connection pad. The main feature of the method of manufacturing a semiconductor device in which layout wiring is provided is that the redistribution wiring is formed by a thick film forming method.

【0008】この半導体装置及び半導体装置の製造方法
によれば、再配置配線の形成に厚膜形成法を用いること
により、再配置配線を施すために高価な薄膜形成装置等
が不要となると共に処理ステップを低減できるので、製
造コストを低減して安価な半導体装置を提供することが
できる。
According to this semiconductor device and the method for manufacturing the semiconductor device, by using the thick film forming method for forming the rearrangement wiring, an expensive thin film forming apparatus or the like for performing the rearrangement wiring becomes unnecessary and the processing is performed. Since the number of steps can be reduced, the manufacturing cost can be reduced and an inexpensive semiconductor device can be provided.

【0009】また、前記第2の目的を達成するため、本
発明に係る半導体装置は、請求項6に記載のように、半
導体素子を備えた半導体基板に、オリジナルパッドと接
続し、且つ、一部が接続用パッドとして露出する複数の
再配置配線を設けた半導体装置において、前記接続用パ
ッドが露出する面には、2以上の接続用パッドと接続す
る少なくとも1つの回路素子が設けられている、ことを
その主たる特徴とする。また、本発明に係る半導体装置
の製造方法は、請求項9に記載のように、半導体素子を
備えた半導体基板に、オリジナルパッドと接続し、且
つ、一部が接続用パッドとして露出する複数の再配置配
線を設ける半導体装置の製造方法において、前記接続用
パッドが露出する面に、2以上の接続用パッドと接続す
るように少なくとも1つの回路素子を設ける、ことをそ
の主たる特徴とするこの半導体装置及び半導体装置の製
造方法によれば、再配置配線の接続用パッドを利用して
他の回路素子を搭載することにより、半導体素子に他の
回路素子を接続して三次元に構成された複合回路を簡単
に構成することができ、これにより高密度実装の要求に
追従できる半導体装置を提供できる。
In order to achieve the second object, according to a sixth aspect of the present invention, a semiconductor device according to the present invention is connected to an original pad on a semiconductor substrate having a semiconductor element, and In a semiconductor device provided with a plurality of rearrangement wirings whose parts are exposed as connection pads, at least one circuit element connected to two or more connection pads is provided on the surface where the connection pads are exposed. , Is its main feature. Further, in the method for manufacturing a semiconductor device according to the present invention, as described in claim 9, a plurality of semiconductor substrates provided with semiconductor elements are connected to an original pad and a part of which is exposed as a connection pad. In a method of manufacturing a semiconductor device having relocation wiring, at least one circuit element is provided on a surface where the connection pad is exposed so as to be connected to two or more connection pads. According to the method of manufacturing the device and the semiconductor device, another circuit element is mounted by using the connection pad of the rearrangement wiring to connect the other circuit element to the semiconductor element to form a three-dimensional composite structure. It is possible to provide a semiconductor device that can easily configure the circuit and can follow the demand for high-density packaging.

【0010】本発明の前記目的とそれ以外の目的と、構
成特徴と、作用効果は、以下の説明と添付図面によって
明らかとなる。
The above and other objects, constitutional features, and operational effects of the present invention will become apparent from the following description and the accompanying drawings.

【0011】[0011]

【発明の実施の形態】最初に、第一の目的を達成するた
めの半導体装置の製造方法を図1〜図6を用いて説明す
る。
First, a method of manufacturing a semiconductor device for achieving the first object will be described with reference to FIGS.

【0012】図1は周知の方法によって作成されたオリ
ジナルウエハーで、図中の符号11はシリコンウエハ
ー、12はSiN等から成るパッシベーション膜、13
はAlから成るオリジナルパッドである。このオリジナ
ルウエハーには、IC等の半導体素子(図示省略)が所
定配列で形成され、各半導体素子に対応して複数のオリ
ジナルパッド13が設けられている。
FIG. 1 is an original wafer prepared by a known method. In the figure, reference numeral 11 is a silicon wafer, 12 is a passivation film made of SiN or the like, and 13 is a silicon wafer.
Is an original pad made of Al. On this original wafer, semiconductor elements (not shown) such as ICs are formed in a predetermined array, and a plurality of original pads 13 are provided corresponding to each semiconductor element.

【0013】製造に際しては、まず、図2に示すよう
に、パッシベーション膜12の表面に、オリジナルパッ
ド13が露出するようにスクリーン印刷法によって絶縁
ペーストを印刷し、印刷した絶縁ペーストを硬化させて
層間絶縁膜14を形成する。層間絶縁膜14用の絶縁ペ
ーストには、熱処理による硬化を可能とした熱硬化性の
ポリイミド系樹脂やBCB(ベンゾシクロブデン)樹脂
やエポキシ系樹脂等から成る樹脂ペーストが使用できる
他、紫外光等の光照射による硬化を可能としたポリイミ
ド系樹脂やBCB樹脂やエポキシ系樹脂等から成る光硬
化性樹脂ペーストが使用できる。また、層間絶縁膜14
は、表面全体に一旦絶縁膜を形成してから、レーザー加
工等によってオリジナルパッド13部分のみを露出させ
る方法によっても形成できる。
In manufacturing, first, as shown in FIG. 2, an insulating paste is printed on the surface of the passivation film 12 by a screen printing method so that the original pad 13 is exposed, and the printed insulating paste is cured to form an interlayer. The insulating film 14 is formed. As the insulating paste for the interlayer insulating film 14, a resin paste made of a thermosetting polyimide resin, BCB (benzocyclobutene) resin, epoxy resin, or the like that can be cured by heat treatment can be used. It is possible to use a photo-curable resin paste made of polyimide resin, BCB resin, epoxy resin, or the like that can be cured by light irradiation. In addition, the interlayer insulating film 14
Can also be formed by a method in which an insulating film is once formed on the entire surface and then only the original pad 13 is exposed by laser processing or the like.

【0014】次に、図3に示すように、オリジナルパッ
ド13の表面に無電解メッキ法によってNiとAuの2
層から成るUBM層15を形成する。このUBM層15
としてNiを用いる理由はAlから成るオリジナルパッ
ド13との密着力を得ることにあり、Auを用いる理由
は後述するバンプ18の形成前にNiが酸化してしまう
ことを防止することにある。また、Alから成るオリジ
ナルパッド13の表面に形成されている酸化膜は無電解
メッキ法の実施過程で除去される。
Next, as shown in FIG. 3, the surface of the original pad 13 is plated with Ni and Au by electroless plating.
A UBM layer 15 consisting of layers is formed. This UBM layer 15
The reason why Ni is used is to obtain an adhesive force with the original pad 13 made of Al, and the reason to use Au is to prevent Ni from being oxidized before the formation of the bumps 18 described later. Further, the oxide film formed on the surface of the original pad 13 made of Al is removed in the process of performing the electroless plating method.

【0015】次に、図4に示すように、層間絶縁膜14
の表面に、一端部がUBM層15と重なるようにスクリ
ーン印刷法によって導体ペーストを印刷し、印刷した導
体ペーストを硬化させて再配置配線16を形成する。再
配置配線16用の導体ペーストには、熱処理による硬化
を可能とした熱硬化性のエポキシ系樹脂等にAg,Ag
−Pd合金,Ag−Pt合金等の金属粒子を添加したも
の等から成る導体ペーストが使用できる他、紫外光等の
光照射による硬化を可能とした光硬化性のエポキシ系樹
脂等にAg,Ag−Pd合金,Ag−Pt合金等の金属
粒子を添加したもの等から成る導体ペーストが使用でき
る。ちなみに、再配置配線16用の導体ペーストの印刷
にはスクリーン印刷法以外の厚膜形成法、例えばディス
ペンス法によって前記導体パターンを描画し、描画した
導体ペーストを硬化させる方法や、Agを微粒子化して
溶剤中に溶かし込んだ導電性の溶液をインクジェット法
により前記導体パターンを描画し、描画した導体ペース
トを硬化させる方法等が使用できる。
Next, as shown in FIG. 4, the interlayer insulating film 14 is formed.
A conductor paste is printed by a screen printing method on the surface of the so that one end portion thereof overlaps the UBM layer 15, and the printed conductor paste is cured to form the rearrangement wiring 16. The conductor paste for the rearrangement wiring 16 includes Ag, Ag and a thermosetting epoxy resin that can be cured by heat treatment.
In addition to the use of a conductor paste made of a material such as -Pd alloy or Ag-Pt alloy to which metal particles are added, it is possible to use Ag, Ag for a photo-curable epoxy resin or the like that can be cured by irradiation with light such as ultraviolet light. A conductor paste made of a material to which metal particles such as —Pd alloy or Ag—Pt alloy is added can be used. By the way, in printing the conductor paste for the rearrangement wiring 16, a thick film forming method other than the screen printing method, for example, a method of drawing the conductor pattern by a dispensing method and curing the drawn conductor paste, or atomizing Ag A method may be used in which a conductive solution dissolved in a solvent is used to draw the conductor pattern by an inkjet method and the drawn conductor paste is cured.

【0016】次に、図5に示すように、層間絶縁膜14
及びUBM層15の表面に、再配置配線16の一部が接
続用パッド16aとして露出するようにスクリーン印刷
法によって保護ペーストを印刷し、印刷した保護ペース
トを硬化させて表面保護膜17を形成する。表面保護膜
17用の保護ペーストには、前記絶縁ペーストと同様の
ものが使用できる。また、表面保護膜17は、厚膜形成
法によって表面全体に一旦保護膜を形成してから、レー
ザー加工等によって接続用パッド16a部分のみを露出
させる方法によっても形成できる。
Next, as shown in FIG. 5, the interlayer insulating film 14 is formed.
A protective paste is printed on the surface of the UBM layer 15 by a screen printing method so that a part of the rearrangement wiring 16 is exposed as a connection pad 16a, and the printed protective paste is cured to form a surface protective film 17. . The same protective paste as the insulating paste can be used for the surface protective film 17. The surface protective film 17 can also be formed by a method in which a protective film is once formed on the entire surface by a thick film forming method and then only the connecting pad 16a portion is exposed by laser processing or the like.

【0017】次に、図6に示すように、再配置配線の1
6の接続用パッド16a上に、スクリーン印刷法によっ
てはんだペーストを印刷し、印刷したはんだペーストを
加熱溶融してボール状のバンプ18を形成する。バンプ
18用のはんだペーストには、Sn−Pb系の有鉛半田
だけでなく無鉛はんだペーストが使用できる。ちなみ
に、バンプ18の形成には半田ボールを直接搭載する方
法等も使用できる。また、バンプ形成に用いる材料とし
てはんだペーストではなく、前述した再配置配線に用い
た導体ペーストを用いることも可能であり、そのバンプ
18の形状はボール状以外の形状であってもよい。
Next, as shown in FIG.
Solder paste is printed on the connection pads 16a of No. 6 by the screen printing method, and the printed solder paste is heated and melted to form ball-shaped bumps 18. As the solder paste for the bumps 18, not only Sn—Pb based lead-containing solder but also lead-free solder paste can be used. Incidentally, a method of directly mounting a solder ball or the like can be used to form the bump 18. Further, it is also possible to use not the solder paste but the conductor paste used for the above-mentioned rearrangement wiring as a material used for bump formation, and the shape of the bump 18 may be a shape other than a ball shape.

【0018】次に、バンプ18を形成した後のウエハー
11をチップサイズにダイシングして所期の半導体装置
を得る。以上の説明ではウェハサイズで処理を行うもの
として説明をしたが、予めチップサイズにダイシングさ
れたICチップに対して同様な処理することも可能であ
る。
Next, the wafer 11 on which the bumps 18 have been formed is diced into a chip size to obtain a desired semiconductor device. In the above description, the wafer size is used for the processing, but it is possible to perform the same processing on an IC chip previously diced to the chip size.

【0019】図7は図1〜図6に示した製造方法を利用
して製造された半導体装置の一部分を示す。この半導体
装置SC1にはオリジナルパッド13を始点として種々
の形状の再配置配線16が設けられ、再配置配線16の
接続用パッドと導通するようにバンプ18が設けられて
いる。図から分かるように、チップ周囲に1次元的に配
置されていたオリジナルパッド13の位置を再配置配線
16によって2次元的に配置し直すことで、バンプ18
の配置間隔はオリジナルパッド13の配置間隔よりも広
くなっている。
FIG. 7 shows a part of a semiconductor device manufactured by using the manufacturing method shown in FIGS. The semiconductor device SC1 is provided with rearrangement wirings 16 of various shapes starting from the original pad 13, and bumps 18 are provided so as to be electrically connected to the connection pads of the rearrangement wirings 16. As can be seen from the figure, the bumps 18 are repositioned two-dimensionally by the rearrangement wiring 16 from the positions of the original pads 13 which are arranged one-dimensionally around the chip.
Is wider than the original pad 13.

【0020】このように図1〜図6に示した半導体装置
の製造方法によれば、層間絶縁膜14,再配置配線16
及び表面保護膜17の形成に厚膜形成法を用いることに
より、再配置配線16を施すために高価な薄膜形成装置
や露光現像装置等が不要となると共に処理ステップを低
減でき、製造コストを低減して安価な半導体装置を提供
できる利点がある。
As described above, according to the method of manufacturing the semiconductor device shown in FIGS. 1 to 6, the interlayer insulating film 14 and the rearrangement wiring 16 are provided.
Also, by using the thick film forming method for forming the surface protective film 17, an expensive thin film forming device, an exposure and developing device, etc. for providing the rearrangement wiring 16 are not required, and the processing steps can be reduced and the manufacturing cost can be reduced. Then, there is an advantage that an inexpensive semiconductor device can be provided.

【0021】尚、図1〜図6に基づく説明では、再配置
配線16の接続用パッド16a上に直接バンプ18を形
成したが、図8に示すように、接続用パッド16a上
に、無電解メッキ法により補助バンプ19を形成し、こ
の上に前記同様のバンプ20を形成するようにしてもよ
い。また、表面保護膜17を厚く形成することでICに
対する保護がより強固になり、ダイシング後はリアルサ
イズCSPとして取り扱うことが可能となる。
Although the bumps 18 are formed directly on the connection pads 16a of the rearrangement wiring 16 in the description based on FIGS. 1 to 6, as shown in FIG. 8, electroless electrolysis is performed on the connection pads 16a. The auxiliary bump 19 may be formed by a plating method, and the bump 20 similar to the above may be formed thereon. Further, by forming the surface protection film 17 thick, the protection for the IC becomes stronger and it becomes possible to handle it as a real size CSP after dicing.

【0022】次に、第二の目的を達成するための半導体
装置の構造を図9以降に示す。この半導体装置SC2に
はパッド21に接続された種々形状の配線パターン22
が設けられ、その一部に接続用パッド22aが形成され
ている。幾つかの配線パターン22の接続用パッド22
aには外部との接続を目的とした、はんだボール23が
設けられ、また、幾つかの配置パターン22の接続用パ
ッド22aは図11に示す他の半導体装置SC3用の接
続端子としてそのままの状態で露出している。また、半
導体装置SC2の部品実装面には、1つのコンデンサ部
24が2つの配線パターン22の接続用パッド22aと
接続するように設けられ、2つの抵抗部25がそれぞれ
2つの配線パターン22の接続用パッド22aと接続す
るように設けられている。
Next, the structure of a semiconductor device for achieving the second object is shown in FIG. The semiconductor device SC2 has a wiring pattern 22 of various shapes connected to the pad 21.
Is provided, and the connection pad 22a is formed in a part thereof. Connection pads 22 of some wiring patterns 22
Solder balls 23 are provided at a for the purpose of connecting to the outside, and the connection pads 22a of some of the arrangement patterns 22 are left as they are as connection terminals for another semiconductor device SC3 shown in FIG. Is exposed at. Further, on the component mounting surface of the semiconductor device SC2, one capacitor section 24 is provided so as to be connected to the connection pads 22a of the two wiring patterns 22, and two resistance sections 25 are connected to each of the two wiring patterns 22. It is provided so as to be connected to the pad 22a.

【0023】コンデンサ部24は積層セラミックコンデ
ンサ等から成り、一方の外部端子を図中左側の配線パタ
ーン22の接続用パッド22aに接続され、他方の外部
端子を図中右側の配線パターン22の接続用パッド22
aに接続されている。このコンデンサ部24は予め作成
したコンデンサ部品を半田や導電性接着剤を用いて接続
する他、半導体装置SC2の部品実装面に積層構造のコ
ンデンサ回路を直接形成することにより設けることも可
能である。
The capacitor section 24 is composed of a laminated ceramic capacitor or the like, one external terminal of which is connected to the connection pad 22a of the wiring pattern 22 on the left side of the drawing, and the other external terminal of which is connected to the wiring pattern 22 on the right side of the drawing. Pad 22
connected to a. The capacitor section 24 may be provided by connecting a capacitor part which is prepared in advance by using solder or a conductive adhesive, or by directly forming a laminated capacitor circuit on the component mounting surface of the semiconductor device SC2.

【0024】各抵抗部25は、2つの配線パターン22
の接続用パッド22aに重なるようにスクリーン印刷等
の厚膜形成法によって抵抗ペーストを塗布して硬化させ
ることにより形成されている。抵抗部25用の抵抗ペー
ストには、熱硬化性或いは光硬化性の樹脂に金属粉末を
添加したもの等から成る抵抗ペーストが使用できる。勿
論、各抵抗部25は予め作成した抵抗部品を半田や導電
性接着剤を用いて前記コンデンサ部品と同時に実装する
ようにしてもよい。
Each resistance portion 25 has two wiring patterns 22.
It is formed by applying and hardening a resistance paste by a thick film forming method such as screen printing so as to overlap the connection pads 22a. As the resistance paste for the resistance portion 25, a resistance paste made of a thermosetting or photocuring resin to which metal powder is added, or the like can be used. Of course, each resistor portion 25 may be formed by mounting a resistor component prepared in advance at the same time as the capacitor component by using solder or a conductive adhesive.

【0025】図11に示した半導体装置SC3は6つの
ボール状のバンプ31を有している。図12及び図13
に示すように、この半導体装置SC3は各バンプ31が
半導体装置SC2に形成された接続用パッド22aに接
続されている。また、図12には半導体装置SC3がコ
ンデンサ部24及び抵抗部25を覆うようにして半導体
装置SC2に実装されている状態が図示されているが、
コンデンサ部24及び抵抗部25の位置は半導体装置S
C3の下に限定されず、半導体装置SC2の実装面上任
意の位置に配置できることは言うまでもない。
The semiconductor device SC3 shown in FIG. 11 has six ball-shaped bumps 31. 12 and 13
As shown in FIG. 5, each bump 31 of the semiconductor device SC3 is connected to the connection pad 22a formed on the semiconductor device SC2. Further, although FIG. 12 shows a state in which the semiconductor device SC3 is mounted on the semiconductor device SC2 so as to cover the capacitor section 24 and the resistance section 25,
The positions of the capacitor portion 24 and the resistor portion 25 are the semiconductor device S.
Needless to say, it is not limited to under C3 and can be arranged at any position on the mounting surface of the semiconductor device SC2.

【0026】図13から分かるように、実装後の半導体
装置SC3の高さを半導体装置SC2に設けられたはん
だボール23の高さより低くすることで、半導体装置S
C3が実装された半導体装置SC2を基板等に実装する
場合、半導体装置SC3が実装の支障になることはな
い。
As can be seen from FIG. 13, the height of the semiconductor device SC3 after mounting is made lower than the height of the solder balls 23 provided in the semiconductor device SC2, whereby the semiconductor device S
When the semiconductor device SC2 on which C3 is mounted is mounted on a substrate or the like, the semiconductor device SC3 does not hinder the mounting.

【0027】このように図9及び図10に示した半導体
装置SC2と図12及び図13に示した半導体装置によ
れば、配線パターン22の接続用パッド22aを利用し
てコンデンサ部24や抵抗部25等の受動部品や別の半
導体装置SC3を半導体装置SC2に搭載することによ
り、半導体装置SC2の半導体素子に他の回路素子を接
続して三次元に構成された複合回路(図9〜図13参
照)を簡単に構成でき、これにより高密度実装の要求に
追従できる半導体装置を提供できる利点がある。
As described above, according to the semiconductor device SC2 shown in FIGS. 9 and 10 and the semiconductor device shown in FIGS. 12 and 13, the connecting portion 22a of the wiring pattern 22 is used to utilize the capacitor portion 24 and the resistor portion. By mounting passive components such as 25 or another semiconductor device SC3 on the semiconductor device SC2, another circuit element is connected to the semiconductor element of the semiconductor device SC2 to form a three-dimensional composite circuit (FIGS. 9 to 13). (Refer to FIG. 3) can be easily configured, and thus there is an advantage that a semiconductor device that can follow the demand for high-density mounting can be provided.

【0028】尚、図9〜図13に基づく説明では、チッ
プサイズの半導体装置SC2にコンデンサ部24や抵抗
部25や半導体装置SC3等の回路素子を搭載するもの
を例示したが、ウエハーサイズで回路素子を搭載した後
にウエハーをチップサイズにカットして図9及び10に
示す半導体装置SC2や図12及び図13に示す半導体
装置を得るようにしてもよい。
In the description based on FIGS. 9 to 13, the chip size semiconductor device SC2 is provided with the circuit elements such as the capacitor section 24, the resistance section 25, and the semiconductor apparatus SC3. After mounting the elements, the wafer may be cut into a chip size to obtain the semiconductor device SC2 shown in FIGS. 9 and 10 or the semiconductor device shown in FIGS. 12 and 13.

【0029】また、回路素子としてコンデンサ部24と
抵抗部25と半導体装置SC3を例示したが、これら以
外の種々の回路素子を実装できることは言うまでもな
く、配線パターン22の形状も任意に変更可能である。
Although the capacitor portion 24, the resistor portion 25 and the semiconductor device SC3 are illustrated as the circuit elements, it is needless to say that various circuit elements other than these can be mounted, and the shape of the wiring pattern 22 can be arbitrarily changed. .

【0030】さらに、半導体装置SC2としてはんだボ
ール23が設けられているものを示したが、予め作成し
たコンデンサ部品と抵抗部品を半導体装置SC2に実装
する場合には、コンデンサ部品または抵抗部品を搭載す
る前に接続用パッド22a上にスクリーン印刷法によっ
てはんだボール23用のはんだペースト(図6の説明と
同様のもの)を印刷しておき、コンデンサ部品と抵抗部
品を半田によって接続するに際してリフロー炉を通過さ
せるときに、印刷されたはんだボール23用の電極ペー
ストを加熱溶融してボール状のはんだボール23を形成
するようにしてもよい。
Further, although the semiconductor device SC2 provided with the solder balls 23 is shown, when mounting a capacitor component and a resistor component prepared in advance on the semiconductor device SC2, the capacitor component or the resistor component is mounted. A solder paste for solder balls 23 (similar to the one shown in FIG. 6) is printed on the connection pads 22a by a screen printing method before passing through a reflow furnace when connecting the capacitor parts and the resistance parts by soldering. At this time, the printed electrode paste for the solder balls 23 may be heated and melted to form the ball-shaped solder balls 23.

【0031】さらに、半導体装置SC2上に形成する配
線パターン22は図1〜図6に示した再配置配線製造方
法を用いて形成することができる。また、従来例に示し
た様な薄膜技術を用いた再配置配線の形成方法により製
造された半導体装置を半導体装置SC2として用いても
前記同様の作用効果を得ることができる。
Further, the wiring pattern 22 formed on the semiconductor device SC2 can be formed by using the rearrangement wiring manufacturing method shown in FIGS. Further, even when the semiconductor device manufactured by the method of forming the rearranged wiring using the thin film technique as shown in the conventional example is used as the semiconductor device SC2, the same effect as the above can be obtained.

【0032】さらに、図14に示した様に、各種の回路
素子を搭載した半導体装置SC2の部品実装面に表面保
護膜26を形成し、外部との接続端子部分を開口し、そ
の開口部に導電体柱27を埋め込み、導電体柱27の上
にはんだボール28を形成することで回路部品を組み込
んだ真の意味でのSIP(システム・イン・パッケー
ジ)をリアルサイズCSPで作ることができる。
Further, as shown in FIG. 14, a surface protection film 26 is formed on the component mounting surface of the semiconductor device SC2 on which various circuit elements are mounted, the connection terminal portion with the outside is opened, and the opening portion is formed. By embedding the conductor pillars 27 and forming the solder balls 28 on the conductor pillars 27, a true SIP (system-in-package) in which circuit components are incorporated can be made in a real size CSP.

【0033】表面保護膜26の形成と接続端子部の開口
には、既に述べてきたようにスクリーン印刷法など各種
の厚膜形成方法やSC2の部品実装面全面に保護膜を形
成し、接続端子部分をレーザ加工で開口する方法が使用
できる。導電体柱27の形成は無電解メッキ法や導電ペ
ーストを充填する方法が用いられ、はんだボール28は
クリームはんだ印刷法やはんだボールを直接搭載する方
法で形成することができる。
In the formation of the surface protective film 26 and the opening of the connection terminal portion, as described above, various thick film forming methods such as the screen printing method or a protective film is formed on the entire surface of the component mounting surface of SC2, and the connection terminal is formed. A method of opening the portion by laser processing can be used. The conductor columns 27 are formed by an electroless plating method or a method of filling a conductive paste, and the solder balls 28 can be formed by a cream solder printing method or a method of directly mounting the solder balls.

【0034】[0034]

【発明の効果】以上詳述したように、請求項1及び2に
係る発明によれば、再配置配線を施すために高価な薄膜
形成装置等が不要となると共に処理ステップを低減でき
るので、製造コストを低減して安価な半導体装置を提供
できる。
As described above in detail, according to the inventions according to claims 1 and 2, since an expensive thin film forming apparatus or the like for performing the relocation wiring is not required and the processing steps can be reduced, the manufacturing It is possible to reduce the cost and provide an inexpensive semiconductor device.

【0035】また、請求項6及び9に係る発明によれ
ば、半導体素子に他の回路素子を接続して三次元に構成
された複合回路を簡単に構成することができ、これによ
り高密度実装の要求に追従できる半導体装置を提供でき
る。
Further, according to the inventions according to claims 6 and 9, it is possible to easily construct a three-dimensional composite circuit by connecting another circuit element to the semiconductor element, whereby high-density mounting can be achieved. It is possible to provide a semiconductor device that can comply with the above requirements.

【図面の簡単な説明】[Brief description of drawings]

【図1】ウエハーを示す図FIG. 1 is a diagram showing a wafer.

【図2】層間絶縁膜形成後の断面図FIG. 2 is a sectional view after forming an interlayer insulating film.

【図3】UBM形成後の断面図FIG. 3 is a sectional view after UBM formation.

【図4】再配置配線形成後の断面図FIG. 4 is a cross-sectional view after forming the rearrangement wiring.

【図5】表面保護層形成後の断面図FIG. 5 is a cross-sectional view after forming a surface protective layer.

【図6】バンプ形成後の断面図FIG. 6 is a sectional view after bump formation.

【図7】図1〜図6に示した製造方法を利用して製造さ
れた半導体装置の一例を示す図
FIG. 7 is a diagram showing an example of a semiconductor device manufactured by using the manufacturing method shown in FIGS.

【図8】図6に示したバンプ形成方法の変形例を示す図FIG. 8 is a diagram showing a modification of the bump forming method shown in FIG.

【図9】半導体装置の上に回路部品を搭載した状態を示
す図
FIG. 9 is a diagram showing a state in which circuit components are mounted on a semiconductor device.

【図10】図9の側面図FIG. 10 is a side view of FIG.

【図11】図9に示した半導体装置に搭載される他の半
導体装置を示す図
FIG. 11 is a diagram showing another semiconductor device mounted on the semiconductor device shown in FIG. 9;

【図12】図9に示した半導体装置に図11に示した半
導体装置を搭載した状態を示す図
12 is a diagram showing a state in which the semiconductor device shown in FIG. 11 is mounted on the semiconductor device shown in FIG.

【図13】図12の側面図FIG. 13 is a side view of FIG.

【図14】図12に示した半導体装置に絶縁膜を形成し
てICパッケージとなった状態を示す図
14 is a diagram showing a state in which an insulating film is formed on the semiconductor device shown in FIG. 12 to form an IC package.

【符号の説明】[Explanation of symbols]

11…シリコンウエハー、12…パッシベーション膜、
13…オリジナルパッド、14…層間絶縁膜、16…再
配置配線、16a…接続用パッド、SC1…半導体装
置、SC2…半導体装置、21…パッド、22…配線パ
ターン、22a…接続用パッド、24…コンデンサ部、
25…抵抗部、SC3…半導体装置。
11 ... Silicon wafer, 12 ... Passivation film,
13 ... Original pad, 14 ... Interlayer insulating film, 16 ... Relocation wiring, 16a ... Connection pad, SC1 ... Semiconductor device, SC2 ... Semiconductor device, 21 ... Pad, 22 ... Wiring pattern, 22a ... Connection pad, 24 ... Capacitor part,
25 ... Resistor section, SC3 ... Semiconductor device.

Claims (9)

【特許請求の範囲】[Claims] 【請求項1】 半導体素子を備えた半導体基板に、オリ
ジナルパッドと接続し、且つ、一部が接続用パッドとし
て露出する再配置配線を設けた半導体装置において、 前記再配置配線が厚膜形成法によって形成された厚膜か
ら成る、 ことを特徴とする半導体装置。
1. A semiconductor device comprising a semiconductor substrate having a semiconductor element, and a rearrangement wiring which is connected to an original pad and is partially exposed as a connection pad, wherein the rearrangement wiring is a thick film forming method. A semiconductor device comprising a thick film formed by.
【請求項2】 半導体素子を備えた半導体基板に、オリ
ジナルパッドと接続し、且つ、一部が接続用パッドとし
て露出する再配置配線を設ける半導体装置の製造方法に
おいて、 前記再配置配線を厚膜形成法によって形成する、 ことを特徴とする半導体装置の製造方法。
2. A method for manufacturing a semiconductor device, wherein a semiconductor substrate having a semiconductor element is provided with a rearrangement wiring which is connected to an original pad and a part of which is exposed as a connection pad, wherein the rearrangement wiring is a thick film. A method of manufacturing a semiconductor device, characterized by forming by a forming method.
【請求項3】 厚膜形成法は、スクリーン印刷法によっ
て導体ペーストを印刷し、印刷した導体ペーストを硬化
させるステップを含む、 ことを特徴とする請求項2に記載の半導体装置の製造方
法。
3. The method of manufacturing a semiconductor device according to claim 2, wherein the thick film forming method includes a step of printing a conductor paste by a screen printing method and curing the printed conductor paste.
【請求項4】 厚膜形成法は、ディスペンサ法によって
導体ペーストを描画し、描画した導体ペーストを硬化さ
せるステップを含む、 ことを特徴とする請求項2に記載の半導体装置の製造方
法。
4. The method of manufacturing a semiconductor device according to claim 2, wherein the thick film forming method includes a step of drawing a conductor paste by a dispenser method and curing the drawn conductor paste.
【請求項5】 厚膜形成法は、インクジェット法により
導体ペーストを描画し、描画した導体ペーストを硬化さ
せるステップを含む、 ことを特徴とする請求項2に記載の半導体装置の製造方
法。
5. The method of manufacturing a semiconductor device according to claim 2, wherein the thick film forming method includes a step of drawing a conductor paste by an inkjet method and curing the drawn conductor paste.
【請求項6】 半導体素子を備えた半導体基板に、オリ
ジナルパッドと接続し、且つ、一部が接続用パッドとし
て露出する複数の再配置配線を設けた半導体装置におい
て、 前記接続用パッドが露出する面には、2以上の接続用パ
ッドと接続する少なくとも1つの回路素子が設けられて
いる、 ことを特徴とする半導体装置。
6. A semiconductor device comprising a semiconductor substrate having a semiconductor element and a plurality of relocation wirings connected to an original pad and partially exposed as a connection pad, wherein the connection pad is exposed. At least one circuit element that is connected to two or more connection pads is provided on the surface of the semiconductor device.
【請求項7】 回路素子は、受動部品である、 ことを特徴とする請求項6に記載の半導体装置。7. The circuit element is a passive component, 7. The semiconductor device according to claim 6, wherein: 【請求項8】 回路素子は、半導体素子を備えた半導体
装置である、 ことを特徴とする請求項6に記載の半導体装置。
8. The semiconductor device according to claim 6, wherein the circuit element is a semiconductor device including a semiconductor element.
【請求項9】 半導体素子を備えた半導体基板に、オリ
ジナルパッドと接続し、且つ、一部が接続用パッドとし
て露出する複数の再配置配線を設ける半導体装置の製造
方法において、 前記接続用パッドが露出する面に、2以上の接続用パッ
ドと接続するように少なくとも1つの回路素子を設け
る、 ことを特徴とする半導体装置の製造方法。
9. A method of manufacturing a semiconductor device, wherein a semiconductor substrate having a semiconductor element is provided with a plurality of rearrangement wirings connected to an original pad and a part of which is exposed as a connection pad. A method of manufacturing a semiconductor device, wherein at least one circuit element is provided on the exposed surface so as to be connected to two or more connection pads.
JP2001226172A 2001-07-26 2001-07-26 Semiconductor device and manufacturing method thereof Expired - Fee Related JP4122143B2 (en)

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