JP2003036680A - Flash memory and its storage data erasing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a flash memory in which an erasure sector of a bank unit can be specified and a command input time can be shortened. SOLUTION: When 6th cycle of a command cycle of a sector erasing function is divided into the first half cycle and the second half cycle and bank addresses being different depending on the first half and the second half are specified in 6th address hold-time, as a holding pulse of bank selection information BKLACLK is outputted from a command controller 21, and all sector information included in a specified bank are held en bloc in a sector latch circuit 22 as an erasure sector, in the sector erasing function, erasing sectors in all sectors can be specified with not only erasure specifying of only one sector but a bank unit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flash memory in a non-volatile semiconductor memory device and a method of erasing stored data thereof. In particular, in a sector erasing function, an erasing sector can be designated in a bank unit, and command input time can be shortened. The present invention relates to a flash memory improved as much as possible and a stored data erasing method thereof.

[0002]

2. Description of the Related Art In recent years, with the progress of miniaturization technology of semiconductor elements, LSIs composed of the semiconductor elements have become large in scale, and this tendency is particularly remarkable in the field of semiconductor memory devices.

For example, a dynamic random access memory (DRAM) and a synchronous dynamic random access memory (SDRAM) have been put into practical use as a semiconductor memory having a capacity of 256 Mbits per chip. In the field of non-volatile memory as opposed to these volatile memories, there is a read-only memory (ROM) as a read-only semiconductor memory device, and further, electrically rewritable EEPROMs and flash memories are also increasing in capacity. I'm out. Flash memory is EEP
Flash type EEPR that can erase all the data of each block or all bits of data as a ROM
It is OM.

When writing or erasing the flash memory, a setting command such as a write command or an erase command is given to the flash memory, and the flash memory executes the operation according to the command.

Generally, an instruction is given to a certain one function operation by two command cycles, that is, a cycle for inputting an operation mode command code and a cycle for inputting data contents.

On the other hand, this type of conventional flash memory generally has a sector erase function. A sector is a unit obtained by dividing a memory cell into areas that are erased at once,
For example, in the case of a 32 Mbit flash memory, "5
The memory cell configuration is "12 Kbits x 64 sectors".

Further, the flash memory has a dual function. The dual function divides a sector group into units called banks. For example, in the case of a 32M flash memory, 64 sectors have a structure of 16 sectors × 4 banks, and a sector group included in one bank is erased by a sector erase function. Among them, it is a function capable of reading the memory cells in the other three banks.
In other words, the sector erase function and the read function can be simultaneously executed on one chip.

Referring to FIG. 7 showing a configuration example of a conventional flash memory, the conventional flash memory includes a control buffer 11, an I / O buffer 12, an address buffer 13, a command address decoder 14, and
A command control circuit 15c, an internal address generation circuit 16, a sector decoder 17, and a sector latch circuit 24 are provided.

The control buffer 11 is a circuit which receives a chip enable signal CE and a write enable signal WE which are external control signals, and generates clock signals TWE and AD1LACLK for fetching a command code and an address in a command cycle. The fall timing of these clock signals is determined by the later fall timing of the chip enable signals CE and WE, and the rise timing is determined by the faster rise timing of the chip enable signals CE and WE. .

The I / O buffer 12 takes in the command code supplied from the command signal DQi in the command cycle in synchronization with the clock signal TWE input from the control buffer 11.

The address buffer 13 receives the address signal Ai corresponding to the command signal DQi during the command cycle.
The address supplied from the control buffer 11
It is taken in as an address for sector erasing in synchronization with a clock signal TWE input from.

In the command cycle, the command address decoder 14 decodes the address supplied from the address signal Ai and input through the address buffer (55).
5h / 2AAh) and decode signal TA555 / TA2
This is a circuit that outputs AA.

The command control circuit 15c receives the command code DQ input in the command cycle.
It is a circuit that confirms whether i and the address signal Ai are established in each cycle and generates an establishment signal after the fifth command is established and an erase function start signal LACLK after the sixth command.

The internal address generation circuit 16 is a circuit for generating an address for selecting a flash memory cell in executing the erase operation inside the chip after the erase function command is satisfied.

When executing the erase command (sixth command), the sector decoder 17 receives the sector selection information T according to the address of the sector to be erased, which is input from the address signal Ai.
Generate SAi. Further, it is a circuit for generating sector selection information ISAi by an internal address after the erase function is started.

In the erase function, the sector latch circuit 24 latches sector selection information TSAi to be erased for performing an erase command (sixth command). Further, after starting the erase function, the circuit compares the sector (signal ISAi) selected through the sector decoder with the latch information at the address generated by the internal address, and outputs the erase sector information LASAi.

Referring to FIG. 8 which is a circuit diagram of the sector latch circuit 24, the sector latch circuit 24 has a power supply potential V
Between the DD and the ground potential GND, a p-channel MOS transistor P20 and an n-channel MOS transistor N5 are connected.
0 and n channel type MOS transistors N60 are inserted and connected in series, and inverters 250 and 260 are respectively connected between the series connection point of p channel type MOS transistor P20 and n channel type MOS transistor N60 and the erase sector information output terminal. Of the exclusive OR circuit 270 is connected to the output terminal of this latch and the sector selection information ISAi is input to the other input terminal. 1
As many sets as the number of sector addresses are provided as sets, and as many sets as the number of sector addresses are provided for the number of banks.

A command input operation when the sector erase function is executed in the conventional flash memory described above will be described. Referring to FIG. 7 and FIG. 9 showing a timing chart for explaining the operation of the conventional sector erase function, an example of executing the sector erase function in six command cycles will be shown here.

First, in the flash memory, the control buffer 11 starts an erase command cycle in synchronization with the falling edge of the chip enable signal CE / write enable signal WE, whichever is later, and outputs the clock signal output from the control buffer 11. TWE becomes a logic level H level.

On the other hand, the address buffer 13 continues to input the address 555h during the address hold time in synchronization with the clock signal TWE = H level. Upon receiving the address 555h from the address buffer 13, the command address decoder 14 outputs the output signal TA555 at the H level.

Further, the clock signal AD1LACLK =
Upon receiving the H level, the H level is held even after the address hold time.

On the other hand, the I / O buffer 12 inputs and outputs the command code AAh from the command signal DQi within the command set time in synchronization with the clock signal TWE = H level, and outputs the output command code A.
The command control circuit 15c takes in Ah.

Next, the clock signal TWE becomes L level in synchronization with the rising edge of the chip enable signal CE / write enable signal WE, whichever comes first.

In synchronization with the clock signal TWE = L level, the clock signal AD1LACLK = H level is also delayed and becomes L level. At that time, the command control circuit 1
5c recognizes the address information TA555 and the command code AAh held inside, and the command of the first cycle is established.

Similarly in the second cycle and thereafter, the address information TA2AA and the command code 55h held in the command control circuit 15c are similarly synchronized with the chip enable signal CE / write enable signal WE and the clock signal TWE. Upon recognition, the command of the second cycle is established. Further, the address information TA555 and the command code 80h are recognized, the command of the third cycle is established, and the address information TA555 and the command code AAh
And the command of the fourth cycle is established, the address information TA2AA and the command code 55h are recognized,
The command of the fifth cycle is established.

Then, in the sixth cycle, the I / O buffer 12 outputs the address (SA0) of the sector to be erased in synchronization with the later rising timing of the chip enable signal CE / write enable signal WE as an address signal. Input from Ai, command control circuit 1
5c and the sector decoder 17 are continuously input during the address hold time.

The sector decoder 17 outputs sector selection information TSA0 = H level to the selector latch circuit 24.

On the other hand, the I / O buffer 12 receives and outputs the command code 30h from the command signal DQi within the address hold time in synchronization with the clock signal TWE = H level, and outputs the output command code 30h as a command. The control circuit c15 takes in.

Next, the clock signal TWE becomes L level in synchronization with the rising edge of the chip enable signal CE / write enable signal WE, whichever comes first. In synchronization with the clock signal TWE = L level, the clock signal AD1LACLK = H level is also delayed and becomes L level. At that time, the command control circuit 15c recognizes the command code 30h, and the command of the sixth cycle is established.

At the same time, in synchronization with the clock signal TWE = L level, the selector latch pulse LACLK of the command control circuit 15c becomes H level (one shot pulse), and the sector selection information LSA0 = H level is held in the sector latch circuit 24. It

Next, the clock signal AD1 which becomes L level
The sector selection information TSA0 becomes L level in synchronization with the fall timing of LACLK.

Furthermore, when erasing a plurality of sectors, 30h of the sixth cycle and the addresses SA1 to SAi of the sectors to be erased are sequentially input, and the sector selection information TSA1 to SAi to be erased is held.

Referring to FIG. 10 showing the flowchart of the sector erase function, the sector selection information TSAi to be erased is latched by the sector latch circuit 24 upon completion of the command input of the sector erase function (step S21). Then, the sector selection information ISAi based on the internal address is set (step S22).

If the sector designated by the sector selection information ISAi and the held sector selection information TSAi match, the process proceeds to step S24 and step 25 (step 2).
3).

If they match, the sector erase function is executed for the erase-designated sector (step S24).

If they do not match, sector selection information ISAi
= ISAi + 1 is further incremented (step S25).

It is judged whether the sector erase function has been executed for the last erase-designated sector, and if it is the last erase-designated sector, it ends, and if not the last, it returns to step 25 (step S26).

On the other hand, in Japanese Patent Laid-Open No. 11-273370, when a command for continuously reading data, writing data, or erasing data is externally input to the same sector address, it is enabled in the memory chip. Output chip enable signal,
It is described that data read, data write, or data erase can be successively performed for the same sector address in a memory chip by one time input of a command and a sector address.

Further, any one of the memory chips
When a command for erasing data is externally input to one sector address, the chip enable signal for enabling is output only to the memory indicated by the externally input sector address, and the desired chip in the memory chip is output. It is described that data erase is also performed for one sector address.

However, in this conventional example, as in the invention of the present application, the first half of one cycle period of the erase command
Hold the decode information of the erase address of the second erase address, and further hold the decode information of the second erase address in the latter half of the second half, and compare whether the stored code information of the first and second erase addresses specifies the same bank. Therefore, it does not have a function of determining whether to erase one sector in a bank or all sectors in a bank, and therefore the configuration is different.

[0041]

As described above, the capacity of flash memory is increasing, and the number of sectors is increasing accordingly. Therefore, when erasing a plurality of sectors, 30h of the sixth cycle and the addresses SA1 to SAi of the sectors to be erased are sequentially input, and the sector selection information TSA1 to SAi to be erased is held.

When the command input of the sector erase function is completed, the sector selection information TSAi to be erased is latched in the sector latch circuit 24, and then the sector selection information ISAi according to the internal address is set. Sector selection information I
The sector erase function is repeatedly executed for the erase designated sector until the sector designated by SAi and the held sector selection information TSAi match.

That is, the erase command (3
Since it is necessary to continuously input (0h + sector address) for the number of sectors to be erased, the command input time will be increased in the future.

The object of the present invention is made in view of the above-mentioned conventional drawbacks. In the erase command of the sixth cycle, the erase address specified within the address hold time is divided into the first half and the second half. A function of holding and comparing whether each of the divided two addresses designates the same bank and further judging whether the sector is erased or the bank is erased based on the comparison result, and if the bank is erased, all the sectors in the bank are collectively erased. The purpose of this is to provide a flash memory in which the erase sector can be designated for each bank and the command input time can be shortened.

[0045]

In a flash memory of the present invention, a sector erase operation of a flash memory cell array is sequentially executed by first to nth commands in an n cycle period, and an address hold time at the time of executing the nth command. Holds the decode information of the first erase address given in the first half of the n-th cycle period, and holds the decode information of the second erase address given in the latter half of the n-th cycle period. It is provided with a function of comparing whether the decoded data of the first and second erase addresses designated the same bank.

Further, when the result of the comparison specifies the same bank, it is judged that one sector in the bank is erased, and when different banks are specified, it means that all sectors in the bank are collectively erased. An erasure judgment function for judging can be provided.

Further, the batch erase sector information of all the sectors in the bank designated by the first erase address and the second erase sector information.
The erase sector information holding function for holding the bank information designated by the erase address may be provided.

Another feature of the flash memory of the present invention is that
When the sector erase function command of the flash memory cell is input, the first command code for holding the sector information to be erased in sector units is input and retained as the erase sector of only one sector This is to have a sector erase function of inputting the second command code to be held and holding all the sectors in the bank as erase sectors.

Another feature of the flash memory of the present invention is that
The erase sector address is input in two cycles within the address hold time when the sector erase command of the flash memory cell is executed, and the first cycle is held as the erase sector and bank information including the erase sector. Hold the cycle of as other erase bank information, and recognize whether the same bank is designated or a different bank is designated according to the comparison result of the bank information including these erase sectors and other erase bank information, It has a function to judge sector erase if the same bank is specified and bank erase if different banks are specified.

Further, by providing the erase sector address divided into two in one cycle, it has a function of executing batch erase of all sectors in one bank in one command cycle.

Further, the means for holding as bank information including the erase sector generates and generates a select signal of the erase bank including the erase sector in accordance with the address designating the erase sector in the first cycle. It is a first bank decoder means for latching the selection signal with a first clock signal synchronized with the chip enable or write enable signal.

Further, the means for holding as the other bank information generates the selection signal of the erase bank including the erase sector according to the address designating the erase sector in the second cycle, and the generated signal. Second bank decoder means for latching the selection signal with a second clock signal synchronized with the chip enable or write enable signal.

Whether the same bank is designated,
The means for recognizing whether or not the different bank is designated judges whether it is a sector latch or a bank clutch based on the completion information of the sector erase function command and the information of the comparison result, and outputs a pulse signal of the judgment result. It is a means.

Further, in order to function to judge the sector erase or the bank erase, the information indicating the same bank or a different bank for performing the erase at the time of the erase command is latched, and the latched sector is latched. The information is compared with the sector information selected via the sector decoder based on the address generated by the internal address generation means after the start of the erase function, and if they match, the sector selected by the internal address is determined to be the sector to be erased. The internal sector has a first sector latch means for judging, performing the erasing operation on the sector, and outputting the next sector address to judge the match or non-match when the comparison result is different.

Furthermore, in order to function as the sector erase, when a given command signal is recognized and latched in sector units, it is output in the first code that the latch is in sector units, and the bank is output. In the case of batch latching in units, command control means for outputting the batch latch in bank units by the second code and first and second corresponding first and second codes are received. A second command pulse generating means for generating a second command latch pulse is compared with the first and second latch pulses and sector selection information obtained by decoding the sector address to be erased, and outputs a sector erase control signal. And sector latch means.

In the second sector latch means, the first p-channel type MOS transistor, the first n-channel type MOS transistor and the second n-channel type MOS transistor are connected in series between the power supply potential and the ground potential. Signal is supplied to the gate of the first p-channel MOS transistor at the ground potential during the erasing period, and the gate of the first n-channel MOS transistor is supplied with the batch-in-bank erase sector information. Erase sector selection information based on the first erase address is applied to the gate of the n-channel MOS transistor, and between the series connection point of the first p-channel MOS transistor and the first n-channel MOS transistor and the ground potential. To a third n-channel MOS transistor and a fourth n-channel MOS transistor. Inserted and connected the static in the series connection state,
Erase bank information is given to the gate of the third n-channel MOS transistor, sector selection information based on the internal address is given to the gate of the fourth n-channel MOS transistor, and the first and second portions are connected to the series connection point. Of each of the inverters is connected to the other input terminal of the latch, the output terminal of the latch is connected to one input terminal of the exclusive OR circuit, and the other input terminal is based on the internal address. One set of configurations for inputting sector selection information is provided for the number of sector addresses, and sets for the number of sector addresses are provided for the number of banks.

According to the flash memory stored data erasing method of the present invention, the erase sector address is given to the address buffer in two cycles within the address hold time when the sector erase command of the flash memory cell is executed.
Cycle is held as erase sector and bank information including the erase sector, and the second cycle is held as other erase bank information, and the held bank information including the erase sector is compared with the other erase bank information. Depending on the result, it is recognized whether the same bank is designated or a different bank is designated, and if the same bank is designated, sector erase is performed, and if different bank is designated, bank erase is performed.

Further, it is possible to execute the batch erase of all the sectors in one bank in one command cycle.

Another feature of the stored data erasing method of the flash memory of the present invention is that the sector erasing operation of the flash memory cell array is sequentially executed by the first to nth commands in the n cycle period, and at the time of executing the nth command. Holding the decode information of the first erase address given in the first half of the n-th cycle period in the first bank decoder within the address hold time;
The step of holding the decode information of the second erase address given in the second half of the cycle period in the second bank decoder and the decode information of the held first and second erase addresses specify the same bank. If the result of the comparison specifies the same bank, it is determined that one sector in the bank is erased, and if different banks are specified, all sectors in the bank are compared. And a step of erasing the flash memory cell based on the determination.

[0060]

BEST MODE FOR CARRYING OUT THE INVENTION First, a first embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of a main part of a first embodiment of a flash memory of the present invention, FIG. 2 is a circuit diagram of a sector latch circuit 22, and FIG. 3 is a timing chart for explaining the operation of the first embodiment. It is a chart. Referring to FIGS. 1 and 3, the flash memory 1 includes a control buffer 11, an I / O buffer 12, and an address buffer 13.
A command address decoder 14, a command control circuit 15a, an internal address generation circuit 16, a sector decoder 17, a bank decoder 18, a bank decoder 19, a bank comparison circuit 20, a command controller 21, and a sector latch circuit 22. And

The control buffer 11 receives clock signals TWE and AD from the external control signals CE and WE for fetching a command code and an address at the time of a command cycle.
This is a circuit for generating 1LACLK and AD2LACLK.

Clock signals TWE, AD1LACLK,
The rising timing of AD2LACLK is CE, WE
Whichever is later, the trailing edge is determined, and the trailing timing is determined by the leading edge of CE or WE, whichever is earlier.

The I / O buffer 12 is a circuit for taking in the command code supplied from the command signal DQi in the command cycle in synchronization with the clock signal TWE.

The address buffer 13 is a circuit for fetching the address code supplied from the address signal Ai into the inside thereof in synchronization with the clock signal TWE during the command cycle.

The command address decoder 14 receives the address supplied from the address signal Ai and input through the address buffer 13 during the command cycle, that is,
This circuit is represented by Ai in FIG. 3 to be described later with address codes 555h and 2AAh, decodes these address codes, and outputs decode signals TA555 and TA2AA.

In the erase function command cycle, the command control circuit 15a confirms whether or not the relationship between the input command signal DQi and the corresponding address signal Ai is established for each command cycle, and the fifth command is established. Later establishment signal (a signal to be output to the control buffer, which serves as a flag for generating AD2LACLK) and an erase function start signal BKLA after the execution of the sixth command
This is a circuit that generates CLK and LACLK.

The internal address generation circuit 16 generates an internal address in synchronization with the internal address generation start flag output from the command control circuit 15a. For example, after the erase function command for 6 cycles is established, when the erase operation is executed, the address for selecting the flash memory cell is not supplied from the outside, so it is a circuit for generating inside the chip.

However, the internal address does not operate immediately after fetching the sixth command (erase command), but operates as follows.

When erasing a plurality of sectors, an erase command (for example, 30h which will be described later) is repeatedly input, but a wait time is provided as a timeout from the first 30h input to the second 30h input. This time-out is described in the data sheet of the flash memory, and is generally 50 to 100 μsec although it varies depending on the flash memory product.

After the first input, if the time-out period is reached, the second time is accepted, and after the second input, a new time-out period is set and the third time is waited for acceptance.

That is, when the timeout period ends,
After that, the erase command cannot be accepted. After the time-out period ends, the erase function internally starts and the internal address operates.

Therefore, the internal signal from the command control circuit to the internal address generation circuit becomes a flag signal for starting the erase operation since the time-out period has ended.

When the erase command (sixth command) is executed, the sector decoder 17 receives, for example, the upper addresses SA0 to SA of the sector to be erased, which is input from the address signal Ai.
A sector selection signal TSAi is generated by i, for example, lower addresses 555h to 2AAh. Further, it is a circuit for generating the sector selection signal ISAi based on the generated internal address after the start of execution of the erase function.

When executing the erase command (sixth command), the bank decoder 18 responds to an address (eg, SA0) designating the erase sector in the first half of the command cycle in response to the first erase bank selection signal of the erase bank including the erase sector. T
This is a circuit that generates ABKi and latches the generated first erase bank selection signal TABKi in synchronization with the clock signal AD1LACLK from the control buffer 11.

When executing the erase command (sixth command), the bank decoder 19 responds to an address (for example, SA50) designating the erase sector in the latter half of the command cycle in response to the second erase bank selection signal of the erase bank including the erase sector. TBBK is generated, and the generated bank selection signal TBBKi is generated.
The clock signal AD2 from the control buffer 11
This is a circuit for holding in synchronization with LACLK.

The bank comparison circuit 20 receives the first bank selection signal TABKi held in the bank decoder 18 and the bank decoder 19 when the erase command (sixth command) is executed.
Is compared with the second bank selection signal TBBKi held in the memory to determine whether they are the same, and the determination result information TCO
It is a circuit that outputs MP.

The command controller 21 determines whether the erase command (sixth command) completion information BKLACLK given from the command control circuit 15a and the bank from the bank comparison circuit 20 are the same or not.
Determines whether it is a sector latch or a bank clutch. In the case of a sector latch, a latch pulse is output by the erase function start signal LACLK. In the case of a bank latch, the erase function start signal BK.
It is a circuit that generates a latch pulse with LACLK.

When executing the erase command (sixth command) for the erase function, the sector latch circuit 22 outputs the erase function start signal LACLK and the sector selection information TSAi, or the erase function start signal BKLACLK and the second erase bank selection signal TABKi to the H level. The erase sector information LASAi obtained when the level is reached is latched. Further, after the erase function is started, the sector selection information ISAi selected through the sector decoder 17 based on the address generated by the internal address generation circuit 16 and the erased sector information LA latched
This circuit compares SAi and outputs a match / mismatch signal.

When the sector selection information ISAi and the erase sector information LASAi match, it is determined that the sector selected by the internal address is the sector to be erased, and the erase operation is performed on that sector. When the sector selection information ISAi and the erase sector information LASAi do not match, the next sector address is output as the internal address, and it is determined again whether they match.

Referring to FIG. 2, the sector latch circuit 22
Is the first p between the power supply potential VDD and the ground potential GND.
The channel type MOS transistor P10, the first n-channel type MOS transistor N10 and the second n-channel type MOS transistor N20 are inserted and connected in series.

First p-channel MOS transistor P
The gate of 10 has a signal BR which becomes L level during the erase operation.
ST is applied to the first n-channel MOS transistor N
An erase function start signal LACLK is given to the gate of 10.
Sector selection information TSAi is given to the gate of the second n-channel MOS transistor N20.

The p-channel type MOS transistor P
The third n-channel type M between the series connection point A of the 10 and n-channel type MOS transistor N10 and the ground potential GND.
OS transistor N30 and fourth n-channel MO
The S transistor N40 is inserted and connected in series.

Third n-channel MOS transistor N
An erase function start signal BKLACLK is applied to the gate of 30, and a first erase bank select signal TABKi is applied to the gate of the fourth n-channel MOS transistor N40.

Further, the inverter 22 is connected to the serial connection point A.
The output terminal of 0 and the input terminal of the inverter 230 are connected in common, and the output terminal of the inverter 230 and the input terminal of the inverter 220 are connected in common to form a latch, and the common connection point B (erasing sector information output in the claims). Terminal) erasing sector information LASAi and exclusive OR circuit 2
40 to one of the input terminals and the other input terminal to the sector selection information ISAi to obtain the exclusive OR circuit 2
The configuration in which the coincidence / non-coincidence signal is output from 40 is provided as one set for the number of sector addresses, and the set for the number of sector addresses is provided for the number of banks.

Next, the operation of the first embodiment of the flash memory of the present invention having the above-mentioned configuration will be described.

Referring again to FIGS. 1 and 3, in this embodiment, the sector erase function command, for example, 6
The description will be given assuming that the cycle is assigned in advance. The six command cycles mean that the chip enable signal CE / write enable signal WE are both at L level, in other words, TWE = H level.

Further, as a feature of the present invention, the erase address signal Ai designated in the erase command of the sixth cycle is divided into the first half of the cycle and the second half of the cycle. Here, as an example, the first half of the cycle is used. The case where sector 0 is the erase address specified by and the sector 50 is the erase address specified in the second half of the cycle is shown. As the erase command DQi at that time, an example in which the code is 30h is shown.

In other sector erase function command cycles, the address signal Ai in the first cycle is 555h, the erase command DQi is code AAh, the address signal Ai in the second cycle is 2AAh, and the erase command DQi is code 55h. Address signal Ai of the third cycle
Is 555h, the erase command DQi is code 80h, the fourth cycle address signal Ai is 555h, the erase command DQi is code AAh, the fifth cycle address signal Ai is 555h, and the erase command DQi is code AAh. As described below.

After the fifth cycle of the sector erase function command cycle is established, the chip enable signal CE / write enable signal W is issued in the first half of the erase cycle of the sixth command.
The address buffer 13 wants to erase an address (for example, SA0) in synchronization with either one of the late fall timings of E, that is, the rise timing of the clock signal TWE generated by the control buffer 11.
From Ai.

After inputting the address SA0 from Ai, the sector decoder 17 selects the erase sector in synchronization with the rising timing of the clock signal AD1LACLK output from the control buffer 11, and selects the sector output from the sector decoder 17. Information TSA0 = H
It becomes a level. This H level is the clock signal AD1LA.
It is held until the falling timing of CLK.

Further, the address SA0 is selected in the bank decoder 18 in synchronization with the rising timing of the clock signal AD1LACLK, and the bank including the erase sector is selected. The first erase bank selection signal TABK0 = It becomes H level. This H level is held until the falling timing of the clock signal AD1LACLK.

That is, the sector selection information TSA0 and the first erase bank selection signal TABK0 are the clock signal A.
It is shown that it is held by D1LACLK.

After that, in the latter half of the sixth command erase cycle and within the sector address hold time, one of the chip enable signal CE and the write enable signal WE falls late, that is, it is generated by the control buffer 11. Clock signal AD2LA
In synchronization with the rising edge of CLK, the address buffer 13 addresses (eg, SA5) belonging to a bank other than the bank including the erase sector to be erased.
0) is input from Ai.

After the address SA50 is input from Ai, the address SA50 is selected by the bank decoder 18 in synchronization with the rising timing of the clock signal AD2LACLK, other than the bank including the erase sector to be erased, that is, a different bank. The second erase bank selection signal TBBK1 output from the bank decoder 19
= H level.

This H level is the clock signal AD2LAC.
It is held until the falling timing of LK. That is, the second erase bank selection signal T as different bank information
It is shown that BBK1 is held by the clock signal AD2LACLK.

Then, the command code 30h is inputted from the DQi via the I / O buffer 12, and the rising timing of the chip enable signal CE / write enable signal WE, whichever is earlier, that is, the clock signal output from the control buffer 11 is output. Output from the command control circuit 15a to the command controller 21 in synchronization with TWE = L level.

On the other hand, the bank comparison circuit 7 compares the first erase bank selection signal TABKi with the second erase bank selection signal TBBKi, and if the banks are different, the comparison result judgment result information TCOMP = H level.

Judgment result information TC from the bank comparison circuit 7
When the command controller 21 receives the OMP = H level, the erase function start signal BKLACLK = H level is output to the sector latch circuit 22.

Referring again to FIG. 2, an erase function start signal BKLACLK indicating that the bank is different here.
In the sector latch circuit 22 which has received one pulse of = H level, all of the n-channel type MOS transistors N30 to N3n become conductive, and the n-channel type MOS transistors N40 to N4n also have the first erase bank selection signal TABK0.
= H level, all become conductive and L level is output to each common connection contact A.

When the L level is inverted in polarity and becomes the H level and latched, all sectors in the bank including the sector to be erased are held in the sector latch circuit as erased sectors. The held H level and the sector selection information ISA0 to ISAi at the time of the internal address are individually compared by the exclusive OR circuits 240 to 24n, and the H level indicating the sector erase of each of the erase sector information LASAi to LASAi + 7 is a match signal. Is output as.

Next, a case where the same sector address SA0 is input in the first half and the second half of the sixth cycle within the address hold time of the sixth cycle as in the conventional case will be described.

In the second half of the erase cycle of the sixth command and within the sector address hold time, either the slow fall timing of the chip enable signal CE / write enable signal WE, that is, the clock generated in the control buffer 11 The address buffer 1 is synchronized with the rising timing of the signal AD2LACLK.
3 is the same as in the first half of the sixth cycle, the bank address SA including the erase sector to be erased.
0 is input (not changed) again from Ai.

After inputting the address SA0 from Ai, the address SA0 is synchronized with the rising timing of the clock signal AD2LACLK in the bank decoder 18,
The bank including the erase sector to be erased is selected, and the second erase bank selection signal TBBK0 output from the bank decoder 19 becomes H level.

This H level corresponds to the clock signal AD2LAC.
It is held until the falling timing of LK. That is, the second erase bank selection signal TB which is different bank information.
It indicates that BK0 = H level is held by the clock signal AD2LACLK.

Then, the command code 30h is inputted from the command signal DQi through the I / O buffer 12,
Chip enable signal CE / write enable signal WE
Whichever comes first, that is, the clock signal TWE output from the control buffer 11
= Command control circuit 15 in synchronization with the L level
It is output from a to the command controller 21.

On the other hand, in the bank comparison circuit 7, the first erase bank selection signal TABKi is compared with the second erase bank selection signal TBBKi. Here, if the banks are the same, that is, TABK0 = 1 and TBBK0 = 1. Therefore, the comparison result becomes the L level, and the judgment result information TCOM
Output P = L level.

Judgment result information TC from the bank comparison circuit 7
When the command controller 21 receives the OMP = L level, the erase function start signal LACLK, which is the same bank information, is sent.
= H level is output to the sector latch circuit 22.

Referring again to FIG. 2, the erase function start signal BK which is different bank information from the command controller 21.
In the sector latch circuit 22 receiving LACLK = L level, all the n-channel type MOS transistors N30 to N3n are turned off.

On the other hand, all the n-channel type MOS transistors N0 to N1n receiving the erase function start signal LACLK = H level from the command controller 21 are rendered conductive.

N-channel type MOS transistor N20-
N2n is also TS of the sector selection information TSA0 to TSAi
Upon receiving A0 = H level, the n-channel MOS transistor N20 becomes conductive, and its common connection contact A has L
The level is output.

This L level is inverted in polarity and becomes H level and is latched, so that one sector in the bank including the sector to be erased is held in the sector latch circuit as an erased sector, and the held H level and internal address. The sector selection information ISA0 to be selected is individually compared by the exclusive OR circuit 240, and the H level of the erase sector information LASA0 that indicates the sector erase is output as a coincidence signal.

Further, the H level of the sector selection information ISA0 selected via the selector decoder 17 and the erase sector information LA are selected by the address generated by the internal address.
The H level of SA0 is compared by the exclusive OR circuit 240.

As a result of comparison, since both match at the H level, it is judged that the sector selected by the internal address is the sector to be erased, and the erase operation is performed to that sector.

Next, the clock signal AD1 which becomes L level
The sector selection information TSA0 becomes L level in synchronization with the fall timing of LACLK.

Further, when erasing a plurality of sectors, 30h of the sixth cycle and the addresses SA1 to SAi of the sectors to be erased are sequentially input and the sector selection information TSA1 to SAi to be erased is held.

In the first embodiment described above, the sixth cycle of the sector erase function command cycle is divided into the first half cycle and the second half cycle, and within the address hold time of the sixth cycle, different bank addresses are used in the first half and the second half. In the case of specifying, the command controller 21 outputs a holding pulse of the erase function start signal BKLACLK, which is different bank information, and all the sector information included in the designated bank is collectively held in the sector latch circuit 22 as an erase sector. Therefore, the sector erasing function can specify not only the erasing of only one sector but also the erasing sectors of all the sectors in a bank unit, and the command input time can be shortened.

For example, when it is desired to erase one bank, the erase command has conventionally required 16 cycles, but if this embodiment is applied, the erase command can be erased in one cycle.

Next, a method of erasing stored data in a flash memory to which the above-mentioned embodiment is applied will be described. Referring to FIG. 4, which is a flow chart for explaining a method of erasing stored data in a flash memory, first, in step S11, a sector erasing operation of a flash memory cell array is sequentially executed by first to nth commands in an n cycle period, and Within the address hold time at the time of executing the nth command, the bank decoder 18 holds the decode information of the first erase address (for example, Ai = 555h) given in the first half of the nth cycle period.

Next, in step S12, the decode information of the second erase address (for example, Ai = 2AAh) given in the latter half of the nth cycle period is transferred to the bank decoder 1.
Hold at 9.

In step S13, the first held
Then, the bank comparison circuit 20 compares the decode information of the second erase addresses 555h and 2AAh to specify the same bank.

In step S14, when the comparison result in the bank comparison circuit 20 specifies the same bank, it is determined that one sector in the bank is erased, and when different banks are specified, all the banks in the bank are erased. Judge as batch erase of sectors.

In step S15, step S14
Based on the result of the judgment in step 1, the erase of one sector in the specified bank of the flash memory cells is executed, or the flash memory cells are collectively erased in the specified bank unit.

According to the method described above, the sixth cycle of the sector erase function command cycle is divided into the first half cycle and the second half cycle, and different bank addresses are designated in the first half and the second half within the address hold time of the sixth cycle. With the sector erasing function, not only erasing of only one sector can be designated, but also erasing sectors of all sectors can be designated in a bank unit, and command input time can be shortened.

Next, a second embodiment of the present invention will be described.

Referring to FIG. 5, which is a block diagram of the second embodiment, the flash memory 1 includes a control buffer 11, an I / O buffer 12, and an address buffer 1.
3, a command address decoder 14, a command control circuit 15a, an internal address generation circuit 16,
It includes a sector decoder 17, a bank decoder 18, a sector latch circuit 22, and a command pulse generation circuit 23.

That is, the difference from the first embodiment is that
A command pulse generation circuit 23 is provided in place of the command controller 21 in the first embodiment. Further, the command control circuit 15b outputs notification signals T50 and T30 corresponding to, for example, the command 50h and the command 30h to the command pulse generation circuit 23 as the erase function start signal.

Further, the sector latch circuit 22 has the same circuit configuration as that of FIG. 3 described above, and includes sector selection information TSAi / ISAi to be erased from the sector decoder 17 and a first erase bank selection signal TAB from the bank decoder 18.
Ki and the erase function start signal BKLACLK from the command pulse generation circuit 23 in place of the command controller 21.
Is input.

In this embodiment, in the erase command, in the case of batch latching in bank units, the command code 50h is input to the command signal DQi, the command control circuit 15b recognizes the command code 50h, and the command pulse generating circuit 23 receives the command code 50h. The notification signal T50 is a signal for notifying that it is a batch latch in bank units. Command signal DQ when latching in sector units
The notification signal T30 is a signal that inputs the command code 30h to i, the command control circuit 15b recognizes the command code 30h, and notifies the command pulse generation circuit 23 that the latch is a sector unit.

Referring also to FIG. 6 showing the timing chart for explaining the operation of the second embodiment, the chip enable signal CE / write is executed at the sixth command after the fifth cycle of the sector erase function command is established. After inputting an address to be erased (for example, SA0) to the address signal Ai in synchronization with the slower falling timing of the enable signal WE, the erase sector is selected via the address buffer 13 and the sector decoder 17, and the sector decoder 17 The outputted sector selection information TSA0 to be erased becomes H level, and the sector selection information is held in synchronization with the clock signal AD1LACLK. Further, the first erase bank selection signal TABK0 = H level is input from the bank decoder 18.

On the other hand, the command code 50h is input from the DQi via the I / O buffer 12, and the clock signal TWE determined by the rising edge timing of the chip enable signal CE / write enable signal WE, whichever is earlier.
= Command control circuit 15 in synchronization with the L level
It is taken in and held in b.

The command control circuit 15b outputs the fetched command code 50h to the command pulse generation circuit 23 as a notification signal T50. In the command pulse generation circuit 23, the notification signal T50 is judged,
When recognizing that T50, the erase function start signal BKLACLK for holding all the banks collectively is output as the H level.

In the sector latch circuit 22 which has received one pulse of the erase function start signal BKLACLK = H level, all the n-channel type MOS transistors N30 to N3n become conductive, and the n-channel type MOS transistors N40 to N40-.
Similarly to the first embodiment, N4n also becomes conductive when receiving the first erase bank selection signal TABK0 = H level, and L level is output to each common connection contact A.

Since the L level of the common connection contact A is inverted to the H level and latched, all the sectors in the bank including the sector to be erased are held in the sector latch circuit as erased sectors.

The held H level and the sector selection information ISA0 to ISAi by the internal address are individually compared by the exclusive OR circuits 240 to 24n, and the H level indicating the sector erase of each of the erase sector information LASAi to LASAi + 7 is obtained. It is output as a coincidence signal.

On the other hand, when the command code 30h is input in the sixth cycle as in the conventional case, the command code 30h is input from the command signal DQi via the I / O buffer 12, and either the chip enable signal CE or the write enable signal WE is input. The signal is fetched and held in the command control circuit 15b in synchronization with the clock signal TWE = H level which is determined by the later falling timing.

The command control circuit 15b outputs the fetched command code 30h to the command pulse generation circuit 23 as a notification signal T30. In the command pulse generation circuit 23, the notification signal T30 is judged,
When recognizing that T30, the erase function start signal LACLK for holding one sector is output as the LACLK = H level.

In the sector latch circuit 22 which has received one pulse of the erase function start signal LACLK = H level serving as one sector selection information and has received the erase function start signal BKLACLK = L level, the n channel is set by the erase function start signal BKLACLK = L level. Type MOS transistors N30 to N3
All n are non-conductive.

On the other hand, from the command controller 21 to LA
Upon receiving CLK = L level, all n-channel type MOS transistors N0 to N1n are rendered conductive.

N-channel type MOS transistor N20-
N2n also receives TSA0 = H level of signals TSA0 to TSAi, n channel type MOS transistor N20 becomes conductive, and L level is output to common connection contact A thereof.

This L level is inverted in polarity and becomes H level and is latched, so that one sector in the bank including the sector to be erased is held in the sector latch circuit 24 as an erase sector, and the held H level and internal address. ISA0 is individually compared by the exclusive OR circuit 240, and the H level indicating the sector erase of the erase sector information LASA0 is output as a coincidence signal.

In the above-described second embodiment, as an example, it is possible to determine the bank batch erase or the one-sector erase by the command code 50h and the command code 30h. Therefore, the bank decoder as in the first embodiment is used. Provided is a flash memory which can reduce the chip area without requiring the bank comparison circuit 20, the bank comparison circuit 20, and the command controller 21.

Further, as in the first embodiment, the sector erase function can specify not only erase of one sector but also erase sectors of all sectors in a bank unit, and command input time can be shortened. .

[0144]

As described above, according to the flash memory and the stored data erasing method of the present invention, the sixth cycle of the sector erase function command cycle is divided into the first half cycle and the second half cycle, and the address hold of the sixth cycle is performed. When different bank addresses are designated in the first half and the second half within the time, the holding pulse of the erase function start signal BKLACLK is output from the command controller 21, and all the sector information included in the designated bank is erased in the sector latch circuit 22. The sector erasing function can designate not only the erasing designation of only one sector but also the erasing sectors of all the sectors in a bank unit, and the command input time can be shortened.

Also, a first command code (example 50h) and a second command code (example 30h) designated in advance are used.
Since it is possible to determine whether the bank is collectively erased or one sector is erased, there is no need for a bank decoder means for obtaining different erased bank information and a bank comparison means for determining whether the bank is the same bank or different banks. Provide a flash memory that can reduce the chip area only.

[Brief description of drawings]

FIG. 1 is a configuration diagram of main parts of a first embodiment of a flash memory of the present invention.

FIG. 2 is a circuit diagram of a sector latch circuit 22.

FIG. 3 is a timing chart for explaining the operation of the first embodiment.

FIG. 4 is a flowchart illustrating a stored data erasing method according to the first embodiment of the present invention.

FIG. 5 is a configuration diagram of a second embodiment.

FIG. 6 is a timing chart for explaining the operation of the second embodiment.

FIG. 7 is a diagram showing a configuration example of a conventional flash memory.

FIG. 8 is a circuit diagram of a conventional sector latch circuit 24.

FIG. 9 is a command timing chart for explaining the operation of the conventional sector erase function.

FIG. 10 is a flowchart of a sector erase function.

[Explanation of symbols]

11 Control Buffer 12 I / O Buffer 13 Address Buffer 14 Command Address Decoder 15a, 15b, 15c Command Control Circuit 16 Internal Address Generation Circuit 17 Sector Decoder 18, 19 Bank Decoder 20 Bank Comparison Circuit 21 Command Controller 22, 24 Sector Latch Circuit 23 Command , P1n, P20 p-channel MOS transistors N10, ..., N1n, N20, ..., N2n, N30,
..., N3n, N40, ..., N4n, N50, N60
N channel type MOS transistors 220, ..., 22n, 230, ..., 23n, 250, 2
60 inverters 240, ..., 24n, 270 exclusive OR circuit TABKi first erase bank selection signal TBBKi second erase bank selection signal TWE, AD1LACLK, AD1LACLK clock signal ISAi, TSAi sector selection information BKLACLK, LACLK erase function start signal DQi command signal Ai address signal TCOMP judgment result information LASAi erase sector information

Claims (15)

[Claims] 1. A sector erasing operation of a flash memory cell array is sequentially executed by first to nth commands in an n cycle period, and in the first half of the nth cycle period within an address hold time when the nth command is executed. It holds the decode information of the given first erase address, and further holds the decode information of the second erase address given in the latter half of the n-th cycle period.
A flash memory having a function of comparing whether the held data code of the first and second erase addresses designates the same bank. 2. When the result of the comparison specifies the same bank, it is determined that one sector in the bank is erased, and when different banks are specified, all sectors in the bank are collectively erased. A erasure judgment function for judging is provided.
Flash memory as described. 3. An erase sector information holding function for holding the batch erase sector information of all the sectors in the bank specified by the first erase address and the bank information specified by the second erase address. The flash memory according to claim 1. 4. When a sector erase function command of a flash memory cell is input, a first command code for holding sector information to be erased in sector units is input and retained as an erase sector of only one sector, and a bank A flash memory having a sector erasing function of inputting a second command code to be held collectively in units and holding all sectors in a bank as erase sectors. 5. An erase sector address is input in two cycles within an address hold time when a sector erase command of a flash memory cell is executed, and the first cycle is used as an erase sector and bank information including the erase sector. Hold and hold the second cycle as other erase bank information, and specify the same bank or a different bank according to the comparison result of the bank information including these erase sectors and other erase bank information. The flash memory has a function of recognizing whether or not the same bank is designated, and determining that the sector is erased if the same bank is designated, and determining that the bank is erased if different banks are designated. 6. The erase sector address is set to 2 in one cycle.
6. The flash memory according to claim 1, wherein the flash memory has a function of collectively erasing all the sectors in one bank in one command cycle by giving the divided data. 7. The means for holding as bank information including the erase sector generates and generates an erase bank selection signal including the erase sector in accordance with an address designating the erase sector in the first cycle. 7. The flash memory according to claim 6, which is first bank decoder means for latching the selection signal with a first clock signal synchronized with a chip enable or write enable signal. 8. The means for holding as the other bank information generates a selection signal of an erase bank including the erase sector according to an address designating an erase sector in the second cycle, and the generated selection. 7. The flash memory according to claim 6, which is a second bank decoder means for latching a signal with a second clock signal synchronized with the chip enable or write enable signal. 9. The means for recognizing whether the same bank is designated or the different bank is designated is determined from sector latch function command completion information and the comparison result information whether it is a sector latch or a bank latch. 7. The flash memory according to claim 6, wherein the flash memory is command control means for outputting a pulse signal as a result of the determination. 10. In order to function to judge the sector erase or the bank erase, the information indicating the same bank or a different bank for performing the erase at the erase command is latched and the latched sector is latched. The information is compared with the sector information selected via the sector decoder based on the address generated by the internal address generation means after the start of the erase function, and if they match, the sector selected by the internal address is determined to be the sector to be erased. 7. The flash memory according to claim 6, further comprising first sector latch means for judging, performing an erasing operation on the sector, and outputting a next sector address as the internal address to judge whether the sector address matches or does not match when the comparison result is different. . 11. When recognizing a given command signal to function as the sector erase and latching in sector units, it is output in the first code that the latch is in sector units, and in bank units. In the case of batch latching by the command control means for outputting the batch latch in bank units with the second code, and the first and second corresponding to the first and second codes respectively. And a second pulse latch for outputting a sector erase control signal by comparing the first and second latch pulses with sector selection information obtained by decoding the sector address to be erased. The flash memory according to claim 4, further comprising: 12. The second sector latch means connects a first p-channel MOS transistor, a first n-channel MOS transistor and a second n-channel MOS transistor in series between a power supply potential and a ground potential. Signal is supplied to the gate of the first p-channel MOS transistor at the ground potential during the erasing period, and the gate of the first n-channel MOS transistor is supplied with the batch-in-bank erase sector information. Erase sector selection information based on the first erase address is applied to the gate of the n-channel MOS transistor, and between the series connection point of the first p-channel MOS transistor and the first n-channel MOS transistor and the ground potential. A third n-channel MOS transistor and a fourth n-channel MOS transistor Insert and connect in series connection,
Erase bank information is given to the gate of the third n-channel MOS transistor, sector selection information based on the internal address is given to the gate of the fourth n-channel MOS transistor, and the first and second portions are connected to the series connection point. Of each of the inverters is connected to the other input terminal of the latch, the output terminal of the latch is connected to one input terminal of the exclusive OR circuit, and the other input terminal is based on the internal address. 12. The flash memory according to claim 11, wherein one set of configurations for inputting sector selection information is provided for the number of sector addresses, and sets for the number of sector addresses are provided for the number of banks. 13. The erase sector address is applied to the address buffer in two cycles within the address hold time when the sector erase command of the flash memory cell is executed, and the first cycle includes the erase sector and bank information including the erase sector. And the second cycle is held as other erase bank information, and the same bank is designated or different depending on the comparison result of the held bank information including the erase sector and the other erase bank information. A method of erasing stored data in a flash memory, which recognizes whether or not a bank is designated, and erases sectors if the same bank is designated, and erases banks if different banks are designated. 14. A batch erase operation for all sectors in one bank is performed.
13. The method for erasing data stored in a flash memory according to claim 12, which is executed in a command cycle. 15. A sector erase operation of a flash memory cell array is sequentially executed by first to nth commands in an n cycle period, and within an address hold time at the time of executing the nth command, in the first half of the nth cycle period. The decode information of the given first erase address is set to the first
Holding the decoded information of the second erase address given in the latter half of the n-th cycle period in the second bank decoder, and holding the held first and second A comparison circuit compares whether the decode information of the erase address specifies the same bank, and when the result of the comparison specifies the same bank, it is judged that one sector in the bank is erased, and different banks are selected. A method for erasing stored data in a flash memory, comprising: erasing all the sectors in the bank when specified, and erasing the flash memory cell based on the determination.