JP2003036176A - Interruption processing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an interruption processing system capable of avoiding performance deterioration also with respect to processing in which the flow of control changes at an unpredictable time such as interruption processing. SOLUTION: The interruption processing system is provided with an interruption processing program 6 for executing the program of interruption processing in a computer system, a polling processing part 2 which inspects the occurrence of an interruption request by polling anywhere in an optional program and starts the program 6 when detecting the occurrence of the interruption request, an ordinary interruption processing part 7 for starting the interruption processing program by ordinary interruption processing based on the occurrence of the interruption request, a delay processing part which delays the ordinary interruption processing by the processing part 7 by a prescribed time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interrupt processing system suitable for application to, for example, an operating system (OS).

[0002]

2. Description of the Related Art Generally, a computer system sends an interrupt request to a processor when an event requiring software intervention occurs in peripheral hardware, thereby executing a program currently being executed. It was common to have a mechanism for interrupting the interrupt and starting the interrupt processing program.

On the other hand, recent processors have dramatically improved their performance by adopting the following mechanism. First, a pipeline structure including a large number of stages was provided. Secondly, a cache memory is provided. Thirdly, a large number of registers are provided. Fourth, the branch prediction mechanism was provided.

In such a conventional method, the processor detects the generation of an interrupt processing request, and in response to this, the operating system saves the current state of the processor and then starts the interrupt processing program. When the interrupt processing is completed, the saved state is restored to restart the processing interrupted by the interrupt.

[0005]

The above-mentioned conventional mechanism has a disadvantage that the performance is relatively low for processing such as interrupt processing in which the control flow changes at an unpredictable time.

Further, in a faster communication mechanism such as a so-called Gigabit Ethernet (registered trademark) which can generate an interrupt every 12 μsec, interrupt requests are generated very frequently. For example, if a 1500-byte packet is received at a communication speed of 1 Gbps, one packet will be received every 12 microseconds. If a general hardware configuration in which an interrupt is generated every packet reception is adopted, it becomes necessary to perform interrupt processing every 12 microseconds, which makes it difficult to handle such high-speed interrupts. It was

Further, in a system such as a set-top box that needs to store a large number of interrupt sources inside, the time spent for interrupt processing tends to be high in the total processing time. There was an inconvenience.

If the interrupt generation interval can be predicted, this problem can be solved by polling the timer device by the operating system. (Reference: Mohit Aron and P
eter Druschel, "Soft Timer
s Efficient MicrosecondSo
ftware timer support for
Network Processing, “ACMT
transaction on Computer Sy
stems, vol. 18, No. 3, August
2000. )

However, there is a disadvantage that such a method cannot be applied to an interrupt generation source whose interrupt generation interval cannot be predicted in advance. In the conventional mechanism described above, in the pipeline structure including the first large number of stages, processing in the middle of interruption is wasted. Specifically, in general, the processor has to wait until the intermediate results of the instruction execution left in the pipeline are cleared or discard them before starting or ending the interrupt processing. As a result, the operating rate of each stage in the pipeline is reduced, and as a result, the performance of the processor is reduced.

Further, in the second cache memory, the performance is deteriorated after the process is restored at the time of interruption. Specifically, by executing the interrupt processing program, the cache memory of the processor is rewritten with contents unrelated to the program interrupted by the interrupt. Therefore, when returning from the interrupt processing, there is a disadvantage that the execution efficiency of the interrupted program is reduced.

Further, in the third large number of registers, the number of processes for storing the state of the processor increases. Specifically, today's microprocessors have numerous registers. Therefore, there is an inconvenience that a lot of time is spent on the process of saving or restoring these.

Further, in the fourth branch prediction mechanism, the prediction immediately after the interruption is likely to be missed. Specifically, in the case of a processor equipped with a branch prediction mechanism, the content of the branch prediction buffer is updated by the execution of the interrupt processing program, and the occurrence rate of branch prediction errors increases after returning from the interrupt processing, resulting in poor performance. There was an inconvenience.

Therefore, the present invention has been made in view of the above point, and it is possible to prevent the performance from deteriorating even for a process such as an interrupt process in which the control flow changes at an unpredictable point in time. An object of the present invention is to provide an interrupt processing system capable of performing the above.

[0014]

An interrupt processing system according to the present invention is an interrupt processing system for executing interrupt processing in a computer system, and an interrupt processing program execution unit for executing an interrupt processing program in the computer system, and an optional computer system. The polling processing unit that checks the generation of interrupt requests by polling everywhere in the program and activates the interrupt processing program when the interrupt request generation is detected, and the interrupt processing program by the normal interrupt processing based on the interrupt request generation. And a delay processing unit for delaying the normal interrupt processing by the normal interrupt processing unit by a predetermined time.

Therefore, according to the present invention, the following operations are performed. The inspection determination unit of the polling processing unit determines when the operating system performs a predetermined process, and the inspection unit of the polling processing unit inspects the interrupt request. Such polling processing reduces processing overhead.

In addition to the polling processing unit, a delay processing unit that intentionally delays the time from the generation of the interrupt request to the arrival of the interrupt request input in the processor is also used.

Thus, while maintaining the overhead reduction effect of the polling processing unit, the delay processing unit guarantees that the detection of the interrupt request generation is not delayed for a certain time or more.

At the time of the determination by the inspection determination unit of the polling processing unit, the inspection unit inspects the interrupt request. When the inspection by this inspection department is not performed frequently enough,
That is, when the delayed interrupt request input reaches the processor, the interrupt processing program is activated by the normal interrupt processing unit. The maximum interrupt response time is the time obtained by adding the interrupt response time in the normal system to this delay time.

Since the interrupt request signal can be delayed by using the delay processing section for delaying all the interrupt requests, the polling processing section starts the interrupt processing while guaranteeing the maximum interrupt response time of the system. The probability of can be increased.

Further, the interrupt processing system of the present invention is
In an interrupt processing system that performs timer interrupt processing in a computer system, a timer interrupt processing program execution unit that executes a program for timer interrupt processing in the computer system, and an inspection for the occurrence of interrupt requests by polling everywhere in any program of the computer system. A polling processing unit that activates the timer interrupt processing program when a timer interrupt request generation is detected; a timer interrupt processing unit that activates the timer interrupt processing program by normal interrupt processing based on the timer interrupt request generation; And a delay processing unit for delaying the timer interrupt processing by the interrupt processing unit by a predetermined time.

Therefore, according to the present invention, the following operations are performed. In the setting timer list of the delay processing unit, timer waiting information is prepared for each timer that has not reached the set time after the setting. The timer wait information constitutes a bidirectional linked list.

The timer wait information of the delay processing section has a timer setting time, an allowable delay time, and a procedure pointer.

For the set timer list of the delay processing section,
The timer wait information is arranged in ascending order of the timer set time. The procedure pointer is a pointer that indicates a procedure to be called after a set time has elapsed.

After the elapse of the timer set time of the timer wait information, the procedure pointer gives an instruction to call the procedure of the timer wait information of the timer set time for which the set time has not yet passed.

As a result, the polling processing unit checks the set timer list for the occurrence of the time out of the timer in the timer wait information, and while obtaining the overhead reduction effect, the timer is set for the set timer list for a certain time or more. Guarantee that the timer detection of wait information is not delayed.

That is, due to the allowable delay time of the timer wait information with respect to the timer setting time, the timer interrupt processing unit causes the timer interrupt processing unit to notify the timer interrupt processing program at a time later than the timer setting time within a range not exceeding the maximum value of the timer response time. Set the set timer list to generate an interrupt.

Thus, the polling processing unit can detect that the timer setting time of the timer waiting information has reached the setting timer list before the timer interrupt processing unit generates an interrupt for the timer interrupt processing program. Improve sex.

[0028]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below. The interrupt processing system of the present embodiment reduces the overhead generated by interrupt processing by combining the interrupt request signal polling mechanism by the operating system and the mechanism that intentionally delays the interrupt response time of the processor for the interrupt request signal. To do.

FIG. 1 is a diagram showing a hardware configuration of an interrupt request mechanism in the case of uniformly delaying all interrupt requests applied to this embodiment. In the conventional mechanism described above, the pipeline structure including the first multiple stages reduces the performance of the processor, and the third multiple registers saves or restores them, which requires a lot of time. The inconvenience of spending is a problem that occurs because interrupt processing is started at a time point that cannot be predicted in advance.

Therefore, as shown in FIG. 1, in the program executed in the operating system (OS) 1, the interrupt request signal IR1,
IR2 ... IRn is input, the occurrence of an interrupt request in the interrupt request register 9 is inspected, and the polling processing unit 2 that calls the interrupt processing program 6 by the activation unit 5 is embedded as necessary, thereby solving the above-mentioned problem. can do.

The problem here is in which program and at which position this code is embedded. In order for this polling process to be effective, it is necessary to insert an interrupt request inspection code at a location that is executed at a sufficiently high frequency.

Further, in order to prevent the cache memory hit rate and branch prediction efficiency of an application program from deteriorating, a certain program (for example, not limited to an application program, but may be operating system software) may be changed to another application. It is desirable to perform the inspection immediately before the control is transferred to the program or at a place where it is unlikely that the application program will be continuously executed.

By performing the inspection at such a position, among the above-mentioned problems, the inconvenience that the execution efficiency of the interrupted program is lowered when returning from the interrupt processing by the second cache memory, and The content of the branch prediction buffer is updated by the execution of the interrupt processing program by the branch prediction mechanism of No. 4, and the occurrence rate of branch prediction errors increases after returning from the interrupt processing, so that the inconvenience of performance degradation can be solved. .

Therefore, the inspection determination unit 3 of the polling processing unit 2 determines when the operating system performs the following processing, and the inspection unit 4 of the polling processing unit 2 inspects the interrupt request.

First, it is performed immediately before the end of the system call processing. Here, the system call means that a user or an application program uses an input / output routine or the like incorporated in the operating system.

Second, it is performed immediately before the end of the exception processing, for example, immediately before the end of the memory protection exception processing. Third, it is performed when the CPU is in the idling state where no program is executed.

In the above-mentioned first, second and third cases, since the compiler allocates registers, the number of registers to be restored can be reduced to about half.

It has been reported in the above-mentioned reference that these processes are executed frequently enough for the purpose of this embodiment. By such polling processing, it is possible to reduce the processing overhead described above.

However, it is often necessary to guarantee the maximum value of the interrupt response time. In such a case, the polling processing unit 2 by the operating system (OS) 1 alone is insufficient. Although it is not necessary to guarantee the maximum value, an increase in response time often leads to deterioration of performance.

Therefore, in the present embodiment, in addition to the polling processing unit 2 described above, there is a delay function that intentionally delays the time from the generation of an interrupt request to the arrival of the interrupt request input IRi at the processor 14. We propose to use the interrupt request mechanism together.

As a result, while maintaining the effect of reducing the overhead by the polling processing unit 2, it is possible to guarantee that the detection of the interrupt request generation will not be delayed for a certain period of time or longer.

First and second by the above-mentioned inspection time determination unit 3
And at the time of the third judgment, the inspection unit 4 inspects the interrupt request. When the inspection by the inspection unit 4 is not performed sufficiently frequently, that is, when the delayed interrupt request input IRi reaches the processor 14, the normal interrupt processing unit 7 activates the interrupt processing program 6. Will be.

The interrupt request mechanism having the delay function will be described below. Interrupt request signals IR1, IR
2, ... IRn are signals that become high level H (or 1) when a certain interrupt generation source requests interrupt processing.

The interrupt request register 9 stores the interrupt request currently generated by the operating system (O
S) 1 is a register that can be read by the inspection unit 4 of the polling processing unit 2.

The interrupt in-service register 10 is connected to the processor 1 via the AND circuit 11 and the OR circuit 12.
4 is a register for transmitting the interrupt request input IRi to 4 and can be read by the inspection unit 4 of the polling processing unit 2 in the operating system (OS) 1.

In the rising delay circuit 13, the input signal is low level L (or 0) to high level H (or 1).
After a certain period of time has passed after the
(Or 1), and when the input signal changes from the high level H (or 1) to the low level L (or 0), the output is immediately changed to the low level L (or 0).

The maximum interrupt response time is the sum of this delay time and the interrupt response time in a normal system. Specifically, for example, when the maximum response time to be guaranteed in the system specifications is 500 μsec, 490 μsec obtained by subtracting 10 μsec required for the interrupt processing by the operating system (OS) 1 is set as the delay time.

The variable setting section 8 sets the rising delay circuit 13 so that the delay time can be changed by software. Here, there is also a system including an interrupt generation source that imposes a strict requirement on the interrupt request time. In order to deal with such a case, the delay time can be set to zero.

Since the logical sum of all interrupt request signals can be uniformly delayed by using the interrupt request mechanism for uniformly delaying all interrupt requests, the maximum interrupt response time of the system is guaranteed. At the same time, it is possible to increase the probability of activating the interrupt processing by the polling processing unit 2.

FIG. 2 is a diagram showing the hardware structure of the interrupt request mechanism when the delay time is changed for each interrupt generation source. Here, the same configurations as those in FIG. 1 are denoted by the same reference numerals, the description thereof will be omitted, and only different configurations will be described.

The interrupt mask register 15 is a register for limiting the transmission of the interrupt request input IRi to the processor 14 via the AND circuit 11 and the OR circuit 12, and the polling processing unit in the operating system (OS) 1. The inspection unit 4 of 2 is a readable / writable register.

The rising delay circuit 13 is set by changing the delay time for each interrupt generation source, and a certain period of time elapses after the input signal changes from the low level L (or 0) to the high level H (or 1). The output will be high level H later
(Or 1), and when the input signal changes from the high level H (or 1) to the low level L (or 0), the output is immediately changed to the low level L (or 0).

In FIG. 2, the rising delay circuit 13
-1, 13-2 ... 13-n delay the delay time different for each interrupt generation source, and then the OR circuit 12 takes the logical sum of them.

By using the interrupt request mechanism for changing the delay time for each interrupt generation source, it is possible to select and delay the optimum delay time for each interrupt generation source. It is possible to increase the probability of starting the interrupt processing by the polling processing unit 2 while guaranteeing the interrupt response time and the optimum delay time for each interrupt generation source.

The interrupt request mechanism shown in FIG. 1 for uniformly delaying all interrupt requests has a hardware scale larger than that of the interrupt request mechanism shown in FIG. 2 for changing the delay time for each interrupt source. There is an effect that can be reduced.

On the other hand, the interrupt request mechanism shown in FIG. 2 for changing the delay time for each interrupt source has an effect that an optimum delay time can be set for each interrupt source. .

Not limited to this, the interrupt request mechanism shown in FIG. 1 for uniformly delaying all interrupt requests, and the interrupt request mechanism shown in FIG. 2 for changing the delay time for each interrupt source. It is also possible to apply in combination with.

That is, as for some of the interrupt generation sources, as shown in FIG. 1, the OR circuit 12 logically sums them and then the rising delay circuits 13-1, 13-2, ...
3-n, the other interrupt sources are individually delayed by the rising delay circuits 13-1, 13-2, ... 13-n as shown in FIG. You may comprise so that the logical sum may be taken.

As described above, according to the present embodiment, the following effects of reducing performance degradation can be obtained. First, it is possible to reduce the consumption of a lot of time required for the process of saving or restoring the states of a large number of registers at the start or end of the interrupt process.

Before starting or ending the interrupt processing, the pipeline is waited until the intermediate results of the instruction execution left in the pipeline consisting of a number of stages are swept or discarded. It is possible to reduce the deterioration of the operation rate of each stage in the inside, and consequently, the deterioration of the performance of the processor.

Further, the cache memory due to the execution of the interrupt processing program is rewritten to a content irrelevant to the program interrupted by the interrupt, so that the execution efficiency of the program interrupted when returning from the interrupt processing is lowered. It can be reduced.

Further, the contents of the branch prediction buffer are updated by the execution of the interrupt processing program, and it is possible to reduce the performance degradation due to the increased occurrence rate of branch prediction errors after returning from the interrupt processing.

Next, another interrupt processing system of this embodiment will be described. The other interrupt processing system of the present embodiment uses a timer interrupt processing by combining a polling processing unit that checks whether the timer has expired by the operating system and a data structure that intentionally delays the generation of the timer interrupt. It reduces the overhead that occurs.

FIG. 3 is a diagram showing a data structure of an interrupt request when the timer interrupt is delayed. In FIG. 3, the polling processing unit 2 is the same as that shown in FIGS.
The description is omitted because it is the same as that shown in FIG.
In the set timer list 31, the timer wait information 32-1 is set for each timer that has not reached the set time after setting.
32-2, 32-3 ... Are prepared. These timer wait information 32-1, 32-2, 32-3 ...
Make up a two-way linked list.

The timer wait information 32-1 has a timer set time 32-1-1, an allowable delay time 32-1-2, and a procedure pointer 32-1-3. Further, the timer wait information 32-2 includes a timer setting time 32-2-1, an allowable delay time 32-2-2, and a procedure pointer 32-2-3.
have. Further, the timer wait information 32-3 includes timer set time 32-3-1, allowable delay time 32-3-2,
It has a procedure pointer 32-3-3.

With respect to the set timer list 31, the timer waiting information 32-1, 32-2, 32-3, ... Includes timer set time 32-1-1, timer set time 32-2-1,
The timer set times 32-3-1 ... Are arranged in order from the shortest one. Procedure pointer 32-1-3, procedure pointer 32-2-3, procedure pointer 32-3-3
Is a pointer that indicates a procedure to be called after the elapse of the set time.

Specifically, after the timer set time 32-1-1 of the timer wait information 32-1 has elapsed, the timer wait information 32-2 of the timer set time 32-2-1 that has not yet passed the set time is displayed. The procedure pointer 32-2-3 gives an instruction to call the procedure. At this time, the timer wait information 32-
Instead of 1, the timer wait information 32-2 is rearranged to the front row.

Also, after the timer setting time 32-2-1 of the timer waiting information 32-2 has passed, the timer waiting information 3 of the timer setting time 32-3-1 that has not yet passed the setting time
The procedure pointer 32-3-3 instructs the procedure 2-3 to be called. At this time, the timer wait information 32-2 is rearranged in place of the timer wait information 32-2.

As a result, the polling processing unit 2 causes the timer waiting information 32-
The timer waiting information 32-1 is set to the set timer list 31 for a certain time or more while obtaining the overhead reduction effect by inspecting the occurrence of the time out of the timers 1, 32-2, 32-3 ,. It can be guaranteed that the timer detections of 32-2, 32-3, ... Are not delayed.

That is, the timer wait information 32-1 and 32
-32, 32-3 ... Timer setting time 32-1-1,
Range that does not exceed the maximum value of the timer response time due to the allowable delay times 32-1-2, 32-2-2, 32-3-2, ... For 32-2-1, 32-3-1, ... Then, the timer set times 32-1-1, 32-2-1, 32-3-1
... The setting timer list 31 is set so that the timer interrupt processing unit 34 causes an interrupt to the timer interrupt processing program 33 at a later time.

As a result, the timer interrupt processing unit 34
Before the interrupt is generated for the timer interrupt processing program 33 by the polling processing unit 2, the wait processing information 32-1, 32 for the set timer list 31
-32, 32-3 ... Timer setting time 32-1-1,
It is possible to increase the possibility that it is detected that 32-2-1, 32-3-1 ...

FIG. 4 is a flow chart showing the procedure of timer registration processing. The timer registration process of FIG. 4 is performed when an application program in the operating system (OS) 1 newly registers a timer, such as timer wait information 32-1, 32-2, 32-3 for the set timer list 31. It shows an operation.

In FIG. 4, in step S1, it is determined whether or not the current time is smaller than the timer set time. If the current time is smaller than the timer set time in step S1,
In step S2, an area for timer waiting information is allocated. In step S3, the timer waiting information is initialized.

In step S4, it is inserted into the set timer list. In step S5, it is determined whether or not it has been inserted at the beginning. When it is inserted at the beginning in step S5, the process proceeds to step S6, and in step S6, the timer hardware is set so as to generate an interrupt at the set time + the allowable delay time, and the timer registration process is completed.

If the current time is smaller than the timer set time in step S1, the process proceeds to step S7 and step S7.
Then, the procedure that should be called after the lapse of the set time is called to complete the timer registration processing.

FIG. 5 is a flowchart showing the procedure of polling processing. The polling process of FIG. 5 shows an operation when the polling processing unit 2 in the operating system (OS) 1 inspects the set timer list 31 for the occurrence of a timer expiration.

In FIG. 5, in step S11, it is determined whether the set timer list is empty. If the set timer list is not empty in step S11, the process proceeds to step S12, and it is determined in step S12 whether or not the timer set time of the leading timer wait information has been reached.

When the timer setting time of the head timer waiting information is reached in step S12, the process proceeds to step S13, and the head timer waiting information is removed in step S13.

In step S14, a procedure to be called after the lapse of the set time is called, the process returns to step S11, and the judgments and processes of steps S11 to S14 are repeated. Then, if the set timer list is empty in step S11, the polling process is completed.

FIG. 6 is a flow chart showing the procedure of timer interrupt processing. The timer interrupt process of FIG.
The operation when the timer interrupt processing unit 34 in the operating system (OS) 1 performs timer interrupt processing on the set timer list 31 is shown.

In FIG. 6, in step S21, the leading timer wait information is removed. In step S22, a procedure to be called after the set time has elapsed is called. Step S
At 23, it is determined whether the set timer list is empty. If the set timer list is not empty in step S23, the process proceeds to step S24, and it is determined in step S24 whether or not the timer set time of the leading timer wait information has been reached.

When the timer setting time of the head timer waiting information is reached in step S24, the process returns to step S21, and the determination and processing from step S21 to step S24 are repeated. Then, when the set timer list is empty in step S23 and when the timer set time of the leading timer waiting information has not been reached in step S24, the timer interrupt processing is completed.

FIG. 7 is a flow chart showing the removal of the head timer wait information. The removal of the leading timer wait information in FIG. 7 shows a subroutine of the operation when the timer interrupt processing unit 34 in the operating system (OS) 1 removes the leading timer wait information from the set timer list 31. . This subroutine corresponds to step S13 shown in FIG. 5 and step S21 shown in FIG.

In step S31, the leading timer wait information is removed from the list. In step S32, it is determined whether the set timer list is empty. If the set timer list is not empty in step S32, the process proceeds to step S33,
In step S33, the timer hardware is set so as to generate an interrupt at the set time of the leading element + the allowable delay time, and the removal of the leading timer wait information is completed. If the set timer list is empty in step S32, step S32
In step S34, the timer hardware is set so as not to generate an interrupt.

As described above, according to the present embodiment, the maximum value of the timer response time can be limited and the following performance degradation can be reduced without requiring any special hardware. .

First, at the start or end of the timer interrupt process, it is possible to reduce the amount of time required for the process of saving or restoring the states of many registers.

Before starting or ending the timer interrupt processing, wait until the intermediate results of instruction execution left in the pipeline consisting of many stages are cleared, or by discarding them. It is possible to reduce the operation rate of each stage in the line and, as a result, reduce the performance of the processor.

Further, since the cache memory executed by the execution of the timer interrupt processing program is rewritten to a content unrelated to the program interrupted by the interrupt, the execution efficiency of the program interrupted when returning from the interrupt processing is lowered. Can be reduced.

Further, the contents of the branch prediction buffer are updated by the execution of the timer interrupt processing program, and it is possible to reduce the performance deterioration due to the increased occurrence rate of branch prediction errors after returning from the interrupt processing.

[0090]

According to the interrupt processing system of the present invention, in an interrupt processing system for performing interrupt processing in a computer system, an interrupt processing program executing section for executing a program for interrupt processing in the computer system and an arbitrary program in the computer system are provided. A polling processing unit that inspects the interrupt request generation by polling everywhere, and activates the interrupt processing program when the interrupt request generation is detected,
Since the normal interrupt processing unit that starts the interrupt processing program by the normal interrupt processing based on the generation of the interrupt request and the delay processing unit that delays the normal interrupt processing by the normal interrupt processing unit for a predetermined time are provided, It can reduce the consumption of a lot of time in the process of saving or restoring the state of a large number of registers at the start or end. In addition, before starting or ending the interrupt processing, wait until the intermediate results of instruction execution left in the pipeline consisting of many stages are cleared, or discard them, and It is possible to reduce the deterioration of the operating rate of the stage and, as a result, the deterioration of the performance of the processor. Also, it is possible to reduce the deterioration of the execution efficiency of the program interrupted when returning from the interrupt processing due to the cache memory being executed by the interrupt processing program being rewritten to the contents unrelated to the program interrupted by the interrupt. You can In addition, the content of the branch prediction buffer is updated by the execution of the interrupt processing program, and there is an effect that it is possible to reduce performance degradation due to an increase in the occurrence rate of branch prediction errors after returning from the interrupt processing.

Further, in the interrupt processing system of the present invention, in the above description, the polling processing section is judged by the inspection time judgment section and the inspection time judgment section which judge the time when the possibility of executing the program of the computer system is low. Since the inspection unit for inspecting the generation of the interrupt request at the time point and the activation unit for activating the interrupt processing program when the generation of the interrupt request is detected by the inspection unit, the processing overhead can be reduced by the polling process. Has the effect.

Further, since the interrupt processing system of the present invention has the variable setting section for variably setting the delay time by the delay processing section in accordance with the inspection by the polling processing section in the above description, the software for the delay processing section is set. Thus, there is an effect that the delay time can be set to be changeable.

Further, in the interrupt processing system of the present invention, in the above description, since the delay processing unit delays a plurality of interrupt requests uniformly, it is possible to uniformly delay the logical sum of all interrupt request signals. The effect that the probability of the interrupt processing being activated by the polling processing unit can be increased while ensuring the maximum interrupt response time of the system is achieved.

In the above-described interrupt processing system of the present invention, the delay processing section delays a plurality of interrupt requests by changing the delay time for each interrupt generation source. The effect is that the time can be set.

Further, in the interrupt processing system of the present invention, in the interrupt processing system for performing the timer interrupt processing in the computer system, the timer interrupt processing program executing section for executing the program of the timer interrupt processing in the computer system, and any of the computer system A polling processor that checks the generation of interrupt requests by polling everywhere in the program and starts the timer interrupt processing program when the generation of a timer interrupt request is detected, and a timer that performs normal interrupt processing based on the generation of a timer interrupt request. Since the timer interrupt processing unit for starting the interrupt processing program and the delay processing unit for delaying the timer interrupt processing by the timer interrupt processing unit by a predetermined time are provided,
The effect of limiting the maximum value of the timer response time and reducing the following performance degradation can be obtained without requiring special hardware. First, it is possible to reduce consumption of a lot of time required for the process of saving or restoring the states of a large number of registers at the start or end of the timer interrupt process. Also, before starting or ending the timer interrupt processing, wait until the intermediate results of instruction execution left in the pipeline consisting of many stages are cleared, or by discarding these, It is possible to reduce the operation rate of each stage and, as a result, reduce the performance of the processor. Further, it is possible to reduce the deterioration of the execution efficiency of the program interrupted when returning from the interrupt processing due to the fact that the cache memory by the execution of the timer interrupt processing program is rewritten to the content unrelated to the program interrupted by the interrupt. be able to. In addition, the content of the branch prediction buffer is updated by the execution of the timer interrupt processing program, and there is an effect that it is possible to reduce the deterioration in performance due to the increased occurrence rate of branch prediction errors after returning from the interrupt processing.

Further, in the above-described interrupt processing system of the present invention, since the delay processing unit updates before and after the processing of a plurality of timer interrupt requests, the set time is still set after the timer setting time of the timer wait information has elapsed. By instructing the procedure pointer to call the procedure of the timer wait information of the timer setting time that has not elapsed, the polling processing unit checks the setting timer list for the occurrence of the timer expiration of the timer wait information. It is possible to ensure that the timer detection of the timer wait information is not delayed with respect to the set timer list for a certain time or more while obtaining the reduction effect.

[Brief description of drawings]

FIG. 1 is a diagram showing a hardware configuration of an interrupt request mechanism in the case of uniformly delaying all interrupt requests applied to this embodiment.

FIG. 2 is a diagram showing a hardware configuration of an interrupt request mechanism when the delay time is changed for each interrupt request.

FIG. 3 is a diagram showing a data structure of an interrupt request when a timer interrupt is delayed.

FIG. 4 is a flowchart showing a procedure of timer registration processing.

FIG. 5 is a flowchart showing a procedure of polling processing.

FIG. 6 is a flowchart showing a procedure of timer interrupt processing.

FIG. 7 is a flowchart showing removal of leading timer wait information.

[Explanation of symbols]

1 ... Operating system (OS), 2 ... Polling processing unit, 3 ... Inspection determination unit, 4 ... Inspection unit, 5
...... Activating unit, 6 ... Interrupt processing program, 7 ... Normal interrupt processing unit, 8 ... Variable setting unit, 9 ... Interrupt request register, 10 ... Interrupt service register,
11 ... AND circuit, 12 ... OR circuit, 13 ... Rising delay circuit, 14 ... Processor, 15 ... Interrupt mask register, 31 ... Setting timer list, 32-
1 ... Timer wait information, 32-1-1 ... Timer set time, 32-1-2 ... Allowable delay time, 32-1-3 ...
Procedure pointer, 32-2 ... Timer wait information, 32-
2-1 ... Timer setting time, 32-2-2 ... Allowable delay time, 32-2-3 ... Procedure pointer, 32-3 ...
Timer wait information, 32-3-1 ... Timer set time, 3
2-3-2 ... Allowable delay time, 32-3-3 ... Procedure pointer, 33 ... Timer interrupt processing program, 3
4 ... Timer interrupt processing block,

Claims (7)

[Claims] 1. An interrupt processing system for performing interrupt processing in a computer system, and an interrupt processing program execution unit for executing an interrupt processing program in the computer system, and an interrupt request by polling at any place in any program of the computer system. A polling processing unit that inspects the occurrence and activates the interrupt processing program when an interrupt request is detected, and a normal interrupt processing unit that activates the interrupt processing program by normal interrupt processing based on the interrupt request occurrence. And a delay processing unit that delays the normal interrupt processing by the normal interrupt processing unit by a predetermined time, and an interrupt processing system. 2. The interrupt processing system according to claim 1, wherein the polling processing unit determines by an inspection time determination unit that determines a time point when the program of the computer system is unlikely to be executed, and the inspection time determination unit. An interrupt processing system, comprising: an inspection unit for inspecting the generation of an interrupt request at the time when the interrupt request is generated, and an activation unit for activating the interrupt processing program when the inspection unit detects the generation of the interrupt request. 3. The interrupt processing system according to claim 1, further comprising a variable setting unit that variably sets a delay time by the delay processing unit in accordance with an inspection by the polling processing unit. 4. The interrupt processing system according to claim 1, wherein the delay processing unit uniformly delays a plurality of interrupt requests. 5. The interrupt processing system according to claim 1, wherein the delay processing unit delays a plurality of interrupt requests by changing a delay time for each interrupt generation source. 6. An interrupt processing system for performing timer interrupt processing in a computer system, and a timer interrupt processing program executing section for executing a program for timer interrupt processing in the computer system, and polling at various places in an arbitrary program of the computer system. And a polling processing unit that activates the timer interrupt processing program when a timer interrupt request generation is detected, and the timer interrupt processing program by normal interrupt processing based on the timer interrupt request generation. An interrupt processing system comprising: a timer interrupt processing unit for activating the timer interrupt processing unit; and a delay processing unit for delaying the timer interrupt processing by the timer interrupt processing unit for a predetermined time. . 7. The interrupt processing system according to claim 6, wherein the delay processing unit updates before and after processing of a plurality of timer interrupt requests.