JP2003030041A - Circuit and method of memory initialization and memory initialization circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress increase of power consumption in a memory to be caused when the power of the memory is applied earlier. SOLUTION: By providing a memory initialization circuit 6, a power up sequence to set a state that a control command from the outside of the memory is acceptable is executed to the memory by a power up sequence part 63 according to the buildup of the power source VCC2 of the memory detected by a power detecting circuit part 61. Then, the memory is set in a power saving operation mode by a power saving mode setting part 63.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory initialization circuit and method, and more particularly to a memory initialization circuit and method used in memory control in which a memory and a memory controller for controlling the memory operate with different power supplies. is there.

[0002]

2. Description of the Related Art In recent years, with the increase in capacity and speed of information processing, a memory used in an information processing apparatus such as a computer has been increased in capacity and speed. Therefore, the control of the memory is also complicated, and a memory controller for memory control independent of a microprocessor such as a CPU is used. FIG. 4 shows a conventional memory control system. The memory controller 2 controls the memory 3 via the control bus 4 in response to a memory access request from the CPU 1 to issue a data read / write instruction. At that time, the memory 3 is connected via the data bus 5.
The data read from the memory 3 is obtained, or the data to be written to the memory 3 is provided.

In such a memory control system,
In a volatile memory such as SRAM or DRAM, when a sudden power drop occurs due to a power failure or the like, the data in the memory cannot be written back to a non-volatile storage medium such as a hard disk, resulting in data loss. is there. Therefore, conventionally, as shown in FIG. 4, the power supply VCC1 such as the memory controller 2 or the CPU 1 which consumes a large amount of current and the power supply VCC2 of the memory 3 are separated from each other, and the current is supplied from the battery to the VCC2 during the power failure. As a result, a configuration for holding the data in the memory is used (see, for example, JP-A-5-226159).

[0004]

However, in such a conventional memory control system, the power supply VCC1 of the memory controller 2 and the CPU 1 and the power supply VCC2 of the memory 3 are separate systems, and therefore, for example, a normal When VCC2 is turned on before VCC1 and rises to the operable potential of the memory 3 when the power is turned on, there is a problem that the memory 3 becomes uncontrolled and its current consumption increases. The present invention is intended to solve such a problem, and an object of the present invention is to provide a memory initialization circuit and method capable of suppressing an increase in current consumption in a memory that occurs when the power of the memory is first turned on. I am trying.

[0005]

In order to achieve such an object, a memory initialization circuit according to the present invention is a memory control system having a memory for storing data and a memory controller for controlling this memory. A memory initialization circuit used for initializing a memory, comprising an initialization means for setting an operation mode of the memory to an operation mode in which power consumption in the memory is reduced in response to a rise of a power supply of the memory. It is a thing.

As a concrete structure of the initialization means, a power-up sequence section for executing a power-up sequence for making the memory accept a control command from the outside of the memory, and after executing this power-up sequence. A power saving mode setting unit that sets the memory to the power saving operation mode may be provided.

The memory initialization method of the present invention is used in a memory control system having a memory for storing data and a memory controller for controlling the memory,
A memory initialization method for initializing a memory, wherein the operation mode of the memory is set to an operation mode in which the power consumption of the memory is reduced in response to the rise of the power supply of the memory.

More specifically, the memory may be set to the power saving operation mode after executing a power-up sequence for making the memory accept a control command from outside the memory. .

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a memory control system to which a memory initialization circuit according to an embodiment of the present invention is applied. The memory control system is supplied to the memory 3 for storing data, the memory controller 2 for controlling the memory 3 via the control bus 4 and the data bus 5 in response to a memory access request from the CPU 1, and the memory 3. Power supply VCC
A memory initialization circuit 6 for initializing the memory 3 at the rising edge of 2 is provided. The memory 3 and the memory initialization circuit 6 are supplied with a power supply VCC2 of a system different from the power supply VCC1 of the memory controller 2 and the CPU 1.

FIG. 2 shows a configuration example of the memory initialization circuit 6. The memory initialization circuit 6 is provided with a power supply detection unit 61, a power-up sequence unit 62, a power saving mode setting unit 63, and a bus control unit 64. Power detection unit 61
Is a circuit unit that detects that VCC2 has risen to the operable potential of the memory 3. The power-up sequence unit 62 is a circuit unit that executes a power-up sequence for the memory 3 in response to the rise detection of VCC2 by the power supply detection unit 61. The power-up sequence is an operation for the memory 3 to start a normal operation when the power supply to the memory 3 is started. For example, when the memory 3 is a clock synchronous SDRAM (Synchoronouse DRAM), the memory 3 is set so that it can accept control commands.

The power-saving mode setting unit 63 includes a power source detecting unit 6
This is a circuit unit that sets the operation mode of the memory 3 to the power saving mode after the execution of the power-up sequence by the power-up sequence unit 62 after the detection of the rise of the VCC2 by 1 is completed. For example, in an SDRAM or the like, when there is no normal read / write access to the memory, the access waiting on the control bus 4 is stopped, and further, the operating clock is internally disabled to reduce the current consumption. A power saving operation mode is provided. Generally, such an operation mode can be controlled from outside the memory 3 via the control bus 4. The bus control unit 64 is a circuit unit that controls the memory 3 via the control bus 4 and the data bus 5 in accordance with an instruction from the power-up sequence unit 62 or the power saving mode setting unit 63.

Next, the operation of the memory initialization circuit will be described with reference to FIG. In the memory initialization circuit 6, when the power supply detection unit 61 detects the rise of the power supply VCC2 of the memory 3 (step 100: YES), the power-up sequence unit 62 executes the power-up sequence for the memory 3. (Step 101). After that, the power saving mode setting unit 63 sets the memory 3 to the power saving operation mode (step 102) and ends the series of memory initialization processing.

As described above, since the memory initialization circuit 6 is provided and the memory 3 is initialized in accordance with the rise of the power supply VCC2 of the memory 3, the operation mode in which the power consumption can be reduced can be set. It is possible to suppress the increase in current consumption in the memory that occurs when the power is turned on first,
Power supply VCC1 for memory controller 2 and CPU 1
Even in a memory control system in which the power supply VCC2 of the memory 3 is a separate system, stable operation can be obtained when the power is turned on.

Further, when the memory 3 is set to the power saving operation mode, the operation mode with the lowest power consumption has a very high effect. Furthermore, it is possible to set the detection threshold value of the overcurrent detection circuit of the power supply on the memory side to an appropriate value, which enables accurate detection of overcurrent due to a true abnormality of the memory, and It is possible to minimize the allowable current value of the power supply of, and the power supply can be configured with a small size and a low cost.

In the above description, the memory initialization circuit 6
When VCC2 is used as the operating power source of the
1 can be realized by a power supply circuit inside the memory initialization circuit 6.
In this case, the above memory initialization process is started in response to the activation of the memory initialization circuit 6. The case where the SDRAM is used as the memory 3 has been described as an example.
The present invention is not limited to this, and the present invention can be similarly applied to a memory of another control method, and similar operational effects can be obtained.

[0016]

As described above, according to the present invention, the operation mode of the memory is set to the operation mode in which the power consumption of the memory is reduced according to the rise of the power supply for the memory. Even if the memory control system can suppress the increase of the current consumption in the memory that occurs when the power supply of is first turned on, and the power supply for the memory and the CPU and the power supply for the memory are separate systems, Stable operation is obtained when the power is turned on.

[Brief description of drawings]

FIG. 1 is a block diagram of a memory control system to which a memory initialization circuit according to an embodiment of the present invention is applied.

FIG. 2 is a block diagram showing a configuration of a memory initialization circuit.

FIG. 3 is a flowchart showing a memory initialization operation.

FIG. 4 is a block diagram showing a conventional memory control system.

[Explanation of symbols]

1 ... CPU, 2 ... Memory controller, 3 ... Memory, 4
Control bus, 5 Data bus, 6 Memory initialization circuit, 61 Power supply detection unit, 62 Power up sequence unit, 63 Power saving mode setting unit, 64 Bus control unit.

Claims (4)

[Claims] 1. A memory initialization circuit used in a memory control system having a memory for storing data and a memory controller for controlling the memory, the memory initialization circuit initializing the memory, the method comprising: Accordingly, the memory initialization circuit is provided with an initialization unit that sets an operation mode of the memory to an operation mode in which power consumption in the memory is reduced. 2. The memory initialization circuit according to claim 1, wherein the initialization unit executes a power-up sequence for bringing the memory into a state in which a control command from the outside of the memory can be accepted. A memory initialization circuit comprising: a sequence unit; and a power saving mode setting unit that sets the memory to a power saving operation mode after executing the power-up sequence. 3. A memory initialization method for initializing the memory used in a memory control system having a memory for storing data and a memory controller for controlling the memory, the method comprising: Accordingly, the memory initialization method is characterized in that the operation mode of the memory is set to an operation mode in which power consumption in the memory is reduced. 4. The memory initialization method according to claim 3, wherein the memory is subjected to a power saving operation after a power-up sequence for executing a power-up sequence for allowing the memory to accept a control command from outside the memory. A memory initialization method characterized by setting to a mode.