JP2003023411A - Orthogonal frequency-division multiplex signal generator, and orthogonal frequency-division multiplex signal decoder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a configuration of an orthogonal frequency-division multiplex(OFDM) signal generator and an orthogonal frequency-division multiplex signal decoder, that can adaptively set modulation parameters, obtain information signal of a large capacity from a 1st serial data bus, depending on the quality of transmission line and subjects the signal to radio transmission to a 2nd serial data bus. SOLUTION: This invention realizes this configuration by configuring the orthogonal frequency-division multiplex signal generator and the orthogonal frequency-division multiplex signal decoder, in such a way that an input processing circuit 1 obtains an information signal from a 1st serial data bus for the purposes of radio transmission, an input circuit 51 applies error correction coding to increase an amount of data to be transmitted; trellis coding and modulation mapping to the signal, an OFDM transmission section 52 modulates the signal and transmits the modulated signal together with parameter information related to the operation of the input circuit; an OFDM reception section 54 receives the processed signal to obtain the parameter information; and an output circuit section 55 decodes the signal, on the basis of the parameter information, to obtain the information signal and supplies the information signal to a 2nd serial data bus.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an orthogonal frequency division multiplex signal generator and a decoding apparatus therefor, and more particularly to an orthogonal frequency division multiplex signal having a limited frequency band for information signals such as encoded digital video signals. , And orthogonal frequency division multiplexing (OFDM: Or
TECHNICAL FIELD The present invention relates to an orthogonal frequency division multiplex signal generation device that transmits a thogonal frequency division multiplex signal and an orthogonal frequency division multiplex signal decoding device that receives the orthogonal frequency division multiplex signal.

[0002]

2. Description of the Related Art Conventionally, an orthogonal frequency division multiplex signal transmission system has been used as a transmission system for transmitting a compression-coded digital information signal. Since the orthogonal frequency division multiplex signal transmission system divides the information signal to be transmitted into carrier waves of many frequencies and modulates and transmits,
Since the modulation speed of each carrier can be reduced, signals can be transmitted without being affected by multipath.
It has also been decided to adopt it as a terrestrial digital broadcasting system from three years.

Further, since an information signal is transmitted using many carriers, it is a transmission system having a high frequency utilization efficiency such as a rectangular transmission spectrum. The orthogonal frequency division multiplex signal transmission system is a wireless LAN (Local Area Network). It has also come to be used in the field of communication such as.

In the orthogonal frequency division multiplex signal transmission apparatus and the reception apparatus thus transmitting using the orthogonal frequency division multiplex signal transmission method, although the transmission quality is less deteriorated due to multipath distortion, signals such as long-distance reception can be obtained. When the reception level of the signal decreases, or when some of the carriers composed of many frequencies are interfered, the quality of the received signal decreases as with other modulation methods, and the transmitted information signal Error data is likely to be included in.

As a method for correcting such an error signal into a correct signal, for example, by using the Reed-Solomon code invented by Reed and Solomon et al.
By generating a redundant signal for error signal correction in advance and transmitting it by adding it, the receiving device detects whether or not the received data includes the error signal based on this signal, and the error signal is detected. When detected, an error signal is detected, corrected, and corrected by using the error correction signal to correct the error signal to correct data or to correct the information signal close to the transmitted information signal. There is.

In this way, the information signal to which the error correction signal is added is transmitted as a signal modulated by the orthogonal frequency division multiplex signal system, but in order to further enhance the error signal resistance against weak electric field reception, the trellis code is used. Is used.

In the trellis encoding, a q (q is an integer) byte code is added to a p (p is an integer) byte signal, and p +
The signal is transmitted as a q-byte signal, and the receiving side decodes a p-byte signal from the p + q-byte signal by the trellis coding. Although the transmission rate is increased by transmitting the signal, the error rate of the signal whose correction capability is enhanced by using the q-byte signal is higher than that of the error signal increased due to the increase of the transmission rate. It is used as an improved code generation method.

In this way, the information signal to which the code for error signal correction is added is an orthogonal frequency division multiplex signal for multi-value modulation and transmitting the carrier waves of the respective frequencies forming the orthogonal frequency division multiplex signal. Is generated as
A generation method for generating the orthogonal frequency division multiplexed signal, a transmission device equipped with the method, and a reception device for receiving the transmitted signal will be described with reference to examples.

FIG. 8 shows a block diagram of a conventional orthogonal frequency division multiplex signal transmitter. The transmitter shown in this figure is
The main part of the transmitting device disclosed in Japanese Patent Laid-Open No. 9-153882 “Orthogonal Frequency Division Multiplexing Signal Transmission System, Transmitting Device and Receiving Device” is shown in FIG. The data is supplied to the input circuit 2, and an error correction code is added as necessary.

The signal to which the error correction code is added is IF
The signal is supplied to an FT (Inverse fast Fourier transform) operation unit 4, and the IFFT operation unit 4 performs an inverse fast Fourier transform operation on the supplied digital data to perform an in-phase signal (I signal; In-phase). And a quadrature signal (Q signal; Quadrature).

I generated by the IFFT operation unit 4
The signal and the Q signal are supplied to the digital quadrature modulator 6,
There, the intermediate frequency signal supplied from the intermediate frequency oscillator 5 is used as a carrier, and the signal and the signal are transferred to the phase shifter 5
1a is used to perform quadrature amplitude modulation (QAM) by using a signal that is phase-shifted by 90 degrees.

Then, for example, with the intermediate frequency as the center value, a positive frequency and a negative frequency with respect to the intermediate frequency are respectively generated as 128 sets of carrier waves, and are generated as an OFDM signal including a total of 257 information carrier waves. .

The OFDM signal supplied from the digital quadrature modulator 6 is supplied to the D / A converter 7, and the clock signal supplied from the clock frequency divider 3 is used as a sampling clock signal to be converted into an analog signal. The converted analog signal is supplied to the frequency converter 8.

In the frequency converter 8, the supplied analog signal is converted into a high frequency signal in a predetermined transmission frequency band, and the converted high frequency signal is subjected to processing such as power amplification in the transmitter 9 and is not shown. A part of the signal radiated from the antenna to the space transmission line and radiated to the space transmission line is received by a reception antenna (not shown) and supplied to the orthogonal frequency division multiplexing signal receiving apparatus.

FIG. 9 shows a block diagram of an example of a conventional orthogonal frequency division multiplexing signal receiving apparatus. This receiving device is a main part of the receiving device disclosed in Japanese Patent Laid-Open No. 9-153882, "Orthogonal Frequency Division Multiplexing Signal Transmission System, Transmitting Device and Receiving Device".

In the figure, an OFDM signal supplied via a receiving antenna (not shown) is high-frequency amplified by the receiving section 11, further converted to an intermediate frequency by the frequency converter 12, and supplied to the intermediate-frequency amplifier 13. The amplified signal is supplied to the carrier extraction and quadrature demodulator 14.

The carrier extraction circuit portion of the carrier extraction / quadrature demodulator 14 is a circuit for extracting the center carrier (carrier) of the input OFDM signal with as little phase error as possible, and is extracted by the carrier extraction / quadrature demodulator 14. The center carrier signal thus generated is supplied to the intermediate frequency oscillator 15, where a center frequency signal phase-locked with the center carrier frequency is generated.

One of the center frequency signals is supplied to the quadrature demodulator section of the carrier extracting and quadrature demodulator 14, and the other one is phase-shifted by 90 degrees by the 90-degree shifter 16, It is supplied to the quadrature demodulator 14.

In this way, from the quadrature demodulator section of the carrier extraction and quadrature demodulator 14, an analog signal equivalent to the analog signal output from the D / A converter 7 of the transmitter (orthogonal frequency division multiplexed signal). Are demodulated and obtained, and one of the obtained signals is supplied to the synchronizing signal generation circuit 17 and the other is supplied to the low pass filter (LPF) 18, and these signals are transmitted as OFDM signal information. A signal in a required frequency band is passed, supplied to the A / D converter 19 and converted into a digital signal.

Further, one of the demodulated analog signals supplied from the carrier extracting and quadrature demodulator 14 is supplied to the synchronizing signal generating circuit 17, and the synchronizing signal generating circuit 1 is provided.
In 7, the sampling signal is generated in the sample synchronization signal generation circuit section in phase synchronization with the pilot signal transmitted as a continuous signal in each symbol period including the guard interval period.

The generated sampling signal and pilot signal are supplied to the symbol synchronization signal generation circuit section, the resymbol period is detected by checking the phase state, the symbol synchronization signal is generated, and the generated symbol synchronization is generated. A clock signal for decoding operation for removing the guard interval period is generated based on the signal, and is supplied as a drive signal to each circuit unit.

On the other hand, of the signals supplied from the carrier extraction / quadrature demodulator 14, the other demodulated analog signal is passed through the LPF 18 and the A / D converter 19 to F
It is supplied to the FT calculation unit 20.

In the FFT calculation unit 20, a fast Fourier transform (FFT) calculation is performed under the control of the system clock signal from the synchronization signal generation circuit 17, and a real part signal (R signal) for each frequency of the supplied signal. And an imaginary part signal (I signal) are calculated, and the obtained R signal and I signal for each frequency are decoded by decoding the digital information signal based on their respective signal levels, and are decoded. The digital information signal is supplied to the output circuit 21, subjected to error correction, output signal processing such as parallel-serial conversion, and supplied to the output terminal 22 for demodulation.

Next, in Japanese Unexamined Patent Publication No. 11-163823, "Orthogonal Frequency Division Multiplexing Signal Transmission Method, Transmitting Apparatus and Receiving Apparatus", a large number of encoding and modulation methods can be selected according to the receiving situation. A signal transmission method has been proposed and will be described.

FIG. 4 is a diagram showing a main part of an input circuit on the transmission side in the orthogonal frequency division multiplexing signal transmission method, and FIG. 5 is a view showing a main part of an output circuit on the reception side.

The input circuit shown in FIG. 4 is used in place of the input circuit 2 of the conventional orthogonal frequency division multiplexing signal transmission apparatus shown in FIG. 8, and the output circuit shown in FIG.
It is used instead of the output circuit 21 of the conventional orthogonal frequency division multiplex signal transmission device shown in FIG.

First, the input circuit shown in FIG. 4 is composed of a plurality of error correction coding circuits and modulation mapping circuits in the input circuit 2 shown in FIG. From the error correction coding rate, the trellis coding rate, and the modulation mapping method of, the rate specifying control signal (a signal obtained by multiplexing a plurality of rate specifying signals, hereinafter simply referred to as a rate specifying signal) Error correction coding circuit with each rate specified,
The difference is that it is configured by a trellis encoding circuit and a modulation mapping circuit, and a frame synthesis circuit.

The output circuit is shown in FIG.
In contrast to the output circuit 21 shown in FIG. 5 which is composed of a single demodulation demapping circuit and an error correction circuit, respectively, the output circuit shown in FIG. 5 has a plurality of demodulation demapping schemes, a decoding rate of Viterbi decoding, and Among the decoding rates of the error correction method, the demodulation demapping circuit 37, the Viterbi decoding circuit 38, the error correction circuit 39, and the frame decoding circuit 36, each of which has a rate designated by a rate designation signal, are featured. is there.

The error correction coding circuit 3 shown in FIG.
Reference numeral 1 denotes, for example, an encoding circuit having two types of encoding rates, and, for example, based on a rate designation signal obtained by receiving and demodulating the upstream modulation data transmitted from the receiving apparatus, a code having either one type of encoding rate. An error correction code (for example, Reed-Solomon code) is added to the digital data by selectively using the digitization circuit, and the obtained signal is supplied to the trellis coding circuit 32.

The trellis coding circuit 32 is composed of four types of convolutional coding circuits having coding rates of, for example, 1/2, 3/4, 5/6 and 7/8, and these rate designating signals are assigned to these convolutional coding signals. Based on this, any one type of convolutional coding circuit is selected and used. The digital data thus convolutionally encoded is supplied to the modulation mapping circuit 33.

In the modulation mapping circuit 33, for example, 4P
4 of SK, 16QAM, 64QAM, and 256QAM
It is composed of a modulation mapping circuit for performing modulation in accordance with one of the types of modulation schemes, and any one type of modulation mapping circuit is selected and used based on the above-mentioned rate designation signal, and digital data subjected to modulation mapping is obtained. Generated and output.

Further, the above rate designation signal is supplied to a frame synthesizing circuit described later as an ID signal indicating each rate of the error correction coding rate, the trellis coding rate, and the modulation mapping method.

In the frame synthesizing circuit 34, the modulation-mapped digital data supplied from the modulation mapping circuit 33 and the above-mentioned ID signal supplied are frame-synthesized and output as an R signal and an I signal. It These R signal and I signal are the IF signals of FIG.
It is supplied to the FT calculation unit 4 and subjected to IFFT calculation, and is converted into an in-phase signal (I signal) and a quadrature signal (Q signal).

On the other hand, in the receiving device, as described with reference to FIG. 9 described above, the R signal and the I signal obtained by the FFT operation are respectively supplied to the frame decoder 36 of FIG. The modulated and mapped digital data is supplied to the demodulation demapping circuit 37 and further decoded to obtain I.
The D signal is a demodulation demapping circuit 37 and a Viterbi demodulation circuit 3.
8 and the error correction circuit 39 are supplied as rate specifying signals.

In the demodulation demapping circuit 37, 4PSK, which corresponds to the modulation method of the modulation mapping circuit 33,
It is composed of a demodulation demapping circuit by four types of modulation schemes of 16QAM, 64QAM, and 256QAM, and demodulates a signal of the same modulation scheme as the modulation scheme selected by the modulation mapping circuit 33 on the basis of the above rate designation signal. The demapping circuit is selected and the input digital data is demodulated.

The Viterbi decoding circuit 38 is composed of a Viterbi decoder having four kinds of decoding rates corresponding to the four kinds of coding rates of the trellis coding circuit 32.
Based on the above rate designation signal, the trellis encoding circuit 3
The signal of the decoding rate corresponding to the coding rate selected in 2 is supplied to the Viterbi decoder, and the data decoded there is supplied to the error correction circuit 39.

The error correction circuit 39 is composed of error correction circuits of two kinds of decoding rates corresponding to the two kinds of coding rates of the error correction coding circuit 31, and it is based on the above rate designating signal Viterbi. The signal decoded by the decoder is output as error-corrected decoded data at a decoding rate corresponding to the coding rate selected by the error correction coding circuit 31.

According to the conventional orthogonal frequency division multiplex signal transmission method which operates as described above, the error correction coding rate on the transmission side, which maximizes the amount of data that can be transmitted depending on the reception status,
Trellis coding rate and modulation mapping scheme,
By designating to the transmitting side, the transmitting side generates and transmits the optimum orthogonal frequency division multiplexing signal according to the judgment result of the receiving situation, and even if the receiving situation changes, the change situation also With, the transmission parameters can be reset so that the most data can be transmitted.

However, the above-mentioned JP-A-11-16382.
In the method described in Japanese Patent Publication No. 3, the Viterbi decoding circuit 38 is
Since there are very few common decoding circuit parts for different trellis coding rates, as many Viterbi decoders as the required coding rates are required. In the example shown in the publication, the Viterbi decoding circuit 38 is used. In addition, a Viterbi decoder having four types of decoding rates corresponding to the trellis encoding circuit 32 having four types of encoding rates is required.

Moreover, since the Viterbi decoder is the largest in circuit scale among the modulator and demodulator,
Each time the coding rate is changed, it is necessary to carry out modulation and demodulation using a dedicated decoder corresponding to them, which has a drawback that the circuit scale of these modulation device and demodulation device becomes large.

As one of the methods for solving this drawback, Japanese Patent Laid-Open No. 12-115117 "Orthogonal Frequency Division Multiplexing Signal Transmission Method, Transmitting Device and Receiving Device" is a kind of convolutional code for a trellis coding circuit. A method of transmitting an orthogonal frequency division multiplexed signal using a puncture code has been proposed.

The puncturing code erases data from a single coding rate, for example, a convolutional code having a coding rate of 1/2, in accordance with a certain rule, that is, puncturing, to thereby obtain a code having an arbitrary coding rate. The Viterbi decoder for this puncture code is
Original code before puncturing, eg, coding rate 1 /
A decoder corresponding to decoding at an arbitrary coding rate can be configured by adding a few circuits to the Viterbi decoder corresponding to 2.

FIG. 6 is a main part of an input circuit on the transmitting side in the above-mentioned Japanese Patent Laid-Open No. 12-115117, which is a proposal relating to the decoder, and FIG. 7 is a main part of an output circuit on the receiving side in the publication. It shows the part. 6 and 7, the same components as those in FIGS. 4 and 5 described above are designated by the same reference numerals, and the description thereof will be omitted.

The input circuit shown in FIG. 6 is used in place of the input circuit 2 of the conventional orthogonal frequency division multiplexing signal transmission apparatus shown in FIG. 8 described above, and the output circuit shown in FIG. It is used instead of the output circuit 21 of the conventional orthogonal frequency division multiplexing signal transmission device shown in FIG.

The configuration of the input circuit is as follows. In the input circuit of FIG. 4, there are selected from among a plurality of error correction coding rates, trellis coding rates and modulation mapping schemes.
The error correction coding circuit 31, the trellis coding circuit 32, the modulation mapping circuit 33, and the frame synthesizing circuit 34, each of which has a rate designated by the rate designation signal, are included in the input circuit shown in FIG. In the trellis coding circuit 41, a trellis coding circuit having a single coding rate is used, and the puncture coding circuit 4 whose coding rate is designated by a rate designation signal is provided at the subsequent stage.
2 is used, and the output signal of the puncture encoding circuit 42 is supplied to the modulation mapping circuit 33.

On the other hand, regarding the output circuit, in the output circuit shown in FIG. 5 described above, a plurality of demodulation demapping methods, a decoding rate of Viterbi decoding, and a decoding rate of an error correction method are used to select respective output signals by a rate designation signal. A demodulation demapping circuit 37, a Viterbi decoding circuit 38, an error correction circuit 39, and a frame decoder 3 which operate at a specified rate.
In contrast to the configuration shown in FIG. 7, in the output circuit shown in FIG. 7, the Viterbi decoding circuit 46 is a decoding circuit in which an additional circuit is added to the Viterbi decoder corresponding to the same single coding rate as the input side. The circuit is used, and the depuncture conversion circuit 45 whose conversion rate is designated by the rate designation signal is used in the preceding stage. The depuncture conversion circuit 45 has an output signal of the demodulation demapping circuit 37. Is being supplied.

Furthermore, Japanese Patent Application Laid-Open No. 12-244447 "Orthogonal Frequency Division Multiplexed Signal Transmission Method, Transmitting Device and Receiving Device", which the present inventor invented and filed by the present applicant, and Japanese Patent Application Laid-Open No. 13-36498 ". "Orthogonal frequency division multiplexing signal transmission method, transmitter and receiver"
Japanese Patent Application No. 2000-030143 “Orthogonal Frequency” proposed by the present inventor and filed by the present inventor is a method for operating the system proposed by the above-mentioned Japanese Patent Laid-Open No. 12-115117 with a single system clock. Division multiplex signal generation method, orthogonal frequency division multiplex signal generation device, and decoding device thereof "(unpublished at the time of filing of this application), and Japanese Patent Application No. 20
No. 00-159804 "Orthogonal Frequency Division Multiplexing Signal Generation Device and Orthogonal Frequency Division Multiplexing Signal Decoding Device" (unpublished at the time of filing of this application) proposes a data frame arrangement method for the same system.

[0048]

By the way, in recent years, IE
EE (Institute of Electrical and Electronics Engi
neers) 1394 (officially IEEE 1394-199
5, but here it is abbreviated as IEEE 1394) or U
Electronic devices equipped with a serial bus such as SB (Universal Serial Bus) are increasing.

The IEEE1394 serial bus is AV
As an example of cable transmission applied to an (Audio Visual) system, Japanese Patent Laid-Open No. 11-339386 “IEEE”
The contents are disclosed in "AV system equipped with 1394 serial bus".

The serial bus signal is more suitable for wireless transmission than the parallel bus signal. In particular, IEEE13
Since a transmission system using the 94 serial bus can transmit a large amount of image data, a method using OFDM (Orthogonal Frequency Division Multiplexing) is suitable as a modulation format for wirelessly transmitting the large amount of data.

The IEEE 1394 serial bus is a bus standard relating to a transmission specification that enables bidirectional transmission of information signals. For example, in the case of large-capacity image data, bidirectional transmission or unidirectional transmission is possible. However, in the case of a small-capacity signal relating to bus control data, for example, it is defined as a specification assuming bidirectional transmission of an information signal.

In order to perform such bidirectional or unidirectional transmission of large-capacity data and bidirectional transmission of small-capacity data using the OFDM radio transmission and reception devices, the OFDM transmission device and the reception device are respectively It is necessary to use two sets. For example, in the case of being used as a receiving terminal for receiving a large capacity information signal transmitted in one direction such as in a broadcast type application, an OFDM receiving apparatus and an OFDM receiving apparatus are used.
It is necessary to have a transmitter, which is not economically preferable.

As an application for bidirectionally transmitting a large amount of data such as an image, a TV telephone, a TV
There are conferencing systems, etc., but currently there are not many other applications that require bidirectional transmission, so
An inexpensive transmission / reception system can be constructed by limiting the large-capacity data such as images to be transmitted in one direction without equipping such a bidirectional transmission function.

However, even in that case, like bus control data, it is customary to carry out bidirectional transmission for small-capacity data transmission, and the function of transmitting signals in the opposite direction to the supply of a large amount of data is provided. In the case of a device mainly including a receiving device that does not have this, for example, control data cannot be returned, which is not preferable.

Therefore, in each of the input section of the OFDM transmitter and the output section of the receiver, IEEE1394
A bus control is performed by transmitting control data in a pseudo manner with a serial bus, and a configuration of a signal generation device and a signal decoding device for unidirectionally transmitting a large amount of data such as an image is realized.

That is, such a signal generating device and a signal decoding device transmit large-capacity data by the OFDM system, and small-capacity bus control data are signal-multiplexed at the input part of the OFDM transmitter and the output part of the receiver. It is economically preferable that the circuit scale can be greatly reduced if the transmission can be performed by performing the processing of.

Then, the above-mentioned inventor of the present invention and the applicant of the present application filed Japanese Patent Application Laid-Open No. 12-1151.
No. 17, "Orthogonal Frequency Division Multiplexing Signal Transmission Method, Transmitting Device and Receiving Device" proposes an orthogonal frequency division multiplexing signal transmitting method in which a large number of coding parameters and modulation schemes can be selected according to the reception situation. ing.

According to such an orthogonal frequency division multiplex signal transmission method, the reception state is investigated, and the error correction coding rate and trellis coding on the transmission side are made so that the maximum amount of data that can be transmitted in that communication state is obtained. The parameters of the transmission device are set based on transmission parameter information such as a rate designation signal, which allows designation of a rate, a modulation mapping method, and a transmission rate, and is transmitted.

By using such a transmission parameter setting method, one-way large-capacity data can be transmitted from the data transmitted through the IEEE 1394 serial bus or the like without using two sets of an OFDM transmission device and a reception device. Wireless transmission can be performed by one set of OFDM transmission and reception devices.

Therefore, in the present invention, the above-mentioned Japanese Patent Laid-Open No. 12-1 is used.
In an orthogonal frequency division multiplex signal transmission device and a reception device in which a large number of coding parameters and modulation schemes can be selected according to the reception situation as proposed in Japanese Patent Publication No. 15117, bidirectional transmission is performed using an IEEE 1394 serial bus or the like. Enables an OFDM wireless transmission method for unidirectionally transmitting a large amount of data without using two sets of OFDM transmitting apparatus and receiving apparatus, and an orthogonal frequency division multiplex signal generating apparatus using the method, Another object of the present invention is to provide a configuration of an orthogonal frequency division multiplexing signal decoding device at low cost.

[0061]

The present invention comprises the following means 1) and 2) in order to solve the above problems. That is, 1) obtain the information signal to be wirelessly transmitted from the first bidirectional serial bus, and the first and second redundancy information set for ensuring the transmission quality of the information signal. Based on the redundancy information of 2, the first redundant signal and the second redundant signal are added to the information signal to generate a transmission coded signal, and the generated transmission coded signal and the first and second
By generating multi-valued modulation of the redundancy information and the multi-carrier, an orthogonal frequency division multiplexed signal is generated and radiated to the space transmission line, and the orthogonal frequency division division signal radiated to the space transmission line is generated. Decoding the transmission coded signal based on the first and second redundancy information obtained by receiving, and supplying the information signal obtained by the decoding to the second bidirectional serial bus. An orthogonal frequency division multiplex signal generation device for generating the orthogonal frequency division multiplex signal in an orthogonal frequency division multiplex signal transmission and reception system, wherein the information signal includes an error based on the first redundancy information. Error correction coding means (61) for adding a correction code, and 2 based on the second redundancy signal.
One integer value p and q are set, p bytes of the error correction additional information signal are obtained based on the set integer values p and q, and q bytes are obtained after the obtained p bytes of the additional correction information signal. Intermittent reading means (62) for obtaining an intermittent read signal by obtaining and arranging the empty data, and a trellis code for trellis-encoding the intermittent read signal obtained by the intermittent read means to obtain a trellis-coded signal. A puncturing code for puncturing the trellis coded signal obtained by the trellis coding means to generate the transmission coded signal obtained by replacing the empty data with the coded signal. Means of conversion (6
4), and an orthogonal frequency division multiplex signal generation device comprising at least the above.

2) An information signal to be wirelessly transmitted from the first bidirectional serial bus, and first and second redundancy information set for ensuring the transmission quality of the information signal are obtained, and the first and second redundancy information are obtained. A transmission coded signal is generated by adding a first redundancy signal and a second redundancy signal to the information signal based on second redundancy information, and the generated transmission coded signal and the first and second redundancy signals are generated. The multiplicity-modulation of the redundancy information of 2 and a plurality of carriers is used to generate an orthogonal frequency division multiplex signal to be radiated to a space transmission line, and the orthogonal frequency division division signal radiated to the space transmission line is generated. To decode the transmission coded signal based on the first and second redundancy information obtained by receiving the information, and to supply the information signal obtained by the decoding to the second bidirectional serial bus. Orthogonal frequency division multiplex Is an orthogonal frequency division multiplex signal decoding device for receiving the orthogonal frequency division multiplex signal in a signal transmission and reception system, the carrier frequency demodulation signal for a plurality of carriers by demodulating the received orthogonal frequency division multiplex signal By performing frame decoding and demodulation mapping of the carrier demodulated signal obtained by the carrier demodulating means, and obtaining the first and second redundancy information and the transmission coded signal. Orthogonal frequency division signal demodulation means (71, 72), and depuncture conversion of the transmission coded signal based on the second redundancy information,
And decoding means for performing Viterbi decoding to obtain a decoded signal (73,
74, 75) and error signal correction means (76) for performing error correction processing of the decoded signal based on the first redundancy information to obtain the information signal to be supplied to the second bidirectional serial bus. ), And an orthogonal frequency division multiplex signal decoding device.

[0063]

BEST MODE FOR CARRYING OUT THE INVENTION The preferred embodiments of the orthogonal frequency division multiplex signal generator and the orthogonal frequency division multiplex signal decoder according to the present invention will be described below.
FIG. 1 shows an orthogonal frequency division multiplex signal generation device according to the present invention,
FIG. 3 is a block diagram showing an embodiment of a decoding device and a decoding device therefor.

As shown in the figure, the orthogonal frequency division multiplex signal generating apparatus in this embodiment has an input signal processing circuit 5
0, an input circuit 51, and an OFDM transmitter 52. All of these circuits are supplied with a single system clock signal and driven by the signal to perform a desired operation.

The orthogonal frequency division multiplex signal decoding apparatus shown on the right side of the figure is composed of an OFDM receiving section 54, an output circuit 55, and an output signal processing circuit 56, and is similar to the orthogonal frequency division multiplex signal generating apparatus. All circuits are driven by a single system clock signal.

Next, the operations of the orthogonal frequency division multiplex signal generator (hereinafter abbreviated as a generator) and the orthogonal frequency division multiplex signal decoder (hereinafter abbreviated as a decoder) configured as above will be described.

First, in the generator, the video signal data supplied from an electronic device such as a digital movie, a digital camera, a digital video recorder, etc. equipped with an IEEE1394 serial bus is IEEE1394.
It is supplied to the input signal processing circuit 50 via the serial bus.

In the input signal processing circuit 50, the IEEE
From the signal flowing through the 1394 serial bus, the generator obtains the data to be transmitted to the decoding device from the data flowing through the bus, and the obtained data is supplied to the input circuit 51.

The supplied data is, for example, data of an information signal having a large capacity such as a video signal, but here, a small capacity of data transmitted from the generation device to the decoding device together with the data portion of the information signal. Allows bus control data to be transmitted.

In this way, the bus control data is transmitted from the generation device to the decoding device, but the information signal is not transmitted from the decoding device to the generation device. Therefore, the bus control data from the decoding device to the generation device is transmitted. Will not be transmitted.

Therefore, the bus control data from the decoding device which is not transmitted to the generation device is artificially created in the input signal processing circuit 50, and the created pseudo bus control data is from the decoding device. It is assumed that the data is data transmitted via the IEEE 1394 serial bus, and the IEEE 1394
By performing bus control of the serial bus, data is transmitted from the generation device to the decoding device, and the decoding device obtains the data output.

The pseudo bus control data thus created in the input signal processing circuit 50 is I in the normal case.
IEEE 1394 based on the IEEE 1394 protocol
It is created as a signal flowing through the serial bus, and the large volume of information data is transmitted from the generation device to the decoding device based on the generated pseudo control data, but the pseudo control data has a large volume only for the decoding device. It can be used, for example, when transmitting information data.

The operation timing of the generator is controlled by the system clock signal generated by the input signal processing circuit 50, and the generation timing of the pseudo control data is also generated based on the system clock signal. Is supplied by

The signal thus obtained from the IEEE 1394 serial bus and the pseudo control data created there are supplied to the input circuit 51.
1 adds an error correction code to the supplied data output,
Processing such as trellis coding and puncture coding is performed, and the processed signals are placed at the positions of signal point arrangements defined in the two-dimensional plane represented by the real number axis and imaginary number axis for digital modulation. Mapping is performed, and R (real) signal and I (Imaginary) that have been mapped
Each of the signals is supplied to the OFDM transmitter 52.

In the OFDM transmitter 52, the R signals corresponding to the respective generated subcarriers supplied,
And each mapping data by I signal is IFF
It is supplied to a T (Inverse fast Fourier transform) operation unit, where a subcarrier signal modulated according to the supplied mapping data is generated, and the generated carrier signal is converted into a radio frequency signal of a predetermined frequency. It is converted and supplied to the space transmission line 53 from an antenna (not shown).

The radio frequency signal supplied to the space transmission path 53 is received by a reception antenna (not shown) and is transmitted to the OFDM.
The FFT (Fast Fourier) is supplied to the receiving unit 54.
Transform (Fast Fourier Transform) computing section demodulates the mapping data relating to each subcarrier signal wirelessly transmitted, and the mapping data by the R signal and the I signal obtained by demodulation is supplied to the output circuit 55.

The output circuit 55 obtains decoded data by decoding the mapping data represented by the demodulation voltage of the supplied R signal and I signal by demodulation demapping, and the obtained decoded data is subjected to depuncture conversion. , Viterbi decoding, and error correction processing are performed to obtain a data output signal. The data output signal is the same as the data output signal supplied from the input signal processing circuit 50.

The obtained data output signal is supplied to the output signal processing circuit 56, and the supplied data output signal is I
Signal processing for supplying to the IEEE 1394 serial bus is performed, and the data subjected to the signal processing is IEEE
It is supplied to the 1394 serial bus.

In this way, one of the IEEE1394
The large-capacity information signal obtained from the serial bus is wirelessly transmitted and supplied to the other IEEE 1394 serial bus. At the same time, the bus control signal is also wirelessly transmitted from the generation device side to the decoding device side.

When the bus control data is multiplexed with the large capacity information signal and transmitted to the decoding device, the transmitted bus control signal is used for the bus control, but when such a bus control signal is not transmitted. Creates a bus control signal in the output signal processing circuit 56 and uses the created bus control signal to exchange pseudo control data with the IEEE 1394 serial bus while performing the bus control while the IEEE 1394 serial bus is being controlled. Supply data to the bus.

In this way, the bus control data generated by the output signal processing circuit 56 is the control necessary for supplying the data output transmitted from the generating device to the decoding device to the IEEE1394 serial bus based on the IEEE1394 protocol. It is generated and supplied as data.

The flow of the operation by the control data relating to the transfer of the packet data which is performed in the normal state is as follows. First, the tree identification is performed to determine the parent-child relationship between the nodes of the connected device, and the tree identification result is used. Determines the root node that determines the top of the tree structure, and determines the node ID
By identifying the self-device, the isochronous resource manager that manages the synchronous transfer is defined, then the cycle start packet is transmitted as the cycle master, and finally the bus manager that performs the overall management is determined. This is the operation to be decided.

In this way, data transmission between nodes is performed, but when the data transfer is not performed as asynchronous transfer, the bus manager decision is omitted and the isochronous resource manager replaces the bus manager. Control can be performed, and a method of controlling such data transmission is specified in the IEEE 1394 protocol.

Data transmission for causing the isochronous resource manager to control the bus manager is performed by two digital signal recording / reproducing devices such as DVC (Digital).
In the case of unidirectional one-to-one data transfer from Video Cassette) to D-VHS (Digital-VHS), isochronous transfer (synchronous transfer) will be used.
Since the bus manager can be omitted to perform data transmission, the above operations 1 to 3 can be omitted.

In the data transmission in which the operation can be partially omitted, a RAM or the like for temporarily storing the digital data that should be provided on the transmitting device side and the receiving device side in order to perform particularly large-capacity data transmission. The hardware configuration can be simplified.

In this way, the normal control signal is transmitted by the bidirectional communication with the bus manager defined, but the data transmission capacity for that purpose may be small. The bidirectional wireless transmission unit is used, and the large-capacity data transmission is performed in one direction after the transmission path is determined by the small-capacity data communication.

That is, in the large-capacity data transmission, first, data from the IEEE 1394 serial bus is acquired by the generation device, the acquired data is wirelessly transmitted to the decoding device by the OFDM method, and the data received by the decoding device is the other data. The large-capacity wireless transmission between different IEEE 1394 serial buses is performed by being supplied to the IEEE 1394 serial bus.

Next, the operations of the generating device and the decoding device for performing wireless transmission in this way will be further described.
FIG. 2 is a block diagram showing an embodiment detailing the configuration of the input circuit 51 shown in FIG.

In the figure, the input circuit 51 is an error correction coding circuit 61, an intermittent read circuit 62, a trellis coding circuit 63, a puncture coding circuit 64, a frame array circuit 65, a modulation mapping circuit 66, and a frame synthesis circuit 67. It is composed of

First, the data output supplied from the input signal processing circuit 50 is supplied to the error correction coding circuit 61, where the data output depends on the coding rate designated by the rate designation signal from a plurality of error correction coding rates. An error correction code is generated, and the generated error correction code is supplied to the intermittent read circuit 62 as a signal added to its data output.

In the intermittent read circuit 62, the signal supplied thereto is temporarily stored in a memory circuit (not shown) provided therein, and the signal temporarily stored in the memory circuit is requested by the trellis encoding circuit 63. Intermittent reading is performed byte by byte, and the intermittently read signal is supplied to the trellis encoding circuit 63, where it is encoded at a predetermined single encoding rate.

Then, after the signal coded at the single coding rate, a predetermined number of bytes of "0" is added.
Since the data is arranged, the trellis-coded signal obtained by the trellis coding circuit block is also the intermittently-coded signal.

The signal subjected to the intermittent trellis coding at the single rate in this way is punctured by the puncture coding circuit 64.
The puncture encoding circuit block whose encoding rate is specified by the above rate specifying signal from among a plurality of puncture encoding rates is used, and punctures are processed into continuous data by processing in byte units. Encoding is done.

The signal punctured by the coding rate designated in this way is supplied to the frame arranging circuit 65 for mapping, and the mapping is performed from among a plurality of modulation mapping schemes. Modulation mapping for performing multilevel modulation by the multilevel number designated and given by the rate designation signal is performed.

The digital data obtained by the modulation mapping is obtained as a real part signal and an imaginary part signal corresponding to the positions of signal points on a two-dimensional plane defined by the real number axis and the imaginary number axis. In the synthesizing circuit 67, a real part signal and an imaginary part signal for transmitting the rate designating signal to the obtained signals are generated as a signal that is synthesized, and these generated signals are generated by the OFDM transmitter 5.
2 and the OF of the same as described in connection with FIG. 1 above.
The DM signal is supplied to the spatial transmission line.

Then, the OFDM supplied to the spatial transmission path
The signal is received by the OFDM receiver 54, and the R signal and I signal obtained by the reception are supplied to the output circuit 55. A configuration of the output circuit 55 is shown in FIG.

The output circuit 55 shown in the figure comprises a frame decoder 71, a demodulation demapping circuit 72, a depuncture conversion circuit 73, a RAM 74, a Viterbi decoding circuit 75, and an error correction circuit 76. Next, the operation of the output circuit 55 having such a configuration will be described.

First, the output circuit 55 includes the OFDM receiver 5
The R signal and the I signal obtained by being received at 4 are supplied, and the R signal and the I signal are frame-decoded by the frame decoder 71 to obtain a rate designation signal, and the obtained rate designation signal. Is a demodulation demapping circuit 72, a depuncture conversion circuit 73, a Viterbi decoding circuit 7
5 and the error correction circuit 76, and the modulation-mapped data obtained by frame decoding is supplied to the demodulation demapping circuit 72.

In the demodulation demapping circuit 72, the modulation mapping circuit 66 of the generator is selected from a plurality of demodulation demapping schemes for the data subjected to the modulation mapping.
De-mapping is performed by the demodulation de-mapping circuit in which the demodulation method is specified by the rate specifying signal corresponding to the operation of.

The signal thus demapped is supplied to the depuncture conversion circuit 73, where it is depunctured by the depuncture conversion circuit block at the conversion rate specified by the rate designating signal from the plurality of depuncture conversion rates. The conversion process is performed, and the intermittent data obtained by the conversion process is supplied to the RAM 74 or a FIFO memory (not shown) and temporarily stored as one frame of data.

The temporarily stored data is read as continuous data for each data having the frame structure, and the read data is subjected to Viterbi decoding corresponding to the same single coding rate as the generator side. The Viterbi decoding circuit 75 configured by adding an additional circuit to the circuit unit performs Viterbi decoding, and the signal subjected to Viterbi decoding is supplied to the error correction circuit 76.

Then, in the error correction circuit 76, error correction processing is performed by the error correction circuit block whose decoding rate is specified by the above rate specifying signal from among a plurality of error correction decoding rates, and decoded data is obtained. ,
The decoded data obtained is supplied to the output signal processing circuit 56.

In the output signal processing circuit 56, the data thus decoded is supplied as a data output, and the data output is the large-capacity data transmitted from the generating device to the decoding device as described above, or the data output. It is a large amount of data in which bus control data is multiplexed.

The large amount of data thus supplied is based on the system clock signal and is based on IEEE1394.
It is generated as a serial bus signal, and the generated signal is transmitted via the IEEE1394 serial bus to IEEE13
An information signal is reproduced by being supplied to an electronic device equipped with a 94 serial bus.

As described above, the data obtained from the IEEE 1394 serial bus is added with the redundant code for improving the transmission quality, digitally modulated and wirelessly transmitted, and the transmitted signal is transmitted by the decoding device. Digital demodulation and data processing for improving the quality of received data are performed, and the signal subjected to the data processing is supplied to another IEEE 1394 serial bus.

At this time, the redundant code is added such that the data amount of the redundant signal to be added is variable according to the state of the spatial transmission path, that is, according to the quality of the received signal. The rate specifying signal for specifying the data amount is used as a rate setting signal for each circuit in the generation device.

Next, the operation of the main circuit portion relating to the operation of the rate designation control thus performed will be described in more detail. First, in the error correction coding circuit 61, for example, R
Two types of coding rates by the Reed-Solomon method such as S (315, 16) and RS (315, 32) (here, RS (315, 16) are for a data length of 315 bytes including parity data) An encoding circuit for Reed-Solomon code to which an error correction signal of 16 bytes of parity data is added is built in.

The rate designation in the error correction code is selected by a coding circuit of either one of the coding rates based on the rate designation signal supplied from the outside of the transmitter or generated inside the transmitter. It is used so that an error correction code is added to the input digital data to generate it as 315-byte digital data, and the data thus generated is intermittently read out by the intermittent read circuit 62.
Is supplied to.

A large-capacity memory (RAM: Random Access Memory) is built in the error correction coding circuit so that a code configuration with data interleaving can be performed. For example, one frame is 315 bytes. × The data of the number of frames required for the encoding described later is stored.

The stored data is read for each predetermined number of bytes and subjected to trellis coding and puncture coding. The rate at which the trellis coding and puncture coding are performed is the same as before the coding. Is represented by the number of values obtained by dividing the amount of data of the above by the amount of encoded data. For example, when the ratio of the amount of data after encoding to the amount of data before encoding is 1: 2, the encoding rate is 1 Expressed as / 2.

In this way, the coding for the coding rate in which the numerator and the denominator are given as predetermined integer values is performed by the trellis coding circuit for generating the trellis code from the large capacity memory. Data is intermittently read in units of several units, and the read data is intermittently encoded in units of bytes.

That is, the intermittent reading of the byte unit is
This is performed by the intermittent read circuit 62. For example, when the coding rate is 3/4, after reading 3 bytes of data, reading is stopped for a period of 1 byte (the number obtained by subtracting the numerator 3 from 4 in the denominator). Dummy "0" data is supplied. After that, similarly, the intermittent read operation of reading the 3-byte data and then the 1-byte dummy data is repeated, and the signal intermittently read by the intermittent read circuit 62 is supplied to the trellis encoding circuit 63.

The intermittently read signal thus supplied to the trellis coding circuit is trellis coded at a single coding rate, and the trellis coded signal is supplied to the puncture coding circuit 64. .

Here, when the above-mentioned single coding rate, for example, the coding rate is 1/2, data is erased from the convolutional code in accordance with a certain law, that is, punctured, so that an arbitrary coding rate is obtained. A code is generated, for example, 1/2, 3/4, 5/6, 7/8,
The puncture encoding circuit is composed of five types of encoding rates such as 9/10, and any one type of puncture encoding circuit is selected and used based on the above rate designation signal to perform puncture by processing in byte units. Encoding is performed and encoded into a continuous code, and the signal encoded into the continuous code is supplied to the frame array circuit 65.

The signal supplied thereto is stored as a signal formed in a frame having a predetermined size. Next, the size of the frame will be described. Here, a case will be described in which the size of the frame configuration is 37800 (1 frame 350 bytes × 108 frames) bytes of encoded data per data block regardless of the encoding rate.

The coded data frame length in that case is 35.
Although it is assumed to be 0 byte, 350 is a numerator 1, 3, 5, 7, of values indicated by 5 kinds of coding rates 1/2, 3/4, 5/6, 7/8, 9/10. 315, which is a common multiple of 9
Is multiplied by 10/9 which is the reciprocal of 9/10.

Here, out of 350 bytes of one frame, the data of the data frame length before encoding of 315 bytes is converted into the above-mentioned five kinds of codes of 1/2, 3/4, 5/6, 7/8 and 9/10. When encoded at the encoding rate, each of the encoded data is 630, 420, 378, 36.
It becomes 0,350 bytes of data.

The values are 630 (315 × 2/1),
420 (315 x 4/3), 378 (315 x 6 /
5) 360 (315 x 8/7), 350 (315 x 1)
0/9) and their number is 315
Is a common multiple of 1, 3, 5, 7, and 9, and is naturally an integer value.

Here, the number of 315 bytes has been described as an example, but when this number is not a common multiple of the numerator 1, 3, 5, 7, 9 described above, the number of encoded data is not an integer byte. It disappears and the data becomes an odd number of bytes.

Therefore, for example, when scrambling processing is performed by multiplying the code of M sequence having a different initial value in the data for each frame before encoding by a modulus of 2, for example, it is further encoded. 1 before encoding when doing
When the coding is completed with the coded data for one frame and the coding is performed without affecting the next frame, the coded data for one frame before the coding is an integer byte. At a certain time, the trellis coding process only needs to be performed on the data having an integer byte length, and the structure of the trellis coding circuit can be simplified accordingly.

The 35-byte data obtained by subtracting 315 bytes of the data frame length before encoding from the 350 bytes of the encoded data frame length is the data of data “0” before encoding and the data 315 before encoding. If the data is placed after the byte, the data after decoding can be easily handled, for example, it can be easily matched with Viterbi decoding described later.

Further, in the case of a configuration in which the number of frames included in one data block of encoded data is 108 frames, the number is a common multiple of 2, 4, 6, 8, and 10.
20 multiplied by the maximum of the five types of coding rates, that is, 9/10.

Therefore, 37800 (350
(Bytes × 108 frames) The number of data frames before encoding for generating a data block of bytes is as follows when the encoding rate is 1/2, 3/4, 5/6, 7/8, 9/10. 60, 90, 100, 105 for each
It is 108 frames.

That is, these values are 60 = 37800 × 1
/ 2 x 1/315, 90 = 37800 x 3/4 x 1/3
15, 100 = 37800 × 5/6 × 1/315, 10
5 = 37800 × 7/8 × 1/315, 108 = 378
00 × 9/10 × 1/315, each of which is the total number of data bytes before encoding, which is obtained by multiplying 37800 by the encoding rate.
It is divided by the data length 315 in the frame, and 37800/315 = 120 is 2, 4, 6, 8, 10
It depends on being a common multiple of.

If this 120 is not a common multiple, the number of data frames before encoding does not become an integer number of frames, and odd byte data is generated. However, the number of data frames before encoding is an integer. When it is a frame, the configuration of the circuit for calculating the error correction code is simple, and the error correction circuit in the receiving device can be similarly configured.

The trellis coding process is performed in this way, and the signal having a predetermined frame structure is digitally modulated and transmitted. Next, the modulation mapping for performing the multilevel modulation will be described.

The modulation mapping for performing the digital modulation is, for example, 4PSK, 16QAM, 64QAM,
The modulation mapping circuit 66 is capable of performing mapping for performing five types of digital modulation such as 256QAM and 1024QAM, and the modulation mapping circuit based on any one of these digital modulations is selectively used. At the same time, the digital data subjected to the modulation mapping is generated based on the rate designating signal and supplied to the frame synthesizing circuit 67.

Then, the frame synthesizing circuit 67 is supplied with the digital data supplied from the modulation mapping circuit 66 and the above rate designation signal, and these supplied signals are generated as a frame synthesizing signal,
The generated signal is obtained as a signal to which a frame synchronization signal or an ID signal (identification signal) is added as necessary.

In this way, the input circuit 5 shown here is used.
1, the two types of Reed-Solomon codes, the five types of trellis codes, and the five types of digital multilevel modulation numbers can be set independently, so that a total of 50 (2 ×
It is possible to select 5 × 5) encoding and modulation schemes.

As described above, a plurality of selectable coded and digitally modulated signals are generated by the generator and transmitted to the spatial transmission line, but the transmitted signals are received. The operation of the decoding device for receiving a signal transmitted with a plurality of selectable signals for is further described.

The signal received by the decoding apparatus is supplied to the frame decoder 71 shown in FIG. 3 as the R signal and the I signal from the OFDM receiver 54 shown in FIG. The frame decoder 7
In 1, the supplied signal is frame-decoded, the modulation-mapped data obtained by the frame decoding is supplied to the demodulation demapping circuit 72, and the rate designation signal obtained by the frame decoding is demodulated demapping circuit 72. It is supplied to the depuncture conversion circuit 73 and the error correction circuit 76.

In the demodulation demapping circuit 72, the 4P corresponding to the modulation system of the above-mentioned modulation mapping circuit 66 is used.
SK, 16QAM, 64QAM, 256QAM and 1
The demodulation demapping circuit 72 is configured to perform demodulation demapping according to the five types of 024QAM modulation systems. The demodulation demapping circuit 72 uses these modulation systems based on the rate designation signal obtained by frame decoding. One of the demodulation demapping circuits is selected and used to generate demodulation demapped output data, and the generated output data is supplied to the depuncture conversion circuit 73.

In the depuncture conversion circuit 73, some (for example, "0" data) dummy data is added to the data portion punctured (erased) by the puncture encoding circuit 64, and a single encoding rate is obtained. (For example, a coding rate of 1/2) is a circuit for decoding a signal supplied by being convolutionally coded as a code having the same form as that of the signal, and the dummy data added portion is In the Viterbi decoder 75 in, the data is restored to correct data.

That is, the depuncture conversion circuit 73.
Then, corresponding to the puncture encoding circuit 64, for example, 1 /
It is composed of a depuncture conversion circuit corresponding to five kinds of coding rates of 2, 3/4, 5/6, 7/8, and 9/10, and one of them is based on the above rate designation signal. The depuncture conversion circuit is selected and used to perform depuncture conversion by processing in byte units.

Since the data obtained by the depuncture conversion in this way is a sequence of intermittent data in byte units before puncturing encoding, if this is directly Viterbi decoded, accurate decoded data can be obtained. Absent. Therefore, the intermittent data is once stored in the RAM or the FIFO memory 74 for one data frame (315 bytes), then read as continuous data for each 350 bytes of the frame, and "0" data is inserted in the remaining 35 bytes. , Viterbi decoding circuit 75.

The Viterbi decoding circuit 75 is a circuit constructed by adding an additional circuit to the Viterbi decoding circuit corresponding to the same single coding rate as the modulation side (for example, coding rate 1/2), When the data supplied as the dummy data in the above depuncture conversion circuit is input to the metric calculation circuit inside the Viterbi decoder, the additional circuit generates a metric corresponding to “0” data in the metric calculation performed there. This is a circuit for performing an operation using the metric of the intermediate value of the metric corresponding to the "1" data, and the Viterbi decoding circuit 75 performs the Viterbi decoding of the depunctured transformed data.

In this way, one frame of data supplied to the Viterbi decoding circuit 75 is converted into one data frame 315.
Although 35 bytes of "0" data follow after the bytes are continuous, the portion of the "0" data works to automatically reset the contents of the path memory unit in the Viterbi decoding circuit.

That is, if "0" data is continuously supplied for the number of bits equal to or larger than the number of stages of the path memory, all values of the path memory become "0". For example, the path memory is 100
As for the stage, 35 bytes = 280 bits is sufficient.

When a decoding error occurs, the Viterbi decoding circuit must periodically reset the stored contents of the path memory in order to prevent a chain of errors, but when the path memory has 100 stages, 100 × the number of states ( 64 if 64 states
(00) registers must be reset at once, and the circuit scale for the reset becomes large. However, the reset by the method of supplying the data of "0" as described above is The circuit for that can be simplified and comprised.

The signal Viterbi-decoded as described above is supplied to the error correction circuit 76, in which two kinds of decoding rates corresponding to the two kinds of coding rates of the error correction coding circuit 61 described above are provided. It consists of an error correction circuit,
The error correction coding circuit 6 is based on the above rate designation signal.
The error correction is performed at the decoding rate corresponding to the coding rate selected in 1, and the decoded digital data thus obtained is supplied to the output signal processing circuit 56.

The rate designating signal is a small-capacity data signal in which the data amount of the redundant signal added is variable according to the state of the spatial transmission path, that is, according to the quality of the received signal. The setting for changing the data amount may be performed manually. However, in addition to the manual setting, the conventional small capacity bidirectional communication device is used or the data amount is changed by a modulation method such as BPSK. The signal may be digitally modulated and wirelessly transmitted from the decoding device to the generation device to automatically control the amount of data generated by the generation device.

In the method of transmitting a signal for varying the data amount by the BPSK modulation, or in the case of performing bus control using a small capacity bidirectional communication device, OFDM is used.
A reception status determination circuit (not shown) is provided in the reception unit 54, and the reception status determination circuit monitors the S / N ratio of the signal received by the OFDM reception unit 54, and according to the data error rate detected by the error correction circuit 76. Analyze the quality of the signal being received, determine the error correction coding rate, trellis coding rate, and modulation mapping method on the side of the generator that results in the largest amount of data that can be transmitted, and specify the rate based on these. Generate and transmit signals.

The small-capacity rate designation signal generated in this way is digitally modulated by a modulation system having a simple circuit structure such as BPSK and inexpensive, and is wirelessly transmitted from the decoding device to the generation device, and the generation device outputs the signal. In this way, optimal orthogonal frequency division multiplexing signals are transmitted according to the determination result of the reception status obtained in this way, and even if the reception status changes due to some cause, under that change status, It enables resetting of transmission parameters so that the most data can be transmitted.

As described above, while analyzing the quality of the received signal, the transmission parameter capable of transmitting the largest amount of data among the plurality of transmission parameters is analyzed by the decoding device, and the rate is designated based on the analyzed result. A signal is generated and transmitted to the generation device manually based on the generated rate specifying information or by using a small capacity communication device, and the generation device is based on the supplied rate specifying signal and is an OFDM signal. Is generated and radiated to the spatial transmission path, it is possible to configure a generation device and a decoding device that can transmit high-quality data with a high transmission rate.

Further, since the generation device and the decoding device respectively control the IEEE 1394 serial bus in the input signal processing circuit and the output signal processing circuit, for example, a video camera easily connected to the IEEE 1394 serial bus. It is possible to transmit a large-capacity digital video signal or the like by connecting a device on the information providing side such as the above and a different device such as a monitor TV connected to an IEEE 1394 serial bus via a wireless communication path.

In this case, the respective generators and decoders are synchronized with each other by a common system clock. However, the system clock information generates synchronizing signal information such as a pilot signal (not shown). It is also possible to supply from the device to the decoding device and synchronize the generation device and the decoding device, or another generation device and this decoding device.

In the generating device and the decoding device described here, it is assumed that OFDM (Orthogonal Frequency Division Multiplexing) wireless transmission is suitable for wirelessly transmitting large-capacity image data by the IEEE 1394 serial bus. I mentioned the capacity wireless transmission system.
The 94 serial bus is a data bus that enables bidirectional transmission.

[0148] Two sets of OFDM transmitters and receivers are required to perform OFDM wireless transmission of a large amount of data in both the downlink and uplink directions of bidirectional transmission. When a transmitter and a receiver are used, the price of those devices also increases, and, for example, an application for bidirectional transmission in which a video camera transmits a large amount of image data and simultaneously receives a large amount of data. Since there are not many examples at present, the transmission of large-capacity image data is limited in one direction, so that the circuit scale can be significantly reduced and the video signal transmission device can be constructed at a reduced price. .

In the thus configured generating device and decoding device, the signal designating the variable amount of the redundant signal added according to the quality of the received signal is encoded in a large number according to the reception situation. Orthogonal frequency division multiplexing signal transmission device with selectable modulation method, specify the maximum amount of data that can be transmitted from the reception status to the transmission side as error correction coding rate, trellis coding rate, and modulation mapping method on the transmission side. A decoding device generates the specified rate signal, and the generated small-capacity signal is, for example, BPS.
Digital decoding is performed by a modulation system having a simple and inexpensive circuit configuration such as K, and the decoding device wirelessly transmits it to the generation device. From the generation device, the optimum orthogonal frequency division multiplex signal is transmitted according to the reception status determination result. In addition to the above, even if the reception situation changes, it is possible to reconfigure the transmission parameters so that the largest amount of data can be transmitted under the change situation.

The bidirectional serial bus described in this example is not limited to the IEEE 1394 serial bus, and may be, for example, a home bus or a USB (Universal Serial Bus).
al Bus) and other bidirectional serial buses, and also for the IEEE 1394 serial bus, IEEE 1394a, IEEE 1394b.
Of course, it is also applicable to the upgraded version such as.

Furthermore, the intermittent reading method when performing trellis encoding is free, and it is also possible to read a small amount of data that is predetermined by a predetermined amount, assuming intermittent data, and the data read in such a manner can be used. The storage method in the data block is also arbitrary, and as described above, the intermittent data may be arranged in the order of reading, or the intermittent data may be collectively stored in the intermittent data area.

Furthermore, the generating device and the decoding device shown here radiate the orthogonal frequency division multiplexed signal generated by the generating device as a radio wave from the transmitting antenna to the spatial transmission path, and the radiated signal to the receiving antenna. However, the transmission line is not limited to the spatial transmission line, and any medium capable of transmitting the orthogonal frequency division multiplexing signal can be a wired medium, an optical cable, or a non-linear transmission medium. It is needless to say that a signal subjected to linearization processing such as FM modulation may be generated and transmitted, and in that case, the orthogonal frequency division multiplex signal generated by the above method is transmitted by the medium. The signal is supplied to the generation device and transmitted, and the reception of the transmitted signal is performed by the decoding device for receiving the signal transmitted by the medium.

The signal generated by the orthogonal frequency division multiplex signal generation device has good quality by utilizing the characteristics of the orthogonal frequency division multiplex signal, even when the reflected wave exists in the transmission medium. Even if the signal can be transmitted as an information signal and the level of the signal to be transmitted is lowered and the signal-to-noise ratio of the signal to be received is deteriorated, it is possible to select and code at multiple rates as described above. It is possible to realize an error signal resistant generation device and a decoding device with a relatively simple configuration by using a convertible trellis encoding method.

As described above, according to the orthogonal frequency division multiplex signal generation device and the orthogonal frequency division multiplex signal decoding device described here, the bidirectional serial bus is controlled in a pseudo manner, and the bidirectional serial bus is controlled. Of the information signals, input signal processing means for extracting information signals in the direction of the decoding device from the generation device, and error correction coding means for adding error correction signals to the information signals transmitted from these generation devices to the decoding device,
Trellis coding means for trellis-coding the error-correction additional information signal obtained by the error-correction coding means to obtain a trellis-coded signal, and the trellis-coded signal obtained by the trellis-coding means for a predetermined frame. Frame signal arranging means for generating as an array signal, modulation mapping means for generating a modulation mapping signal for multilevel modulation of the frame array signal generated by the frame signal arranging means, and modulation generated by the modulation mapping means A mapping signal and the error correction coding,
Frame signal synthesizing means for generating a frame synthesizing signal for transmitting a rate specifying signal for performing trellis coding and modulation mapping as an orthogonal frequency division multiplex signal, and a frame synthesizing signal generated by the frame signal synthesizing means It is possible to configure an orthogonal frequency division multiplex signal generation device having an orthogonal frequency division multiplex signal generation means for generating the orthogonal frequency division multiplex signal based on the above.

Further, the trellis coding means may be carried out as follows. In this method, p bytes are read out first for two integer values p and q in byte units, and then q bytes are empty. By means of an intermittent reading means for reading out the data of 1 to obtain an intermittent reading signal, a trellis coding means for trellis coding the intermittent reading signal obtained by the intermittent reading means to obtain a trellis coded signal, and the trellis coding means. Puncture coding means for puncturing the obtained trellis coded signal to obtain a puncture coded signal, and a frame for generating the puncture coded signal obtained by the puncture coding means as the predetermined frame array signal. The trellis coding in such a configuration is performed by the coding ray. There example 1 / 2,3 / 4,5 / 6,
Even when there are a plurality such as 7/8 and 9/10, the trellis coding is performed at one of the coding rates, and the puncture is simple in hardware configuration for the trellis coding at other coding rates. Since it can be performed by the encoding means, the configuration of the orthogonal frequency division multiplex signal generation device for modulating and transmitting the encoded signal obtained by specifying many encoding rates can be facilitated.

The demodulation of the orthogonal frequency division multiplex signal generated as described above is performed by a plurality of orthogonal frequency division multiplex signals generated by the orthogonal frequency division multiplex signal generation device and sent to the spatial transmission line. Orthogonal frequency division signal demodulation means for obtaining a carrier demodulation signal for a carrier wave, and frame decoding means for frame decoding the carrier demodulation signal obtained by the orthogonal frequency division signal demodulation means to obtain a frame array signal and a rate designation signal, Of the frame array signal obtained by the frame decoding means,
Demodulation demapping means for performing multilevel demodulation to obtain a multilevel demodulation signal, and decoding means for trellis decoding the multilevel demodulation signal obtained by the demodulation demapping means to obtain a decoded signal,
Alternatively, a depuncturing means for depuncturing the multilevel demodulated signal to obtain a depuncture signal, a decoding means for obtaining a decoded signal obtained by the depuncturing means, and a Viterbi decoding for the obtained decoded signal to obtain a Viterbi decoded signal Viterbi decoding means, error signal correction means for performing error signal correction processing on the Viterbi decoded signal obtained by the Viterbi decoding means to obtain an error-corrected information signal, and bidirectional serial bus signals are controlled in a pseudo manner. Thus, the orthogonal frequency division multiplex signal decoding device can be configured by including the output signal processing means for transmitting the information signal to the bidirectional serial bus.

Further, according to the orthogonal frequency division multiplex signal generation device and the orthogonal frequency division multiplex signal decoding device configured as described above, a large number of encodings are performed according to the reception status of the orthogonal frequency division multiplex signal decoding device. Of the error correction coding rate, trellis coding rate, and modulation mapping method on the transmission side, which can maximize the amount of data that can be transmitted depending on the reception situation, from the decoding device. After doing, for example, BP
The rate designating signal is digitally modulated by a modulation system having a simple and inexpensive circuit configuration such as SK, and is wirelessly transmitted from the decoding device to the generation device. From the generation device, optimum orthogonal frequency division multiplexing according to the reception status determination result is performed. In addition to setting transmission parameters so that signals can be transmitted, even if the reception status changes, it is possible to re-set the transmission parameters so that the largest amount of data can be transmitted under the changed status. Yes, the data of the IEEE 1394 serial bus and the like are transmitted to the OFDM generation device and the decoding device.
OFD of large capacity information signal data without using as a set
M wireless transmission is possible.

[0158]

According to the invention described in claim 1, in an orthogonal frequency division multiplex signal transmission device and a reception device in which a large number of coding parameters and modulation schemes can be selected according to a reception situation, an IEEE 1394 serial bus or the like is used. A low-cost configuration of an orthogonal frequency division multiplex signal generator that obtains a large amount of data from a serial data bus and transmits it in one direction without using two sets of OFDM transmitters and receivers for bidirectionally transmitted data Has the effect that can be provided.

Further, according to the invention described in claim 2, in the orthogonal frequency division multiplex signal transmission device and the reception device in which a large number of coding parameters and modulation schemes can be selected according to the reception situation, an IEEE 1394 serial bus or the like is used. It receives an OFDM signal in which a large amount of data is unidirectionally transmitted, and supplies the received signal to a bidirectional serial bus, without using two sets of OFDM transmitters and receivers for bidirectionally transmitted data. It is possible to provide the configuration of the orthogonal frequency division multiplex signal decoding device capable of performing at low cost.

[Brief description of drawings]

FIG. 1 is a schematic block diagram of an orthogonal frequency division multiplex signal generation device and an orthogonal frequency division multiplex signal decoding device according to an embodiment of the present invention.

FIG. 2 is a block diagram of an input circuit of the orthogonal frequency division multiplexing signal generation device according to the exemplary embodiment of the present invention.

FIG. 3 is a block diagram of an output circuit of an orthogonal frequency division multiplex signal decoding device according to an embodiment of the present invention.

FIG. 4 is a block diagram of an example of an input circuit in a conventional orthogonal frequency division multiplex signal transmitter.

FIG. 5 is a block diagram of an example of an output circuit in a conventional orthogonal frequency division multiplex signal reception device.

FIG. 6 is a block diagram of another example of the input circuit in the conventional orthogonal frequency division multiplex signal transmitter.

FIG. 7 is a block diagram of another example of the output circuit in the conventional orthogonal frequency division multiplex signal reception device.

FIG. 8 is a block diagram of a conventional orthogonal frequency division multiplex signal transmitter.

FIG. 9 is a block diagram of a conventional orthogonal frequency division multiplex signal reception device.

[Explanation of symbols]

1 Data input terminal 2 input circuits 3 clock divider 4 IFFT calculator 5 Intermediate frequency oscillator 5a Phase shifter 6 Digital quadrature modulator 7 D / A converter 8 frequency converter 9 Transmitter 11 Receiver 12 Frequency converter 13 Intermediate frequency amplifier 14 Carrier extraction and quadrature demodulator 15 Intermediate frequency oscillator 16 90 ° shifter 17 Synchronous signal generation circuit 18 LPF 19 A / D converter 20 FFT calculator 21 Output circuit 22 Demodulated signal output terminal 31 error correction coding circuit 32 Trellis coding circuit 33 Modulation mapping circuit 34 frame synthesis circuit 36 frame decoder 37 Demodulation demapping circuit 38 Viterbi Decoding Circuit 39 Error correction circuit 41 Trellis coding circuit 42 Puncture encoding circuit 45 Depuncture conversion circuit 46 Viterbi Decoding Circuit 50 Input signal processing circuit 51 Input circuit 52 OFDM transmitter 53 Spatial transmission line 54 OFDM receiver 55 Output circuit 56 Output signal processing circuit 61 error correction coding circuit 62 Intermittent readout circuit 63 Trellis coding circuit 64 puncture coding circuit 65 frame array circuit 66 Modulation mapping circuit 67 frame synthesis circuit 71 frame decoder 72 Demodulation demapping circuit 73 Depuncture conversion circuit 74 RAM 75 Viterbi decoding circuit 76 Error correction circuit

Claims (2)

[Claims] 1. An information signal to be wirelessly transmitted from a first bidirectional serial bus, and first and second redundancy information set for ensuring the transmission quality of the information signal are obtained, and the first signal is obtained.
And a first redundant signal and a second redundant signal are added to the information signal based on the second redundancy information to generate a transmission coded signal, and the generated transmission coded signal and the first and second redundancy signals. By orthogonally modulating the second redundancy information with a plurality of carriers, an orthogonal frequency division multiplexed signal is generated and radiated to a spatial transmission line, and the orthogonal frequency division division radiated to the spatial transmission line is generated. The transmission coded signal is decoded based on the first and second redundancy information obtained by receiving the signal, and the information signal obtained by the decoding is supplied to the second bidirectional serial bus. An orthogonal frequency division multiplex signal generator for generating the orthogonal frequency division multiplex signal in an orthogonal frequency division multiplex signal transmission and reception system configured as described above, wherein the information signal is based on the first redundancy information. Error correction coding means for adding an error correction code based on the second redundancy signal, and two integer values p and q based on the second redundancy signal.
Is set, p bytes of the error correction additional information signal are obtained based on the set integer values p and q, and the obtained p
Intermittent read means for obtaining an intermittent read signal by obtaining and arranging q bytes of empty data after the correction additional information signal of bytes, and trellis-encoding the intermittent read signal obtained by the intermittent read means. Trellis coding means for obtaining a trellis coded signal, and the transmission coded signal obtained by puncturing the trellis coded signal obtained by the trellis coding means to replace the empty data with the coded signal. An orthogonal frequency division multiplex signal generation device comprising: 2. An information signal to be wirelessly transmitted from a first bidirectional serial bus, and first and second redundancy information set for securing transmission quality of the information signal are obtained, and the first information is obtained.
And a first redundant signal and a second redundant signal are added to the information signal based on the second redundancy information to generate a transmission coded signal, and the generated transmission coded signal and the first and second redundancy signals. By orthogonally modulating the second redundancy information with a plurality of carriers, an orthogonal frequency division multiplexed signal is generated and radiated to a spatial transmission line, and the orthogonal frequency division division radiated to the spatial transmission line is generated. The transmission coded signal is decoded based on the first and second redundancy information obtained by receiving the signal, and the information signal obtained by the decoding is supplied to the second bidirectional serial bus. An orthogonal frequency division multiplex signal decoding apparatus for performing transmission of the orthogonal frequency division multiplex signal and reception of the orthogonal frequency division multiplex signal in the receiving system, comprising: Carrier demodulation means for demodulating to obtain a carrier demodulation signal for a plurality of carriers, and frame decoding and demodulation mapping of the carrier demodulation signal obtained by the carrier demodulation means to perform the first and second redundancy. Orthogonal frequency division signal demodulation means for obtaining information and the transmission coded signal; decoding means for depuncturing the transmission coded signal based on the second redundancy information and performing Viterbi decoding to obtain a decoded signal; Error signal correction means for performing error correction processing of the decoded signal based on the first redundancy information to obtain the information signal to be supplied to the second bidirectional serial bus. An orthogonal frequency division multiplex signal decoding device characterized by: