JP2003023344A - Pulse waveform regulation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a pulse waveform regulation circuit with which a delay quantity and a duty ratio can be regulated in the same circuit, circuit scale is comparatively small and the variation of output pulses is reduced. SOLUTION: This circuit is provided with a selector 5 for selecting and outputting two kinds of delay pulses respectively showing a prescribed delay quantity in respect to an input pulse from the output of a plurality of serially connected delay cells 1-4, an AND gate 6 for inputting two kinds of selected delay pulses, a latch circuit 7 to be operated with one of two kinds of delay pulses as a set signal and the other delay pulse as a reset signal, and a selector 9 for selecting and outputting either the output of the AND gate 6 or output of the latch circuit 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse waveform adjusting circuit, and more particularly to a pulse waveform adjusting circuit for adjusting a pulse delay amount and a duty ratio.

[0002]

2. Description of the Related Art The structure of a conventional pulse waveform adjusting circuit circuit for adjusting a delay amount and a duty ratio is shown in a block diagram of FIG. In FIG. 15, reference numeral 31 is a duty ratio adjusting circuit, and reference numeral 32 is a delay amount adjusting circuit. As shown in FIG. 15, conventionally, the pulse delay amount and the duty ratio are adjusted by the duty ratio adjusting control signal in the duty ratio adjusting circuit 31 having a duty ratio adjusting function. Is adjusted to adjust the duty ratio of the pulse, and the delay amount is adjusted by the delay amount adjustment control signal in the delay amount adjusting circuit 32 having a delay amount adjusting function in the subsequent stage for the pulse. .

The necessity of having a two-stage circuit configuration as described above will be specifically described with reference to FIG. (1) of FIG. 16 is an input pulse. In the conventional method, the duty ratio is changed by delaying either the rising edge or the falling edge. Therefore, when narrowing the pulse width, the rising edge is delayed to narrow the pulse width as shown in FIG. 16 (2). At this time, the generated pulse is synchronized with the trailing edge of the input pulse. Further, when it is desired to thicken the pulse width, the fall is delayed to thicken the pulse width as shown in FIG. At this time, the generated pulse is synchronized with the rising edge of the input pulse.

In this way, it is inevitable that the change timing of the generated pulse is not constant with respect to the input pulse. For example, when the phase relationship with a plurality of duty ratio adjusting pulses is important, the duty ratio It is necessary to further change the change timing with respect to the adjusted pulse, that is, to adjust the delay amount. This delay amount adjustment is performed by a delay amount adjusting circuit 32 having a delay amount adjusting function, which is provided at a subsequent stage of the duty ratio adjusting circuit 31 having a duty ratio adjusting function.
Is performed to compensate the phase of the duty ratio adjusting pulse. For example, (4) and (5) in FIG.
The delay amount is adjusted so that (2) and (3) of 6 are synchronized with the rising edge of the input pulse.

In the above-mentioned configuration, each circuit for adjusting the delay amount and the duty ratio and the wiring connecting the circuits are present, so that the variation in the pulse after the delay amount and the duty ratio is large. turn into. Further, a duty ratio adjusting circuit 3 having a duty ratio adjustment
1 and the delay amount adjusting circuit 32 having the delay amount adjustment respectively have a delay element, which is not very efficient in terms of circuit integration. In order to improve these problems, the present invention aims to perform simultaneous adjustment of the delay amount and the duty ratio, which are not available in conventional adjustment methods.

[0006]

As described above, in the conventional pulse waveform adjusting circuit for adjusting the duty ratio and the delay amount of the pulse, it is necessary to provide the circuits for adjusting the duty ratio and the delay amount, respectively. There has been a problem that the number of elements increases and the circuit scale increases, and the pulse variation after adjustment increases. The present invention is
An object of the present invention is to solve this problem by a relatively simple method and to realize a pulse waveform adjusting circuit in which delay amount adjustment and duty ratio adjustment can be performed in the same circuit, the circuit scale is relatively small, and output pulse variations are small.

[0007]

In order to achieve the above object, the present invention provides a pulse waveform adjusting circuit for adjusting a delay amount and a duty ratio of an input pulse, wherein a plurality of delay elements for delaying the input pulse by a predetermined time are provided. Two types of delay pulses, which are connected in series and each have a predetermined delay amount with respect to the input pulse, are selected and output from the outputs of the plurality of delay elements for rising delay amount setting and falling delay amount setting. Delay means, gate means for inputting two kinds of delay pulses output from the delay means, and latch means for operating one of the two kinds of delay pulses output from the delay means as a set signal and the other as a reset signal And output selecting means for selecting and outputting either the output of the gate means or the output of the latch means. As a result, the delay amount and duty ratio of the input pulse can be adjusted with the same circuit, and it is possible to realize a pulse waveform adjustment circuit having a small circuit scale and a small variation in output pulse.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A pulse waveform adjusting circuit according to the present invention will be described in detail below with reference to the accompanying drawings.

FIG. 1 is a block diagram of an embodiment of a pulse waveform adjusting circuit of the present invention capable of adjusting a duty ratio and a delay amount by independently adjusting delay amounts of a rising edge and a falling edge of a pulse. It is a figure. In FIG.
Reference numerals 1 to 4 are delay cells, reference numerals 5 and 9 are selectors, reference numeral 6 is an AND gate, reference numeral 7 is a latch circuit, and reference numeral 8 is a comparator. The delay cells 1 to 4 have a function of delaying an input pulse.

The node names in FIG. 1 are given as IN, N01, N0.
2, N03, ..., N0m, N11, N12, N21, N
22, N23, 0UT. Nodes N01, N02,
The delay amounts of N03, ..., N0m are, for example, 1 (ns), 1 (ns), 2 (ns), 3 (ns), respectively, with respect to the input pulse, if one delay cell delays by 1 (ns).
..., m (ns). In the description below, the delay of one delay cell is 1 (ns).

The selector 5 selects two kinds of pulses from among m kinds of pulses having different delay amounts delayed by the delay cell. An example of the internal circuit of the selector 5 is shown in FIG.
The select signals S0 and S1 of the selector 5 are the rising delay amount and the falling delay amount of the pulse set by the user from the outside. The data amounts of the select signals S0 and S1 are both nbit and control N11 and N12, respectively. Here, there is a relation of m = 2n between the variable m representing the type of the delayed pulse and the variable n of the nbit select signals S0 and S1 of the selector 5. In addition, the select signal S
For example, when n = 4, that is, when the delay amount is set by 4-bit data from the outside, S0 (S1) = 0011b means that the delay amount is 0 or S1. , The delay amount is 3 (ns) and S0
When (S1) = 1111b, the delay amount is 15 (ns)
Is. When the values of S0 and S1 set from the outside are 0011b and 1111b, respectively, the output N of the selector 5
In N11, N03, which is the input pulse delayed by 3 (ns), is selected, and in output N12, the input pulse is 15 (ns).
The delayed N015 is selected.

The AND gate 6 is used to narrow the width of the pulse by using the two types of pulses selected by the selector 5 or to delay the pulse without changing the duty ratio of the pulse. FIG. 3 shows how the width of the pulse is narrowed, and FIG. 4 shows how the pulse is delayed without changing the duty ratio of the pulse. First, how the pulse width narrows will be described with reference to FIG. The selected two pulses are designated as output N11 and output N12, and N03, which is obtained by delaying the input pulse by 3 (ns), is selected at the output N11, and the input pulse is 5 at the output N12.
(Ns) The delayed N05 is selected. Thus, when the two pulses of FIG. 3 are selected, AN
The output N21 of the D gate 6 is as shown by N21 in FIG. 3, and if the pulse width of the input pulse is 5 (ns), the pulse width of the output N21 is reduced to 3 (ns).

Next, the manner of delay without changing the duty ratio of the pulse will be described with reference to FIG. When the selected two pulses are output N11 and output N12 and a pulse having the same delay amount as the input pulse (a delay amount of N11 and a delay amount of N12 are equal) is selected, for example, set delay amounts S0, S
By setting both values of 1 to 0101b, the selector 5
When the two types of pulses selected in step 2 have both delay amounts of 5 (ns) as shown in N11 and N12 of FIG. 4, the output N21 of the AND gate 6 does not change in pulse width and is delayed from the input pulse. The amount is a pulse of 5 (ns).

The latch circuit 7 is used to widen the pulse width from the two types of pulses selected by the selector 5. A circuit example of the latch circuit 7 is shown in FIG. The node names in FIG. 5 are L1, L2, L3, and L4, and the timing charts of the nodes are shown in FIGS. 6 and 7. FIG. 6 is a timing chart when the selected two kinds of pulses have overlapping portions, and FIG. 7 shows the timing chart when there are no overlapping portions. The reason why the latch circuit is used to widen the width of the pulse is to cope with the separation when there is no overlapping portion of the selection 2 pulses (N11 and N12 in FIG. 7) as in FIG. Separation means that a generated pulse exists and is divided like L4 in FIG.

L4 is equivalent to the OR logic of N11 and N12, and the part missing due to the separation is N1.
1 and N12 are complemented by L3 which is the output of the latch circuit having the relationship of SET / RESET. This will be specifically described with reference to FIGS. 6 and 7. N11 is controlled by the rising delay amount setting value S0 of the input pulse, and N12 is controlled by the falling delay amount setting value S1 of the input pulse. When widening the pulse width, as shown in FIG. The amount of delay is N
Since it is set to be larger than the delay amount of 11, only these cases will be described.

When two pulses such as N11 and N12 in FIGS. 6 and 7 are selected, L1 and L2 are as shown in the figures. L3 is set at the falling edge of L1 and reset at the falling edge of L2. L4 is N11 and N1
Since it is equivalent to the OR logic of 2, it becomes as shown in the figure. Therefore, N22, which is the output of the latch circuit 7, becomes O of L3 and L4.
It becomes as shown in the figure by R logic, does not cause separation,
The pulse width widens.

Further, N11 and N12 in FIG.
When it changes to H, it may oscillate inside the latch circuit. Therefore, FIG. 8 shows an example of an oscillation countermeasure circuit of the latch circuit. The difference between FIG. 8 and FIG. 5 is that the output N23 of the comparator 8 for determining whether to widen or narrow the pulse width of FIG.
This is the point where the gate (3 input NAND gate 10 in FIG. 8) is applied at.

In the timing chart shown in FIG. 9, N1
A specific description will be given of a situation in which no oscillation occurs even with an input such as 1, N12 in which oscillation may occur. Further, N23 at this time represents a time when the duty ratio is widened by "L",
It is assumed that "H" represents a case where the duty ratio is reduced or a case where the duty ratio is constant and delayed (N23).
(See the description of the comparator 8 described later). In FIG. 9, it is assumed that N11 and N12 rise at the same time. Since N23 at this time is "H", N23 'becomes L, and L23 of the latch circuit shown in FIG.
3 is always "H" and does not oscillate. See also FIG.
0 and FIG. 11 show the operation when the pulse width is widened and the pulse width is narrowed, respectively. From these results, it can be seen that there is no adverse effect due to the latch circuit shown in FIG.

The comparator 8 compares the rising delay amount and the falling delay amount of the pulse arbitrarily set by the user from the outside, and determines whether to narrow or widen the pulse width.
For example, the rising delay amount and the falling delay amount of the pulse externally set by the user are 4 bits, and 011
If it is 1b and 0010b, the comparator 8 compares the size of each 4-bit data and determines that the pulse is thinned. For example, if the comparator 8 outputs "H" to narrow the pulse, the output of the comparator 8 when the pulse is expanded becomes "L". At this time, if the set delay amount is the same on the rising edge and the falling edge, the output of the comparator 8 is set to "H".

The selector 9 outputs a pulse output from the AND gate 6 having a narrow pulse width or a pulse delayed only without changing the duty ratio and a pulse output from the latch circuit 7 having a wide pulse width. Make a choice. The select signal S2 of the selector 9 is supplied to the comparator 8
Output N23. For example, when the select signal S2 is "H", the output from the AND gate 6 is selected, and when the select signal S2 is "L", the output from the latch circuit 7 is selected.

That is, the comparator 8 selects the output from the AND gate 6 by setting the select signal S2 (N23) to "H" when the set delay amount is S0≥S1, and when the set delay amount is S0 <S1. Select signal S2 (N23)
Is set to "L" to select the output from the latch circuit 7. This allows the comparator to determine whether the duty ratio is to be increased or decreased based on the relationship between the set rising delay amount and falling delay amount, and selects and outputs the AND output data or the latch circuit output data with that signal. To reflect. By these, the rising / falling edge of the input pulse can be independently delayed, and a pulse with a adjusted duty ratio can be generated. In this way, the duty ratio can be adjusted, but the delay amount can be adjusted at the same time by substituting a value in which the delay amount from the input pulse is added into the rising delay amount and the falling delay amount set by the user. Therefore, a circuit having a delay amount adjusting function, which is required in the conventional structure, is not required.

FIGS. 12, 13 and 14 are timing charts of the pulse waveform adjusting circuit shown in FIG. Figure 1
2 is a timing chart when expanding the pulse,
FIG. 13 is a timing chart when the pulse is narrowed, and FIG. 14 is a timing chart when the pulse is delayed without changing the duty ratio. Here, the data width of the delay amount externally set by the user is 4 bits, and the delay amount is 1 ns with respect to the set value. That is, the set value is 0110b and the delay amount is 6 ns.

In FIG. 12, the set value of the rising delay amount is 00.
10B is a timing chart when the set value of the falling delay amount is 0100b. In S0 and S1 of FIG. 1, the user sets the set value of the pulse rise delay amount from the outside by 0010.
b, and when the set value of the falling delay amount is set to 0100b, the output nodes N11 and N12 of the selector 5 output from FIG.
As shown in 2, the original pulse is 2 (ns), 4
(Ns) delayed pulse is output, and AN of the subsequent stage is output.
A pulse as shown in FIG. 12 is obtained from the output node N21 of the D gate 6 and the output node N22 of the latch circuit 7, respectively. Further, at this time, the rising delay amount of the pulse set by the user (0010
b), it is determined that the pulse width is increased from the falling delay amount (0100b), and “L” is output as the output (FIG. 1).
2 N23). The output signal from the comparator 8 is used as a select signal in the selector 9. Since the select signal is "L", the output from the latch circuit 7 is selected.
Therefore, it is possible to obtain a pulse in which the rising edge is delayed by 2 (ns), the falling edge is delayed by 4 (ns), and the H section of the pulse is widened by 2 (ns), as shown in FIG. 12, from the output signal OUT. .

FIG. 13 shows that the set value of the rising delay amount is 01.
10B is a timing chart when the set value of the trailing delay amount is 0001b. In S0 and S1 of FIG. 1, the user sets the set value of the pulse rising delay amount to 011 from the outside.
0b and the set value of the falling delay amount are set to 0001b, the output nodes N11 and N12 of the selector 5 are connected to the output nodes N11 and N12 of FIG.
As shown in 3, the original pulse is 6 (ns), 1
(Ns) delayed pulse is output, and AN of the subsequent stage is output.
Pulses as shown in FIG. 13 are obtained at the output node N21 of the D gate 6 and the output node N22 of the latch circuit 7, respectively. Further, at this time, the comparator 8 of FIG. 1 judges that the pulse width is made narrower than the rising delay amount (0110b) and the falling delay amount (0001b) of the pulse set by the user, and outputs “H” as an output (N23 of FIG. 13). ). The output signal from the comparator 8 is used as a select signal by the selector 9. Since the select signal is "H", the output from the AND gate 6 is selected. Therefore, the output signal O
As shown in FIG. 13, a pulse in which the rising edge is delayed by 6 (ns) and the “H” section of the pulse is narrowed by 5 (ns) can be obtained in the UT.

In FIG. 14, the set value of the rising delay amount is 00.
11b is a timing chart when the set value of the falling delay amount is 0011b. In S0 and S1 of FIG. 1, the user sets the pulse rising delay amount setting value from outside by 001.
1b and the set value of the fall delay amount is set to 0011b, the output nodes N11 and N12 of the selector 5 are connected to the output nodes N11 and N12 of FIG.
As shown in FIG. 4, a pulse in which the rising edge and the falling edge of the original pulse are delayed by 3 (ns) is output, and is output to the output node N21 of the AND gate 6 and the output node N22 of the latch circuit 7 in the subsequent stage, respectively. A pulse as shown in FIG. 14 is obtained. At this time, the comparator 8 in FIG.
b) Based on the falling delay amount (0011b), it is determined that the duty ratio of the pulse is not changed, and "H" is output as an output (N23 in FIG. 14). The output signal from the comparator 8 is used as a select signal by the selector 9,
Since the select signal is "H", the output from the AND gate 6 is selected. Therefore, as shown in FIG. 14, it is possible to obtain a delayed pulse for the output signal OUT with a delay of 3 (ns) both at the rising edge and the falling edge of the pulse and without changing the duty ratio.

As described above, the pulse waveform adjusting circuit of the present invention creates a plurality of pulses having different delay amounts from the input pulse in advance and selects one of the generated pulses that meets the output pulse condition. Thus, the rising edge and the falling edge can be adjusted independently, which makes it possible to adjust the delay amount and the duty ratio at the same time. The adjustment amount is left to the set values of the rising delay amount and the falling delay amount from the input pulse input from the outside by the user, and can be set arbitrarily and independently.

In the conventional circuit, it is necessary to adjust the delay amount at a later stage with respect to the pulse whose rising and falling delay amounts are adjusted in the circuit having the duty ratio adjusting function. With the above configuration, it is not necessary to separately provide a circuit having a duty ratio adjusting function and a circuit having a delay amount adjusting function, so that the circuit scale such as the number of delay elements can be reduced. Further, since it is not necessary to separately provide a circuit having a duty ratio adjusting function and a circuit having a delay amount adjusting function, it is possible to reduce the number of wirings between the circuits, and in combination with the reduction in the number of delay elements, variation due to wiring, element It is possible to reduce the variation due to the above, and it is possible to realize a pulse waveform adjusting circuit with less variation in the output pulse.

[0028]

As described above, according to the first aspect of the present invention, in the pulse waveform adjusting circuit, the output of the delay element in which a plurality of delay elements for delaying the input pulse for a predetermined time are connected in series is changed to the input pulse. On the other hand, delay means for selecting and outputting two kinds of delay pulses each showing a predetermined delay amount,
The gate means for inputting the selected two kinds of delay pulses, the latch means for operating one of the two kinds of delay pulses as a set signal and the other as a reset signal, and either the output of the gate means or the output of the latch means are provided. An output selecting means for selecting and outputting is provided. With this, when adjusting the input pulse duty ratio, the delay amount can be adjusted at the same time by adjusting the rising and falling delays of the pulse independently. The set value of the amount can be set arbitrarily and independently. In addition, with one configuration, it is possible to adjust the duty ratio and the delay amount.
By combining these two functions, it is not necessary to separately provide a duty ratio adjustment circuit and a delay amount adjustment circuit as in the past, and the number of delay elements existing in each circuit can be reduced and the circuit scale can be reduced. Further, further integration is possible, and variations due to elements and wiring are reduced.

The invention according to claim 2 of the present invention is characterized in that the delay amounts of the two kinds of delay pulses output from the delay means can be independently set from the outside. This makes it possible to adjust the pulse by easily and independently setting the delay amounts of the rising edge and the falling edge of the pulse from outside.

The invention of claim 3 of the present invention is characterized by comprising an output selection determining means for determining the output selection of the output selecting means from the delay amounts of the two types of delay pulses. As a result, a pulse suitable for the operator's intention can be realized only by setting the delay amount, and a pulse waveform adjusting circuit that is easy to operate can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram of a pulse waveform adjusting circuit of the present invention.

FIG. 2 is an internal circuit diagram of a selector of the pulse waveform adjustment circuit of FIG.

FIG. 3 is a timing chart showing how the pulse width is narrowed by the pulse waveform adjusting circuit of FIG.

FIG. 4 is a timing chart showing how the pulse waveform adjusting circuit of FIG. 1 delays without changing the duty ratio.

5 is a circuit diagram of an example of a latch circuit of the pulse waveform adjustment circuit of FIG.

6 is a timing chart of each node of the latch circuit shown in FIG.

7 is a timing chart of each node of the latch circuit shown in FIG.

8 is a circuit diagram of another example of a latch circuit of the pulse waveform adjusting circuit of FIG.

9 is a timing chart of each node of the latch circuit shown in FIG.

10 is a timing chart of each node of the latch circuit shown in FIG.

11 is a timing chart of each node of the latch circuit shown in FIG.

12 is a timing chart of each node of the pulse waveform adjustment circuit of FIG.

13 is a timing chart of each node of the pulse waveform adjustment circuit of FIG.

14 is a timing chart of each node of the pulse waveform adjustment circuit of FIG.

FIG. 15 is a block diagram of a conventional pulse waveform adjustment circuit circuit.

FIG. 16 is a timing chart of a conventional pulse waveform adjustment circuit circuit.

[Explanation of symbols]

1 to 4 ... Delay cell, 5, 9 ... Selector, 6 ... AND
Gate, 7 ... Latch circuit, 8 ... Comparator, 10 ... 3
Input NAND gate, 31 ... Duty ratio adjusting circuit, 3
2 ... Delay amount adjusting circuit.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Hiroyasu Tagami             134, Kobe-cho, Hodogaya-ku, Yokohama-shi, Kanagawa               Sony LSI Design Stock Association             In-house F term (reference) 5J001 BB03 BB08 BB09 BB12 CC03                       DD07 DD08 DD09

Claims (3)

[Claims] 1. A pulse waveform adjusting circuit for adjusting a delay amount and a duty ratio of an input pulse, wherein a plurality of delay elements for delaying the input pulse for a predetermined time are connected in series, and the input from the output of the plurality of delay elements. Delay means for selecting and outputting two kinds of delay pulses each having a predetermined delay amount for the pulse for setting the rising delay amount and for setting the falling delay amount, and two types of delays output from the delay means. Either gate means for inputting a pulse, latch means for operating one of two types of delayed pulses output from the delay means as a set signal and the other as a reset signal, and output of the gate means or output of the latch means And a pulse output adjusting circuit for selecting and outputting the pulse waveform. 2. The pulse waveform adjusting circuit according to claim 1, wherein the delay amounts of the two types of delay pulses output from the delay unit can be independently set from the outside. 3. The pulse waveform adjusting circuit according to claim 1, further comprising an output selection determining unit that determines an output selection of the output selecting unit based on a delay amount of the two types of delay pulses.