JP2003022192A - Compression programming method using block sort compression algorithm, processor system using the programming method and method for information distribution service - Google Patents

Abstract

PROBLEM TO BE SOLVED: To encode a program code by compression so as to decode it from addresses branched at random and to transmit information written by a virtual machine language independent from architecture. SOLUTION: When a program code is encoded by compression so as to store relation between a current aligning position number and a preceding aligning position number by using block sort compression algorithm, the program code can be immediately decoded from addresses branched at random by a branching instruction. A compressed virtual machine code string is directly interpreted and executed at decoding. Thereby, the program code can be compressed by the block sort compression algorithm having a high compression ratio almost equal to that of text data and information can be exchanged without depending on the architecture.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a program code compression / decompression technique, and is particularly suitable for efficiently compressing an executable program code and executing the compressed instruction code while decompressing it. Compression programming method, compressed program code information providing method, and processor system using the compression programming method.

[0002]

2. Description of the Related Art In an embedded processor used for a portable device, a controller, etc., the available memory capacity of the program is small because the memory capacity to be incorporated is limited. This is also because secondary storage devices such as hard disks cannot be used. Therefore, a processor architecture that is as code-efficient as possible is desired.

For example, for a processor having an instruction code architecture with a length of 32 bits, half of that is 16
Some have an instruction code for shortening the bit length. The instruction code and the like are described in the following documents (Segars, S., Clarke, K. a.
nd Goodge, L .; : Embedded c
ontrol problems, Thumb an
d the ARM7TDMI, IEEE Micr
o, vol. 15, no. 5, pp. 22-
30, Oct. 1995).

As in this example, when the instruction code is expanded and converted into a decodable instruction code at the time of execution, the compressed code is stored in the cache memory, so that the apparent cache capacity is increased and the cache miss is reduced. There is an effect that is done. However, since instructions that can be shortened are limited to a partial instruction set, a large compression effect cannot be expected.

In another proposal, compressed opcodes are decompressed by the time they are loaded into cache memory, but without the benefit of mitigating cache misses. In this case, since the branch destination address is deviated between the decompression coded cache memory and the compression coded main memory, the instruction code is converted so as to branch to the compression coded branch destination address. The method of doing is proposed.

Further, the compressed target branch address is complicated because it may be an intermediate address of the compressed code, and the branch target address is usually limited to the head of the compressed code. In addition, it is also troublesome when the compressed code crosses the boundary of the access unit, so it has been proposed to add a boundary restriction. Here, regardless of which method is used before or after loading the decompression of the compressed code into the cache memory, the conventional instruction decoder can be used as it is after decompression, so that it is not necessary to change the programming model.

[0007]

As described above, since the program code has a branch instruction, it must be possible to decompress the compressed code at a random position. The LZ compression method (A Universal Algo) proposed by Ziv and Lempel in 1977 is commonly used for compressing serial data such as text and files.
rithm for Sequential Data
Compression, IEEE Trans.
on Information. Theory, vol. I
T-23, no. 3, pp. 337-349,
May 1977) is a system in which a part of flowing data is used as a window to dynamically refer to itself by a pointer as a dictionary, and therefore random expansion cannot be performed, and it is difficult to use for compressing program codes.

Therefore, in order to improve the compression efficiency of the program code, it has been considered to use the Huffman coding system having a static dictionary over the entire program. The Huffman coding method is described in the following document (Kozuc.
h, M. and Wolfe, A .; : Comp
region of Embedded System
m Programs, Proc. of ICC
D'94, pp. 270-277, 1994).

However, since the Huffman code has a variable length that shortens the code that frequently appears, the implementation method of the code having a long code length is complicated. Therefore, it is necessary to consider a code system that has been modified so as not to exceed a certain length. Further, since the Huffman code is a prefix code (a code having a condition that no code word matches a subsequence starting from the head of another code word), it cannot be decoded unless processed in order from the head of the code word. That is, since it cannot be decoded from the middle position of the branched code, it must be the beginning of the code word. These reduce the compression efficiency of the code. Compared to the Huffman code,
There is an Arithmetic code that makes it easy to form a variable length code. Its application to program code compression has also been proposed in the following document (Lekatsa).
s, H .; and Wolf, W.D. : SAMC:
A Code Compression Algori
thm for Embedded Processo
rs, IEEE Trans. Computer-
Aided Design of Integrate
d Circuits and Systems, v
ol. 18, no. 12, pp. 1689-1
701, Dec. 1999).

However, in order to realize the branch, the data is handled in block units having byte boundaries so that branching is performed in byte units. Therefore, a compressed code dedicated to branching is provided. Therefore, the compression efficiency originally possessed by the Arithmetic code is not a little lost.

Another feature of program code is
It is divided into an opcode and an operand part, and the appearance pattern and frequency of both are different. In general, the pattern of the operation code portion appears repeatedly, but the pattern of the operand portion takes various forms in contrast to this, and therefore the pattern as the instruction code tends to be various. This reduces the compression efficiency of the code.

In a high performance architecture, in order to maximize the parallelism, VLIW (Very Lon) is used.
g Instruction Word) may be used. The disadvantage of this method is that the instruction word length is long and the number of invalid instruction fields is large, resulting in poor code efficiency, resulting in a large program code size.

By the way, the program code is not always written in the target machine language. It may be written in intermediate code, such as the Java language, and run on the target architecture via its interpreter or compiler. Web browsers and the like are often used in order to be able to display whatever machine the receiving side that processes the transmitted display information is using.

That is, if the program code size written in the intermediate code is large, it becomes a communication bottleneck.
In such a case, code compression is required. Interpreted execution of intermediate code by the interpreter is inherently slower than direct execution of compiled code. Therefore, if the intermediate code is compressed / transmitted, decompressed on the receiving side and interpreted and executed, a double load occurs. It is desired to solve the above problems.

A first object of the present invention is to provide a compression programming method using a block sort compression algorithm and a processor system using the compression programming method.

A second object of the present invention is to provide a highly efficient compression method even for VLIW format program code, which tends to have a large program size.

[0017]

[Means for Solving the Problems] In order to solve the above problems,
The method described below may be mentioned.

For example, Huffman and Arithme
Consider another compression scheme instead of tic encoding. Recently L
Another compression method called a block sort compression method, which is comparable to the compression rate of the Z compression method, has been of great interest theoretically because of its high compression rate.

The block sort compression method is described in the following document (Fenwick, PM:
Blocksorting text compres
sionFinal report, Technic
al Report 130, Department
of Computer Science, Uni
Versity of Auckland, Auck
land, New Zealand, 1996).

The block sort compression method creates a cyclic shift (or rotation shift) sequence for the entire text data, arranges all the cyclic shift sequences by lexicographical ordering, and arranges them. It will be transformed. The last column is characterized by the fact that the same text symbols are likely to be consecutive, so the text data can be compressed by encoding the consecutive length.

Further, in the principle of decoding block-sort compressed data, a method of decoding at random (from anywhere) can be derived, so that it can be applied to a method of compressing program code. In the block sort compression method,
The compression ratio can be increased as a whole by aligning all the program codes and efficiently encoding them together. In order to immediately decode the compressed program code encoded by the block sort compression method, the compression encoding method is adopted from the beginning while preserving the positional relationship before and after the alignment.

Further, in the VLIW system, by arranging each of the parallel-divided fields, the compression is efficiently performed without impairing the original parallelism of the VLIW. In the compression of the intermediate code string, high-speed execution is realized by directly deciphering the instruction simultaneously with the decompression.

In addition to the above method for solving the above problems,
Further, according to the present invention, in a compression programming method, a step of setting a plurality of codes corresponding to a plurality of commands constituting a certain arbitrary program, a step of arranging the plurality of codes using a compression algorithm, arranging the plurality of codes, and compressing and encoding them. It is to provide a compression programming method characterized by including.

Further, according to the present invention, in a compression programming method using a compression algorithm, a field of one instruction is divided into a plurality of instruction blocks for an instruction format having a plurality of instruction fields, and each divided block position is divided. Arranging after compression, a step of arranging the plurality of instruction code strings formed by the alignment after mixing and combining the plurality of instruction code strings, and the plurality of arranged instruction codes It is an object of the present invention to provide a compression programming method characterized by including a step of compression-encoding a column and a step of decoding in parallel for each divided block at the time of decoding.

Further, according to the present invention, in a processor system using a compression programming method, a setting unit for setting a plurality of codes corresponding to a plurality of commands constituting a certain arbitrary program, and a plurality of codes are set by using a compression algorithm. It is to provide a processor system characterized by comprising a compressing unit for arranging and arranging after compression.

Further, according to the present invention, in a processor system based on a compression programming method, for an instruction format having a plurality of instruction fields, a field of one instruction is divided into a plurality of instruction blocks, and each divided block position is divided. An aligning unit for aligning after compression, a unit for arranging the plurality of instruction code strings formed by the alignment after mixing the plurality of instruction code strings, and arranging the plurality of instruction code strings, and the plurality of arranged instructions. It is an object of the present invention to provide a processor system including a compression unit that compresses and encodes a code string, and a decoding unit that performs parallel decoding for each divided block when decoding.

Further, according to the present invention, in an information communication system for controlling transfer of information such as a program code, there is provided a transmitting side terminal provided with an information transfer section for controlling information transfer of a program code string compressed by a block sort compression algorithm. Information further comprising: a receiving side terminal for receiving the information-transferred program code string, wherein the receiving side terminal can directly perform decoding and interpretation of the program code string. It is to provide a communication system.

Furthermore, the present invention is a program code information distribution service method, wherein a receiving side terminal receives a program code compressed by a block sort compression algorithm distributed from a transmitting side terminal, After the reception is completed, the reception side terminal notifies the transmission side terminal of the reception completion, and the step of directly decoding and interpreting the compressed program code at the reception side terminal is included. This is to provide a method of information distribution service.

Moreover, the present invention includes a plurality of storage elements,
An interpreter that includes a processor that operates using a compression algorithm, has a compression instruction area in which the plurality of storage elements store a compressed program code, and directly decodes the program code by the compression algorithm and can interpret and execute the program code. It is to provide a processor system characterized by including.

[0030]

BEST MODE FOR CARRYING OUT THE INVENTION In order to explain the compression programming method of the present invention using a block sort compression algorithm which is one of the compression algorithms, first, 31 commands of a processor having a 16-bit length instruction word will be described. The following program example 200 (FIG. 2) is used. Command is Figure 3
As shown in the table 300 of FIG.
The short code 30
1, indicated by a mnemonic 302 corresponding to the shortened code. The registers used are R0, R1, R2 and R3. @ R2 indicates that the memory address indicated by the contents of the register R2 is referred to. # 0 indicates that the numerical value 0 is referred to.

Here, the comparison instruction is CMP / GE R0, R3 when expressed by mnemonic 302, and branches to a branch address when R3 is greater than R0 or equal to R0. In this comparison command, machine language 303 is displayed in hexadecimal notation "3.
303 ″, and the shortened code is 0.

When the addition instruction is expressed by the mnemonic 302, the contents of the registers R0 and R3 are added by ADD R0 and R3 and the result is stored in R0 (R0 + R3 → R0). The machine language 303 is "330C", which is a shortened code 1.

The shift instruction is SHLR8 R0 when expressed by the mnemonic 302. The contents of the register R0 are shifted right 8 bits and stored in R0 (R0 >> 8 → R).
0). The machine language 303 is “4019” and the shortened code is 2.

The move instruction 1 is represented by mnemonic 302 as MOV R0, R1 and stores the contents of register R0 in register R1 (R0 → R1). The machine language 3
03 is "610C", which is a shortened code 3.

The move instruction 2 is represented by mnemonic 302 as MOV R0, R2, and the contents of register R0 are stored in register R2 (R0 → R2). The machine language 3
03 is “620C”, which is a shortened code 4.

The move instruction 3 is MOV @ R2, R3 when expressed by the mnemonic 302, and the content of the memory address indicated by the content of the register R2 is stored in the register R3 ((R2) → R3). The machine language 303 is "632
2 "and shortened to code 5.

When the move instruction 4 is expressed by the mnemonic 302, it is MOV # 0, R0, and the numerical value 0 is stored in the register R0.
(0 → R0). The machine language 303 is "E00
When it is 0 ", the shortened code is 6.

The branch instruction is represented by BT when expressed by the mnemonic 302, and branches to the branch destination L when the branch flag is true. The machine language 303 is “89 **”, which is the shortened code 7. It is desired to describe the branch destination address in “**” of “89 **”, but the specific embedding will be described later.

Further, the branch instruction is an unconditional branch BRA.
(The machine language is “A ***”), it is also included in BT and the same shortened code 7 is used. A method of distinguishing "89 **" from "A ***" will also be described later. In Figure 2,
In order to show the actual execution sequence of the program based on the table 300 shown in FIG.
(PC) is described.

The program example 200 shown in FIG. 2 is arranged in the order of program counter (PC) in units of 16-bit instruction code. That is, as shown in FIG. 4, the instruction code string of the program is described using the shortened code 301 of FIG. 3 (step 400). Further, it is cyclically shifted to the left by one instruction code unit (step 401), and these shortened codes are arranged according to a defined order such as a dictionary or the size of numbers to form an array 440 (step 402).

FIG. 5 shows details of the array 440 shown in FIG. For the aligned sequences, the current alignment position number 41
0 is attached. Naturally, the first column 460 of the array 440 is in a situation where the same shortened code is continuously set in the order of arrangement. The last column 430 of the array 440 is cyclically shifted and arranged according to a defined order such as a lexicographical expression or a size of numbers. It is in a situation where it easily hardens.

In the original block sort compression method, compression coding is performed by utilizing the property that the same shortened code in the last column 430 tends to be solidified continuously. The decoding is performed by first decompressing this compression code (which is assumed here because there are several methods for compression encoding) to obtain the final column 430 and align it. ,
Since the first column 460 is automatically obtained by the cyclic shift (1 step), the pre-sorting position number 420 of the last column 430 and the current sorting position number 410 after the sorting movement are related (2 stages) at that time. Be seen.

As described above, in the original block sort compression method, since the decoding operation is indirect in two stages,
In the present invention, instead of compressing and coding the last column 430, the last column 430 is used to show the correspondence between the pre-sort position number 420 and the current sort position number 410, as shown in Table 6 of FIG.
Save 00 by compression encoding so that the decoding operation is straightforward.

As described above, the table 600 of FIG. 6 showing the correspondence between the pre-sort position number 420 and the current sort position number 410.
A table 600 needs to be created when compression-encoding and saving. The table 600 (FIG. 6) will be described with a specific example. Here, in order to improve the compression efficiency of encoding,
Absolute current alignment position number 410 (or absolute value number 41
Instead of using 0), use the relative position number 650 for each abbreviated code.

For example, the ADD of the shortened code 1 ("330
For the C ″) instruction 602, the first column 460 shown in FIG.
The current aligned position numbers 02 to 07 corresponding to the corresponding code 1 of No. 1 are represented by relative position numbers 0 to 5 of the shortened code 1. That is, the six shortened codes 1 corresponding to the current aligned position numbers 02 to 07 in the first column 460 of FIG. 5 are expressed by serially numbering 0 to 5 with "0" as a reference. Here, the relative position number corresponding to the current aligned position number 04 is "2", but the notation is omitted in this table.

Then, the abbreviated code 660 (2, 3, 3, 4, 4, 5) of the pre-sorting position number 420 (FIG. 5) corresponds to the pre-sorting position numbers 02 to 07 shown in FIG. (08,10,11,13,19,22) corresponds to the shortened code shown in the corresponding first column 460 when cyclically shifting to the current aligned position number. Furthermore, the symbol represented as the encoding of the relative number of the unaligned position number 420 is the ADD (“330C”) instruction 60.
For example, the current alignment position number and the corresponding relative position number pointed to by the corresponding command of each destination shortening code indicated by the shortening code 660 are designated.

For example, "0" is given as the encoding of the relative number of the shortened code 2, but the destination command is SH.
The relative position number "0" of the current alignment position number 08 of LR8 is designated. Also, "0+" is given as the encoding of the relative number of the shortened code 3, but the move destination command is MOV.
The relative position number "1" of the current aligned position number 11 of R0 and R1 is designated. Next, "0" is given as the encoding of the relative number of the first abbreviated code 4, but the destination command specifies the relative position number "0" of the current alignment position number 13 of MOV R0, R2. Although "3 # 2" is given as the encoding of the relative number of the second shortened code 4, the move destination command specifies the relative position number "3" of the current alignment position number 19 of MOV R0, R2. . Although "1 #" is given as the encoding of the relative number of the last abbreviated code 5, the destination command specifies the relative position number "1" of the current alignment position number 22 of MOV @ R2, R3.

That is, from the viewpoint of efficient compression coding,
If the relative number p670 is consecutive with p and p + 1, '
Indicated as p + by the + 'symbol. Further continuous cases, that is, p, p + 1 ,. ． ． , P + j, where j + 2 (j is a number greater than 0) consecutive, is shown as p + j. When the relative numbers are continuous in this way, only the pointer to the entry number p is indicated, so when the relative position number p + 1 + i in the middle is entered, the pointer is pointed like p # i. However, when i is 0, it is p #.

Using the table 600 of FIG. 6 created in this way, compression encoding as in the table 700 of FIG. 7 is performed. The abbreviated code 701 of FIG. 7 is the code indicated by reference numerals 601 to 608 of FIG. 6, and the encoded symbol of FIG. 7 is the code 66 of the pre-alignment position number 420 of FIG.
It represents a coded symbol of 0 and a relative number. For each abbreviation code 701, the abbreviated code q of the pre-sorting position number 420 (FIG. 6) is pointed to, and the continuous number from the relative number p is described. Here, the delimiter () is removed and encoded and compressed. Further, the abbreviated code 6 indicated by reference numeral 607 and the relative position number 0 corresponding to the position number 27 (FIG. 4) of the starting original program indicated by reference numeral 402 are simultaneously encoded. By performing compression encoding in this way, a direct decoding operation can be performed.

For example, in the compression code (FIG. 7) of the program example 200 of FIG. 2, the relative position number 0 of the shortened code 6 (instruction code "E000") of FIG. 6 is entered and the decoding operation is started. Therefore, the current instruction code is "E000". The machine counter “E000” corresponding to 00 is instruction-decoded and executed by the program counter (PC) 201 (FIG. 2) of the original program.

The next instruction code ("620C") corresponding to PC = 01 is read from the relative position number 0 (FIG. 6) which is the entry of the abbreviated code 6 in FIG. 7, and is abbreviated code 4 (instruction code 620C). , Rc = 3 # 1 given as a relative number encoding is obtained. Then, the machine language "620C" is instruction-decoded and executed.

In the next instruction code (6322) corresponding to PC = 02, the shortened code 701 of FIG. 7 is "6".
And entry 3 (rc of shortened code 4 of encoding 702)
= 3 # 1), that is, the command MO
With the shortened code 5 (instruction code 6322) corresponding to the aligned position number 18 corresponding to the relative position number 3 pointed to by V R0 and R2, the decoding of the code of the relative number is rc-> 3 # 1 = from the above definition. 3 + 2 −> (1 #
1) + 2 = (1 + 2) + 2 = 5 (relative position number). Then, the machine language "6322" is instruction-decoded and executed.

The instruction code (“330C”) corresponding to the next PC = 03 is read from “5” of the shortened code 701 in FIG. 7 and is the corresponding shortened code 1 (instruction code 330C) of the encoding 702. The relative position number is (1+
1) + 3 = 5. Hereinafter, the program is similarly executed while being decrypted.

Now, as described above, the decoding is repeated in sequence, and the shortening corresponding to the absolute position number 28 (or "28" of the aligned position number 410) in FIGS. 5 and 6 corresponding to PC = 11. When the code 7 (relative position number 00) is reached, the conditional branch instruction BT (89 **) is encountered. At this time, if the flag is true, PC =
In the machine word "620C" corresponding to 21, it is necessary to branch to the current alignment position number 13 (relative position 0) pointed to by the abbreviation code 4, so the ** of the BT (89 **) has abbreviated code 4 (relative The code at number position 0) is embedded. Here, the length of ** is 8 bits in the original code, but the length can be appropriately selected when encoding. Also, PC
= 17, the current alignment position number 29 in FIGS. 5 and 6
Reaching short code 7 (relative number position 1) corresponding to
Even if the conditional branch instruction BT (89 **) is encountered, it is similarly encoded. Furthermore, FIGS. 5 and 6 corresponding to PC = 30.
The short code 7 (relative number position 2) corresponding to the current aligned position number 30 of the unconditional branch instruction BRA (A **
Even if *) is encountered, the same encoding is performed. Note that 89 ** and A *** can be distinguished by the relative position of the shortened code 7.

Next, VLIW (Very Long I)
The program code compression in the instruction set of the nstruction word format will be described. For example, in the block diagram shown in FIG. 8, one VLIW instruction is composed of four blocks, and the instruction code of each block is shown as a shortened code for easy description. In the VLIW code compression method of the present invention, p1j and p2 are separately assigned to block positions j = 1, 2, 3, and 4 as shown in block 800 so that four blocks can be decoded in parallel.
j, ..., Pij are arranged and connected.
Here, if there is an index portion 801 that indicates the position order of each field, the index portion 801 may be omitted or the index portion 801 may not be provided.

With respect to the program counter PC (i = 1, n), a cyclic shift sequence is created for each block pi1, pi2, pi3, pi4, aligned and arrayed.

These respective columns are arranged in a merged / aligned manner without being divided for each block position. Then, the mixed array 820 is completed regardless of the block positions. Array 8
The current alignment numbers 01 to 32 are assigned to 20.
Here, codes corresponding to pi1, pi2, pi3, and pi4 (“12384529” and “29112574”, respectively).
5 "," 45986344 ", and" 4474741 "
2 ") is at the corresponding aligned position of sequence 820 as indicated by the arrow.

Decoding is performed by simultaneously specifying four parallel position numbers. That is, a compression-encoded correspondence table of the current alignment position number 822 and the pre-alignment position number 823 using the last column 830 of the plurality of instruction code sequences in the array 820 (FIG. 6).
Decryption of a table as shown in FIG. Even if the block positions are not divided and mixed and aligned, the correct decoding can be performed because each point to the next decoding position.

The principle of parallel program code compression / decoding described above can be applied not only to VLIW but also to a single instruction word architecture. That is, for example, as shown in FIG. 9, the serial program code 900 is divided into four instruction units, and four parallel sequences 910, 920, 930, and 940, so-called pseudo VLI.
Create the W method. Then, in order to perform branching without problems in this method, the original branch instructions 931, 922, 9
13 to the dummy instructions (941, 9
11, 921), (932, 942, 912), (92
3, 933, 943) is added. By doing so, the serial program code 900 can be pseudo-parallelized, and the decoding speed can be accelerated.

Further, an intermediate language (for example, Java)
This section describes a compression method for virtual program code strings written in (language). For example, the virtual machine CPU shown in FIG.
In an information communication system including a CPU 1 and a CPU 2, processors (CPUs 1 and 2) conventionally used in mobile phones and personal computers have architectures having different instruction sets depending on manufacturers. Further, there are various display devices. Also, if the screen size is large or small, it is necessary to change the display layout.

Therefore, assuming a virtual machine such as a Java machine, a virtual program code string written in an intermediate language and compressed is sent to the CPU 1 (for example, the sending side terminal).
After transmitting or delivering from the base station) to the CPU2 (for example, a mobile phone used by the end user) which is the receiving side terminal, the receiving side terminal receives and expands the code string,
It will be executed while being interpreted by the built-in processor.
Further, the receiving side terminal also notifies the transmitting side terminal when the reception of the code string is completed. The virtual code string is executed while being interpreted by a virtual machine interpreter written so that it can be executed by a specific processor. A large-sized virtual program code string needs to be compressed for storage, but is compressed and transferred even in a communication path with a low transfer rate. Therefore, the receiving terminal decompresses and decodes the compressed virtual program code string into the original virtual program code string, and executes it while interpreting it by the built-in interpreter, resulting in a significant decrease in execution speed.

The system block shown in FIG. 11 of the present invention has similarities to the system block configuration shown in FIG. 10 of the conventional example, but in order to prevent the execution speed of the intermediate language from decreasing, the reception corresponding to the virtual machine is performed. Side terminal (CPU2)
The built-in interpreter is designed to directly decompress and execute the compressed code string of a virtual program. That is, the shortened code corresponding to each instruction command forming the expanded / decoded virtual program of the virtual machine is directly linked and executed by the execution program (interpreter) of the specific machine that executes the virtual instruction.

The above description is summarized in FIG.
The processor system configuration is as shown in. The processor having the configuration shown in FIG. 1 is the same as the processor installed in each terminal of FIGS. 10 and 11. The compression-encoded program shown in FIG. 2, the last column 43 in FIG.
The correspondence table of the current sorted position number and the unsorted position number shown in FIG. 6 and the correspondence table of the shortened code and the coding shown in FIG. 7, which are created by using 0, are stored in the compression unit (not shown). It is created and saved, and the compression unit is stored in the compression instruction area 104 of the memory 101. Further, the compression unit includes a correspondence table of the current alignment position number 822 and the pre-alignment position number 823, which are created using the last column 830 of FIG. 8 and are stored after compression. A program that is not compressed is stored in the non-compressed area 103 of the memory. Generally, the compression instruction area and the non-compression area are stored in a ROM (Read Only).
Memory) or a non-volatile memory conforming to the ROM. However, in the transmission / reception system, the reception side terminal is not limited to this occasion. There is a read / write main memory area used for work. Since the compression code of the table 700 shown in FIG. 7 is stored in the compression instruction area 104, the decoding unit 107 is provided to decode the compression code.

Since a part of the decoding process is cached for the high speed decoding process, the decoding cache unit 106 is provided. The instruction code decoded by the decoding unit and the decoding cache unit is sent to the instruction cache unit 105, and merges with the decoding cache unit 106 which is a processing unit of the non-compressed instruction. In the instruction cache unit 105, the cache
If a mistake occurs, the process returns to the decoding cache unit 106 and the process proceeds. Therefore, a branch instruction that has a cache miss in the instruction cache unit goes to the place where the decode cache unit manages the branch instruction.

Since the decoding cache unit 106 is arranged by the block sort compression method, it can be collected and fixedly stored in a designated place. Decoding section 107
Is internal to the virtual machine interpreter 108 and is directly interpreted when decoding the compressed code string of the virtual program,
Link to the executable program. In addition, a decoder unit 109 that interprets the contents of the instruction cache unit 105, a control unit 110 that controls the decoder unit 109, a register 111 that stores and processes data in the main memory area 102, addition / subtraction based on the data, and the like. The calculator 112 is provided for executing the calculation of.

[0066]

The compression programming method of the present invention and the processor system using the compression programming method can be decoded from the branch destination even by the appearance of a branch instruction. Therefore, the compression programming method is suitable for program codes for random access. Moreover, in the instruction code, the repetitive correlation is different between the operation code and the operand part, but unlike the conventional compression method which is affected by these, since the compression encoding is performed regardless of these structures, a high compression rate can be achieved. .

Further, even in the program code of the VLIW architecture, which tends to have a large program size, highly efficient compression can be expected. The virtual program code can also be compressed, transferred, and directly interpreted and executed while being decoded.

[Brief description of drawings]

FIG. 1 is a block diagram of a processor that decodes, interprets, and executes a compressed program code according to the present invention.

FIG. 2 is a diagram showing a program example of a certain machine.

FIG. 3 is a diagram showing a table showing correspondences between mnemonics, abbreviated codes, and machine languages in a program example.

FIG. 4 is a diagram showing a compression state by arranging in a short code notation.

FIG. 5 is a diagram showing alignment and arrangement of a program example.

FIG. 6 is a diagram showing a table showing that compression is performed so as to save the relationship between the current aligned position number and the pre-aligned position number.

FIG. 7 is a diagram showing a table showing compression encoding.

FIG. 8 is a diagram showing a state of parallel alignment of VLIW program codes.

FIG. 9 is a diagram showing that a dummy branch is inserted in the VLIW method.

FIG. 10 is a block diagram showing a state in which a conventional program code written in an intermediate language is transmitted and received to be interpreted and executed by a virtual machine.

FIG. 11 is a block diagram showing a state in which a program code written in an intermediate language of the present invention is compressed, transmitted / received, decoded by a virtual machine, and directly interpreted and executed.

[Explanation of symbols]

101 ... Memory, 102 ... Main memory area, 103 ... Uncompressed area, 104 ... Compressed area, 107 ... Decoding unit, 106 ...
Decoding cache unit, 105 ... Instruction cache unit, 109
Decoder, 110 ... Control unit, 111 ... Register, 11
2 ... Arithmetic unit, 200 ... Program code, 600 ... Correspondence table of current aligned position number and unaligned position number, 700 ...
Correspondence table for short code and compression encoding.

Claims (21)

[Claims] 1. In a compression programming method, a step of setting a plurality of codes corresponding to a plurality of commands constituting a certain arbitrary program; and after arranging the plurality of codes using a compression algorithm,
A compression programming method comprising the steps of arranging and compression encoding. 2. The compression programming method according to claim 1, wherein the code is a short code corresponding to the command, and the plurality of codes are arranged according to a defined order. 3. The compression programming method according to claim 1, wherein the compression algorithm is a block sort compression algorithm. 4. The step of compression-encoding includes the step of creating a correspondence table of the current alignment position number and the pre-alignment position number by using the tail sequence of the plurality of arranged codes, and storing the table after compression. The compression programming method according to claim 1, comprising: 5. A compression programming method using a compression algorithm, wherein for an instruction format having a plurality of instruction fields, a field of one instruction is divided into a plurality of instruction blocks, and each divided block position is aligned after compression. Compressing the arranged instruction code strings; mixing the arranged instruction code strings, arranging the combined instruction code strings after merging them A compression programming method characterized by including a step of encoding and a step of decoding in parallel for each divided block at the time of decoding. 6. The compression programming method according to claim 5, wherein the plurality of instruction codes are composed of a plurality of shortened codes. 7. The step of compression-encoding uses a last column of the plurality of arranged instruction code sequences, creates a correspondence table of current aligned position numbers and unaligned position numbers, and stores the table after compression. The compression programming method according to claim 5, further comprising: 8. In a processor system using a compression programming method, a setting unit for setting a plurality of codes corresponding to a plurality of commands constituting a certain arbitrary program, and after arranging the plurality of codes using a compression algorithm, A processor system comprising: a compression unit that arranges and compression-encodes. 9. The processor system according to claim 8, wherein the compression algorithm is a block sort compression algorithm. 10. The processor system according to claim 8, wherein the code is a short code corresponding to the instruction command, and the plurality of codes are arranged in a defined order. 11. The compression unit creates and stores a correspondence table of the current alignment position number and the pre-alignment position number by using the last row of the arranged codes. 8. The processor system according to item 8. 12. A processor system according to a compression programming method, for an instruction format having a plurality of instruction fields, divides a field of one instruction into a plurality of instruction blocks, and aligns the divided block positions after compression. And a means for arranging the plurality of instruction code strings, which have been arranged in a row, after arranging the plurality of instruction code strings after mixing, and arranging the plurality of instruction code strings. A processor system, comprising: a compression unit that performs compression encoding, and a decoding unit that performs parallel decoding for each divided block when decoding. 13. The processor system according to claim 12, wherein the plurality of instruction codes are composed of a plurality of shortened codes. 14. The compressing unit uses the last column of the plurality of arranged instruction code sequences, creates a correspondence table of the current aligned position number and the unaligned position number, and stores it after compression. The processor system according to claim 12. 15. An information communication system for controlling the transfer of information such as a program code, comprising an originating terminal having an information transfer section for controlling the information transfer of a program code string compressed by a block sort compression algorithm, The information communication system further comprises a receiving side terminal that receives the program code sequence to which the information is transferred, and the receiving side terminal can directly perform decoding and interpretation of the program code sequence. 16. The program code string is an intermediate language, the calling terminal is a virtual machine provided in a base station, the receiving terminal is a mobile phone, and the program code string is received. 16. The information communication system according to claim 15, wherein the completion is notified to the calling side terminal. 17. In a program code information distribution service method, a step of receiving a program code compressed by a block sort compression algorithm distributed from a transmission side terminal at a reception side terminal, and after the reception of the program code is completed. An information distribution comprising: a step of notifying completion of reception from the receiving side terminal to the transmitting side terminal; and a step of directly decoding, interpreting and executing the compressed program code at the receiving side terminal. Service method. 18. The receiving terminal is a mobile phone having an interpreter for interpreting the program code string,
The calling side terminal gives a user who uses the mobile phone,
The information distribution service method according to claim 17, wherein the information distribution service method is a base station that distributes information such as the program code. 19. The method according to claim 17, wherein the interpretable and executable step includes a step in which an interpreter incorporated in the receiving side terminal directly decompresses, interprets, and executes the compressed program code. Information delivery service method. 20. A processor comprising a plurality of storage elements and operating using a compression algorithm, wherein each of the plurality of storage elements has a compression instruction area for storing a compressed program code, A processor system comprising an interpreter capable of directly decoding a program code, interpreting and executing the program code. 21. The compression algorithm is a block sort compression algorithm.
Processor system according to.