JP2003021661A - Withstand voltage testing device - Google Patents
Withstand voltage testing deviceInfo
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- JP2003021661A JP2003021661A JP2001242957A JP2001242957A JP2003021661A JP 2003021661 A JP2003021661 A JP 2003021661A JP 2001242957 A JP2001242957 A JP 2001242957A JP 2001242957 A JP2001242957 A JP 2001242957A JP 2003021661 A JP2003021661 A JP 2003021661A
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- voltage
- output
- current
- output voltage
- value
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Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、耐電圧特性を試験
する試験装置に関し、特に供試物に印加する高電圧の安
定性能に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test apparatus for testing withstand voltage characteristics, and more particularly to stability performance of high voltage applied to a sample.
【0002】[0002]
【従来の技術】耐電圧試験装置は、各種安全規格(JI
S規格、UL規格、CSA規格など)に合致するかを、
それらの規格上で要求される交流の高電圧を供試物に一
定時間印加して、該供試物の耐電圧性能を判定する試験
装置であり、その良否判定は供試物に流れる電流を測定
することにより行われる。そして、交流の高電圧を得る
には、一般的に50Hz又は60Hzの商用電源を昇圧
する方法或は図9及び図10に示すように、発振部1に
て正弦波を発生させ、電力増幅する方法が採用されてい
る。2. Description of the Related Art Withstand voltage testers are compliant with various safety standards (JI
S standard, UL standard, CSA standard, etc.)
It is a test device that determines the withstand voltage performance of the sample by applying a high AC voltage required for those standards to the sample for a certain period of time. It is done by measuring. Then, in order to obtain a high AC voltage, a method of boosting a commercial power source of 50 Hz or 60 Hz is generally used, or a sine wave is generated in the oscillating unit 1 to amplify the power, as shown in FIGS. 9 and 10. The method has been adopted.
【0003】図9に示す帰還方式の従来技術は、発振部
1にて発生させた正弦波信号を増幅器Prと電力増幅器
Paにて電力増幅してトランスTの1次側巻線を励磁し
て該トランスの2次側巻線に例えば5kV(rms)
(以下rmsを省略する)に昇圧された出力電圧Voを
得、該電圧を供試物3に印加して電流検出器40に流れ
る電流Ioを検出し、該供試物の良否を判定するように
構成されている。In the conventional feedback system shown in FIG. 9, the sine wave signal generated in the oscillating unit 1 is power-amplified by an amplifier Pr and a power amplifier Pa to excite the primary winding of a transformer T. 5 kV (rms) on the secondary winding of the transformer
The output voltage Vo boosted (hereinafter, rms is omitted) is obtained, the voltage is applied to the DUT 3, the current Io flowing through the current detector 40 is detected, and the quality of the DUT is determined. Is configured.
【0004】一方図10に示す帰還方式の従来技術は、
発振部1にて発生させた正弦波信号を、乗算器7を介し
て電力増幅器Paで電力増幅してトランスTの1次側巻
線を励磁して該トランスの2次側巻線に例えば5kVに
昇圧された出力電圧Voを得、該電圧を供試物3に印加
して電流検出器40に流れる電流Ioを検出し、該供試
物の良否を判定するように構成されている。On the other hand, the conventional feedback system shown in FIG.
The sine wave signal generated by the oscillating unit 1 is power-amplified by the power amplifier Pa via the multiplier 7 to excite the primary side winding of the transformer T and, for example, 5 kV to the secondary side winding of the transformer. It is configured to obtain the output voltage Vo boosted in step 1, apply the voltage to the DUT 3, detect the current Io flowing through the current detector 40, and determine the quality of the DUT.
【0005】しかし、何れの従来技術においても帰還量
が極めて充分でない場合、供試物3の抵抗成分Rtとト
ランスTの巻線抵抗2とが直列に接続されることとなる
結果、例えば巻線抵抗2を5kΩとして供試物3に0.
1Aの大電流を流すと、該抵抗2には500Vの電圧降
下が生じ、該供試物に印加するように設定した筈の5k
Vは、実際には4.5kVで印加されると言う事態を生
じる。この誤差は10%に相当し、操作者は再度印加電
圧を設定し直さなくてはならない。However, in any of the conventional techniques, when the feedback amount is extremely insufficient, the resistance component Rt of the DUT 3 and the winding resistance 2 of the transformer T are connected in series. The resistance 2 was set to 5 kΩ and the resistance to the sample 3 was reduced to 0.
When a large current of 1 A is applied, a voltage drop of 500 V occurs in the resistor 2, and it should be set to be applied to the DUT 5 k.
The situation occurs that V is actually applied at 4.5 kV. This error corresponds to 10%, and the operator must reset the applied voltage again.
【0006】このような電圧降下対策として、9図に示
す従来技術ではトランスTの2次側巻線出力を抵抗Rd
とRaで分圧し、増幅器Prのマイナス端子に帰還する
ことにより、出力電圧の安定度改善を図っており、抵抗
Ro、コンデンサCoは、高周波域における位相回転に
よる異常発振防止用のものである。As a countermeasure against such a voltage drop, in the prior art shown in FIG. 9, the output of the secondary winding of the transformer T is changed to a resistor Rd.
The output voltage stability is improved by dividing the voltage by R and Ra and returning to the negative terminal of the amplifier Pr. The resistor Ro and the capacitor Co are for preventing abnormal oscillation due to phase rotation in the high frequency range.
【0007】一方10図に示す従来技術では、出力電圧
を検出し適宜減衰した後、AC/DC変換器で交流電圧
を直流電圧に変換した後、比較器(COMP)で基準電
圧Vrefと比較して誤差電圧を得、乗算器7に負帰還
し、出力電圧の安定化を図っており、同図に示す抵抗R
dとコンデンサCdから成る積分回路は、低周波域にお
ける異常発振を防止するためのものである。On the other hand, in the prior art shown in FIG. 10, after detecting an output voltage and appropriately attenuating it, an AC / DC converter converts an AC voltage into a DC voltage and then a comparator (COMP) compares it with a reference voltage Vref. Error voltage is obtained and negative feedback is given to the multiplier 7 to stabilize the output voltage, and the resistor R shown in FIG.
The integrating circuit composed of d and the capacitor Cd is for preventing abnormal oscillation in the low frequency range.
【0008】[0008]
【発明が解決しようとする課題】しかしながら、前述し
た二つの帰還方式による従来技術には以下の問題があ
る。However, there are the following problems in the prior art based on the above two feedback systems.
【0009】即ち図9に示す方式ではトランスの2次側
巻線出力を抵抗RdとRaで分圧し、増幅器Prのマイ
ナス端子に負帰還することにより出力電圧の安定度改善
を図る一方、帰還量の増大を遠因とする増幅器Pr、電
力増幅器Pa及びトランスT部の位相回転による異常発
振等をRo及びCoから成る防止回路にて解決を図って
いるため、この方式による帰還量の最適化は出力安定度
と異常発振防止との兼ね合いにならざるを得ない。当然
あらゆる試験条件下全般で常に異常発振を防止すること
が困難であるため、実用上必要な許容誤差を確保するの
は至難である。That is, in the system shown in FIG. 9, the output of the secondary winding of the transformer is divided by resistors Rd and Ra and negatively fed back to the negative terminal of the amplifier Pr to improve the stability of the output voltage, while the feedback amount is increased. Since the abnormal circuit due to the phase rotation of the amplifier Pr, the power amplifier Pa, and the transformer T section, which is caused by the increase of the power consumption, is solved by the prevention circuit composed of Ro and Co, the optimization of the feedback amount by this method is performed. There is no choice but to strike a balance between stability and prevention of abnormal oscillation. Naturally, it is difficult to always prevent abnormal oscillation under all test conditions, so it is extremely difficult to secure a permissible error necessary for practical use.
【0010】また、図10に示す帰還方法は、帰還ルー
プを構成するAC/DC変換器内部の時定数及び抵抗R
dとコンデンサCdから成る積分回路の時定数により回
路全体の応答速度が遅くなり、出力電圧Voに重畳する
サージ電圧(オーバーシュート或はアンダーシュート)
が過渡的に供試物に加えられる結果、供試物又は該供試
物を形成する素子を破壊するおそれがある。In the feedback method shown in FIG. 10, the time constant and the resistance R inside the AC / DC converter forming the feedback loop are used.
The response time of the entire circuit becomes slow due to the time constant of the integrating circuit composed of d and the capacitor Cd, and the surge voltage (overshoot or undershoot) superimposed on the output voltage Vo
As a result of being transiently added to the sample, the sample or the element forming the sample may be destroyed.
【0011】更に前記2つの従来技術では、異常発振防
止対策等で帰還量が充分確保できない場合、トランスT
の発熱により巻線抵抗値2の増大に伴い出力電圧が降下
すると言う金属抵抗固有の温度特性問題を解決し得な
い。Further, in the above-mentioned two prior arts, when a sufficient feedback amount cannot be secured due to measures for preventing abnormal oscillation, the transformer T
It is impossible to solve the temperature characteristic problem peculiar to the metal resistance that the output voltage drops due to the increase of the winding resistance value 2 due to the heat generation of.
【0012】本発明は、これらの帰還方式の欠点、問題
点を解決するためになされたものである。The present invention has been made to solve the drawbacks and problems of these feedback systems.
【0013】[0013]
【課題を解決するための手段】上記の課題を解決するた
め、請求項1の発明は、交流信号源の出力信号にてトラ
ンスを励磁して交流の高出力電圧を得、該出力電圧を供
試物に印加して電流検出器に流れる電流により耐電圧性
能を試験する耐電圧試験装置において、前記電流検出器
にて検出された検出値を直流化する直流化手段を備え、
電圧設定手段及び第1の加算手段を備え、前記直流化手
段からの直流値と前記電圧設定手段からの出力電圧を前
記第1の加算手段にて加算し、該加算値と前記交流信号
源からの出力信号を乗算して出力電圧を補正する乗算手
段を備えることを特徴とする。In order to solve the above-mentioned problems, the invention of claim 1 excites a transformer with an output signal of an AC signal source to obtain a high AC output voltage and supplies the output voltage. In a withstand voltage test device for testing withstand voltage performance by a current applied to a sample and flowing through a current detector, a direct current converting means for converting the detected value detected by the current detector into direct current is provided,
A voltage setting means and a first adding means, and the direct current value from the direct current converting means and the output voltage from the voltage setting means are added by the first adding means, and the added value and the alternating current signal source It is characterized by comprising a multiplying means for multiplying the output signal of 1 to correct the output voltage.
【0014】請求項2は、請求項1において、前記交流
信号源の出力信号と同相関係にある信号により前記電流
検出器からの検出値を整流する整流手段を備え、前記整
流手段からの出力を前記直流化手段にて直流化し、該直
流値と前記電圧設定手段からの出力電圧を前記第1の加
算手段にて加算することを特徴とする。According to a second aspect of the present invention, there is provided rectifying means for rectifying a detected value from the current detector by a signal in phase with the output signal of the AC signal source, and the output from the rectifying means is provided. It is characterized in that the direct current converting means converts the direct current into a direct current value, and the direct current value and the output voltage from the voltage setting means are added by the first adding means.
【0015】請求項3は、請求項1及び請求項2におい
て、温度検出手段及び温度/電圧変換手段を備え、第2
の加算手段を備え、前記温度検出手段からの検出値を前
記温度/電圧変換手段にて電圧変換し、前記温度/電圧
変換手段の出力と前記直流化手段からの直流値を前記第
2の加算手段にて加算し、該加算値を前記第1の加算手
段に入力することを特徴とする。According to a third aspect of the present invention, in addition to the first and second aspects, the temperature detecting means and the temperature / voltage converting means are provided.
Of the temperature detecting means, the detected value from the temperature detecting means is converted into a voltage by the temperature / voltage converting means, and the output of the temperature / voltage converting means and the DC value from the DC converting means are added to the second adding means. Means for adding and the added value is input to the first adding means.
【0016】[0016]
【発明の実施の形態】本発明の要旨は、図7に示す如
く、出力電流Ioから(B)の補正電圧ΔVcを生成し
てレギュレーション特性(A)を補正することにより出
力電圧特性(C)を得、出力電圧Voの安定化を図ると
ころにある。図7は、この補正の原理を示したもので、
以下に、この原理を説明する。図7の(A)の如く、レ
ギュレーション特性は供試物に流れる電流量Ioに比例
した右下がりの傾き特性を示す。そこで、このような傾
きを有する電圧特性を、−ΔVcとすれば、
−ΔVc =巻線抵抗2の電圧降下分
となる。従って、出力電圧特性(C)のような補正特性
を得るには、電流Ioからこの巻線抵抗2の電圧降下分
と正反対の傾き特性を有する補正電圧ΔVc即ち(B)
を生成し、レギュレーション特性(A)に加算すれば良
い。BEST MODE FOR CARRYING OUT THE INVENTION As shown in FIG. 7, the gist of the present invention is to generate a correction voltage .DELTA.Vc of (B) from an output current Io to correct a regulation characteristic (A) and thereby output voltage characteristic (C). And to stabilize the output voltage Vo. FIG. 7 shows the principle of this correction.
The principle will be described below. As shown in (A) of FIG. 7, the regulation characteristic shows a downward-sloping slope characteristic proportional to the amount of current Io flowing through the sample. Therefore, if the voltage characteristic having such a slope is set to -ΔVc, then -ΔVc = voltage drop of the winding resistance 2. Therefore, in order to obtain a correction characteristic such as the output voltage characteristic (C), the correction voltage ΔVc having a slope characteristic opposite to the voltage drop of the winding resistor 2 from the current Io, that is, (B).
Should be generated and added to the regulation characteristic (A).
【0017】請求項1の発明は、抵抗成分のみで形成さ
れる供試物3に流れる電流IoからΔVcを生成して巻
線抵抗2による電圧降下を補正し、出力電圧Voの安定
化を図るものであり、以下に、図1に示す請求項1の一
実施例に基づき、その動作を説明する。According to the first aspect of the invention, ΔVc is generated from the current Io flowing through the sample 3 formed of only the resistance component to correct the voltage drop due to the winding resistance 2 and stabilize the output voltage Vo. The operation will be described below based on an embodiment of claim 1 shown in FIG.
【0018】図1において、信号発生器10は、50又
は60Hzの正弦波信号を発生するものであり、この正
弦波信号と加算器11からの出力を乗算器20に入力
し、該乗算出力を電力増幅器30にて電力増幅し、トラ
ンスT1の1次側巻線を励磁して出力電圧Voを得てい
る。但し、出力端子Ta−Tb間に供試物3が接続され
ていないときには、加算器11に入力される電圧設定器
6からの出力設定電圧Viのみにより出力電圧Voが設
定されている。このように、出力電圧Voは電圧Viを
可変することで変化させることができる。In FIG. 1, a signal generator 10 generates a sine wave signal of 50 or 60 Hz. The sine wave signal and the output from the adder 11 are input to a multiplier 20, and the multiplication output is The power is amplified by the power amplifier 30, and the primary winding of the transformer T1 is excited to obtain the output voltage Vo. However, when the DUT 3 is not connected between the output terminals Ta and Tb, the output voltage Vo is set only by the output setting voltage Vi from the voltage setting device 6 input to the adder 11. In this way, the output voltage Vo can be changed by changing the voltage Vi.
【0019】次に、供試物3を出力端子Ta−Tb間に
接続し、出力電圧Voを印加すると電流Ioが生じ、レ
ギュレーション特性は、前述した図7の(A)に示した
如くになる。この電流Ioを電流検出器40で電圧検出
し、可変抵抗器4で増幅器14の増幅度を調整して図7
の(A)の傾き特性と正反対の傾きを得、積分器13
(絶対値変換回路及びローパスフィルタから成る)にて
全波整流した後、直流に近似した補正電圧ΔVc即ち図
7の(B)を生成する。なお、電流検出器40はカレン
トトランス或は抵抗器の何れでも良く、また、絶対値変
換回路は全波整流形、半波整流形の何れでも良い。Next, the DUT 3 is connected between the output terminals Ta and Tb, and when the output voltage Vo is applied, a current Io is generated, and the regulation characteristic becomes as shown in FIG. . The voltage of this current Io is detected by the current detector 40, the amplification degree of the amplifier 14 is adjusted by the variable resistor 4, and
Of the slope characteristic of (A) is obtained, and the slope of the integrator 13 is obtained.
After full-wave rectification by an absolute value conversion circuit and a low-pass filter, a correction voltage ΔVc approximated to DC, that is, (B) in FIG. 7 is generated. The current detector 40 may be a current transformer or a resistor, and the absolute value conversion circuit may be a full-wave rectification type or a half-wave rectification type.
【0020】増幅器14は、前記補正電圧ΔVcを得る
ための利得が不足している場合に適宜設ける増幅器で、
電流検出器40の直後に限らず、例えば積分器13を構
成するローパスフィルタの前後に設けても良い。また、
増幅器14の入出力間に設けた可変抵抗器4は、前述し
た如く、増幅器14の利得を変化させて、前記(B)の
ような傾きになるようにする調整器であるが、この調整
は一度で済むため、巻線抵抗値2のバラツキが殆ど一定
値である場合には固定の抵抗器とすることも出来る上、
格別増幅器14の入出力間に設ける必要はなく、増幅器
14と同様、積分器13を構成するローパスフィルタの
前後段に設けて利得調整しても良い。The amplifier 14 is an amplifier which is appropriately provided when the gain for obtaining the correction voltage ΔVc is insufficient.
It may be provided not only immediately after the current detector 40 but also before and after the low-pass filter forming the integrator 13, for example. Also,
The variable resistor 4 provided between the input and output of the amplifier 14 is an adjuster for changing the gain of the amplifier 14 so as to have the inclination as shown in (B) as described above. Since it only needs to be done once, a fixed resistor can be used when the variation in the winding resistance value 2 is almost constant.
It is not necessary to provide it between the input and output of the special amplifier 14, and like the amplifier 14, the gain may be adjusted by providing it at the front and rear stages of the low-pass filter that constitutes the integrator 13.
【0021】このようにして生成した補正電圧ΔVcと
電圧設定器6からの電圧Viを加算器11に入力し、加
算値(ΔVc+Vi)を得る。そして、この加算値と信
号発生源10からの出力を乗算器20にて乗算すること
で、巻線抵抗2における電圧降下分(−ΔVc)を補正
した出力電圧Voを得ることができる。以上のようにし
て、出力電圧Voを補正できる。The correction voltage ΔVc thus generated and the voltage Vi from the voltage setting unit 6 are input to the adder 11 to obtain an added value (ΔVc + Vi). Then, by multiplying the added value and the output from the signal generation source 10 by the multiplier 20, the output voltage Vo in which the voltage drop (−ΔVc) in the winding resistance 2 is corrected can be obtained. As described above, the output voltage Vo can be corrected.
【0022】図4は、前記積分器13を構成する絶対値
変換回路の一実施例であり、以下にその動作を説明す
る。まず演算増幅器Qv1のプラス端子に交流電圧波形
を入力すると、演算増幅器Qv1の出力電圧波形のマイ
ナス側は、ダイオードDv1および抵抗Rv2を介して
演算増幅器Qv1のマイナス端子に入力され、
の比で増幅される。次に、増幅されたその出力は抵抗R
v3を介して演算増幅器Qv2のマイナス端子に入力さ
れ、
の比で増幅される。このようにして、Qv2の出力端子
からプラスに極性反転した半サイクルの出力信号を得
る。また、Qv1の出力に接続されるダイオードDv2
は、Qv1のプラスの出力波形をQv1のマイナス端子
に入力する一方、Qv2のプラス端子にもQv1のプラ
スの出力波形を入力して極性の反転しない出力波形がQ
v2の出力から得られ、最終的にプラスの整流波形が得
られるように動作する。また、前記積分器13を構成す
るローパスフィルタの一実施例を図12に示すが、その
動作説明は省略する。FIG. 4 shows an embodiment of an absolute value conversion circuit which constitutes the integrator 13, and its operation will be described below. First, when an AC voltage waveform is input to the positive terminal of the operational amplifier Qv1, the negative side of the output voltage waveform of the operational amplifier Qv1 is input to the negative terminal of the operational amplifier Qv1 via the diode Dv1 and the resistor Rv2. It is amplified by the ratio of. Then the amplified output is a resistor R
is input to the negative terminal of the operational amplifier Qv2 via v3, It is amplified by the ratio of. In this way, a positive half-cycle output signal whose polarity is inverted is obtained from the output terminal of Qv2. Also, the diode Dv2 connected to the output of Qv1
Input the positive output waveform of Qv1 to the negative terminal of Qv1, while inputting the positive output waveform of Qv1 to the positive terminal of Qv2, the output waveform whose polarity is not inverted is Q.
It is obtained from the output of v2 and operates so as to finally obtain a positive rectified waveform. FIG. 12 shows an example of a low-pass filter that constitutes the integrator 13, but the description of its operation is omitted.
【0023】請求項2の発明は、抵抗成分Rtと容量成
分Ctで形成される供試物3において、該供試物に流れ
る電流Ioから容量成分Ctに流れる電流を除去した補
正電圧ΔVcを生成し、巻線抵抗2による電圧降下を補
正して出力電圧Voの安定化を図るものである。即ち、
前述した如く抵抗成分のみの供試物3に5kVの電圧を
印加して0.1Aの電流Ioが流れる場合、巻線抵抗2
を5kΩとすると、該抵抗2に生ずる電圧降下は500
Vとなる。しかしながら、供試物3が抵抗成分Rtと容
量成分Ctで形成されるときには周知のとおり、
Rrに流れる電流(IRr)=Rtに流れる電流(IR
t)
であり、且つ容量成分に対する電流が90°の進み位相
を有し、電圧が90°の遅れ位相を有するため、便宜的
にRrで説明すると、図8(A)及び(B)に示すとお
り、電流IRrと電流ICtとが
となるベクトル合成値として電流Ioが電流検出器Ri
にて検出されることとなる。このようなベクトル合成さ
れた電流Ioから補正電圧ΔVcを生成すると、該電流
ICtの増大に伴い過補正された補正電圧ΔVcを生成
することとなるため、電流ICtを除去し、抵抗成分の
みに流れる電流IRrのみから補正電圧(B)を生成し
て出力電圧Voを補正しなければならない。According to the second aspect of the invention, in the sample 3 formed of the resistance component Rt and the capacitance component Ct, the correction voltage ΔVc is generated by removing the current flowing in the capacitance component Ct from the current Io flowing in the sample. However, the voltage drop due to the winding resistance 2 is corrected to stabilize the output voltage Vo. That is,
As described above, when a voltage of 5 kV is applied to the sample 3 having only the resistance component and the current Io of 0.1 A flows, the winding resistance 2
Is 5 kΩ, the voltage drop across the resistor 2 is 500
It becomes V. However, when the sample 3 is formed of the resistance component Rt and the capacitance component Ct, as is well known, the current flowing through Rr (IRr) = the current flowing through Rt (IR
t), the current with respect to the capacitance component has a lead phase of 90 °, and the voltage has a lag phase of 90 °. Therefore, for convenience, Rr is shown in FIGS. 8A and 8B. The current IRr and the current ICt are The current Io is the current detector Ri as the vector composite value
Will be detected at. When the correction voltage ΔVc is generated from the vector-combined current Io, the overcorrected correction voltage ΔVc is generated as the current ICt increases. Therefore, the current ICt is removed and only the resistance component flows. The output voltage Vo must be corrected by generating the correction voltage (B) only from the current IRr.
【0024】図2は、請求項2の一実施例を示したもの
であり、以下に、請求項1に異なる部分について図2に
基づき説明する。電流検出器40で電圧検出された合成
電流Ioは増幅器14で増幅され、位相検波回路15に
入力される。但し、この位相検波回路15は前記の絶対
値変換機能を兼備している。なお、図6(A)は、位相
検波回路15の一実施例を示したもので、図6(B)
は、0°位相及び90°位相の検出電流波形及び位相検
波回路における電流波形を示すと共に、タイミング関係
を示している。FIG. 2 shows an embodiment of claim 2, and the parts different from claim 1 will be described below with reference to FIG. The combined current Io whose voltage is detected by the current detector 40 is amplified by the amplifier 14 and input to the phase detection circuit 15. However, this phase detection circuit 15 also has the above-mentioned absolute value conversion function. 6A shows an embodiment of the phase detection circuit 15, and FIG.
Shows the detected current waveform of 0 ° phase and 90 ° phase and the current waveform in the phase detection circuit, and also shows the timing relationship.
【0025】以下に、図6(A)及び(B)に基づき該
位相検波回路の動作を説明する。図6(B)において、
1Aは検出信号波形を表し、2AはスイッチSp1
(2)を駆動する制御信号波形を表し、3Aは演算増幅
器Qp1の出力信号波形を表している。先ず電流検出器
40で検出された合成電流波形がRp3、Rp4を介し
て演算増幅器Qp1のプラス端子に入力されると、1A
から3Aの各信号波形のタイミング関係から明らかなよ
うに、スイッチSp1(2)がオフのときは、Qp1は
増幅度1のフォロワーアンプとして動作し、該スイッチ
がオンになると、
の反転増幅器として動作する。但し、増幅度は1でなく
ても良い。即ち該位相検波回路は、トランスT1のL3
からの信号と同相の信号で、スイッチSp1をオフ/オ
ンさせると、図6(B)の3Aに示す合成波形を出力す
ることになる。なお、スイッチSp1は、後述する位相
検出器16によりオン、オフが制御される。The operation of the phase detection circuit will be described below with reference to FIGS. 6 (A) and 6 (B). In FIG. 6 (B),
1A indicates a detection signal waveform, and 2A indicates a switch Sp1.
The control signal waveform for driving (2) is shown, and 3A shows the output signal waveform of the operational amplifier Qp1. First, when the combined current waveform detected by the current detector 40 is input to the plus terminal of the operational amplifier Qp1 via Rp3 and Rp4, 1A
As is clear from the timing relationships of the signal waveforms from 3A to 3A, when the switch Sp1 (2) is off, Qp1 operates as a follower amplifier with an amplification factor of 1, and when the switch is on, It operates as an inverting amplifier. However, the amplification degree does not have to be 1. That is, the phase detection circuit is the L3 of the transformer T1.
When the switch Sp1 is turned off / on with a signal having the same phase as the signal from, the composite waveform shown in 3A of FIG. 6B is output. The switch Sp1 is on / off controlled by a phase detector 16 described later.
【0026】図2において、図6(B)の3Aに示す波
形は、積分器13(ローパスフィルタから成る。)にて
直流化され、抵抗成分のみの補正信号ΔVcとして生成
され、このΔVcは加算器11で電圧設定器6からの電
圧Viと加算され、加算値(ΔVc+Vi)を得る。そ
して、この加算値と信号発生器10からの出力を乗算器
20にて乗算することで、巻線抵抗2における電圧降下
分(−ΔVc)を補正した出力電圧Voを得る。以上の
ようにして、容量成分のみで形成される供試物3であっ
ても出力電圧Voを補正できる。In FIG. 2, the waveform indicated by 3A in FIG. 6 (B) is converted into a direct current by the integrator 13 (comprising a low-pass filter) and generated as a correction signal ΔVc of only the resistance component, and this ΔVc is added. It is added to the voltage Vi from the voltage setting device 6 in the device 11 to obtain the added value (ΔVc + Vi). Then, the multiplier 20 multiplies the added value by the output from the signal generator 10 to obtain the output voltage Vo in which the voltage drop (−ΔVc) in the winding resistance 2 is corrected. As described above, the output voltage Vo can be corrected even for the sample 3 formed of only the capacitive component.
【0027】図5は、位相検波回路15のスイッチSp
1を駆動する信号を生成する位相検出器16の一実施例
を示すと共に、タイミング関係を示している。そして、
本実施例では図2に示すように、トランスT1のL3巻
線からの信号を用いて位相検出器16に入力している
が、位相検出器16に入力する信号は、信号発生器10
からの信号と同相関係にあれば良いため、格別L3巻線
を用いる必要はない。FIG. 5 shows the switch Sp of the phase detection circuit 15.
An example of the phase detector 16 for generating a signal for driving 1 is shown and the timing relationship is shown. And
In the present embodiment, as shown in FIG. 2, the signal from the L3 winding of the transformer T1 is used for input to the phase detector 16, but the signal input to the phase detector 16 is the signal generator 10.
It is not necessary to use a special L3 winding because it only needs to be in phase with the signal from the.
【0028】これら請求項1及び請求項2の発明によ
り、5kVを印加して出力電流をゼロから最大電流の1
00mAに変化させた時の電圧変動率は、±0.5%以
内と言う実測結果を得ている。According to the first and second aspects of the invention, the output current is changed from zero to the maximum current of 1 by applying 5 kV.
The voltage fluctuation rate when changed to 00 mA is within ± 0.5%.
【0029】図3は、請求項3の発明即ちトランスT1
の発熱により巻線抵抗値2が増大して出力電圧Voが降
下することを補正する一実施例であり、以下に本請求項
3の発明及び図1と異なる構成部分について説明する。
周知の如く、巻線抵抗値2はプラスの温度係数を有して
いるため、トランスT1が発熱することにより該抵抗値
が増加して出力電圧Voを降下させかねない。このよう
なトランスT1の発熱によるレギュレーション特性を、
−ΔVtとすると、請求項1及び請求項2と同様、ΔV
tの補正電圧を生成して出力電圧Voを補正すれば良
い。請求項3の発明では、トランスT1の2次側巻線の
巻線の温度をサーミスタ等の温度検出素子に流れる電流
から温度補正電圧ΔVtを得、この電圧ΔVtと補正電
圧ΔVcとを加算し、更に電圧Viと加算することで出
力電圧を補正している。FIG. 3 shows the invention of claim 3 or the transformer T1.
This is an embodiment for correcting the fact that the winding resistance value 2 increases and the output voltage Vo drops due to the heat generation of 1. In the following, the invention of claim 3 and constituent parts different from FIG. 1 will be described.
As is well known, since the winding resistance value 2 has a positive temperature coefficient, the resistance value may increase due to heat generation of the transformer T1 and the output voltage Vo may drop. The regulation characteristic due to the heat generation of the transformer T1 is
Assuming −ΔVt, ΔV is the same as in claim 1 and claim 2.
The output voltage Vo may be corrected by generating a correction voltage of t. According to the invention of claim 3, the temperature of the winding of the secondary winding of the transformer T1 is obtained from a current flowing through a temperature detecting element such as a thermistor to obtain a temperature correction voltage ΔVt, and this voltage ΔVt and the correction voltage ΔVc are added, Further, the output voltage is corrected by adding it to the voltage Vi.
【0030】図3において、温度検出素子24は、トラ
ンスT1の2次側巻線の温度を検出するためのサーミス
タ抵抗器等であり、該巻線近辺に固着する。そして、該
温度検出素子24の抵抗値変化を温度/電圧変換器23
で電圧変換して温度補正電圧ΔVtを得る。なお、温度
補正電圧ΔVtの傾き調整と電圧増幅は、調整回路22
にて行う。図11は、前記調整回路22の一実施例を示
したもので、その動作説明は省略する。In FIG. 3, the temperature detecting element 24 is a thermistor resistor or the like for detecting the temperature of the secondary winding of the transformer T1 and is fixed near the winding. Then, the resistance value change of the temperature detecting element 24 is detected by the temperature / voltage converter 23.
The voltage is converted to obtain the temperature correction voltage ΔVt. The adjustment circuit 22 adjusts the slope of the temperature correction voltage ΔVt and voltage amplification.
Will be done at. FIG. 11 shows an embodiment of the adjusting circuit 22, and the explanation of its operation is omitted.
【0031】図3において、補正電圧ΔVc及び温度補
正電圧ΔVtを加算器21に入力し、前記加算器21の
出力を更に加算器11に入力して加算値(ΔVc+ΔV
t+Vi)を得、信号発生器10からの信号と該加算値
を、乗算器20及び増幅器30を介してトランスT1を
励磁してトランスT1の温度変化による電圧降下分を補
正する。以上ようにして、トランスT1の発熱による出
力電圧Voの降下を補正することができる。In FIG. 3, the correction voltage ΔVc and the temperature correction voltage ΔVt are input to the adder 21, and the output of the adder 21 is further input to the adder 11 to obtain the added value (ΔVc + ΔV).
t + Vi) is obtained, the transformer T1 is excited by the signal from the signal generator 10 and the added value via the multiplier 20 and the amplifier 30, and the voltage drop due to the temperature change of the transformer T1 is corrected. As described above, the drop of the output voltage Vo due to the heat generation of the transformer T1 can be corrected.
【0032】以上説明した通り、本発明によれば以下の
ような効果を奏することができる。
1) トランスT1の2次側巻線の巻線抵抗に起因する
電圧降下を供試物に流れる電流を検出し、該電流値の大
きさに応じた補正電圧を生成し、出力電圧の降下を補正
する耐電圧試験装置を実現できる。
2) 供試物の抵抗成分或は容量成分に関係なく、出力
電圧を補正できる。
3) 温度上昇によるトランスの2次側巻線の銅線抵抗
値が増大しても、出力温度依存性の少ない安定な耐電圧
試験装置を実現できる。
4) 帰還方式に起因する異常発振による動作不安定問
題を回避することができる。As described above, according to the present invention, the following effects can be obtained. 1) The voltage drop caused by the winding resistance of the secondary winding of the transformer T1 is detected as the current flowing through the DUT, and a correction voltage is generated according to the magnitude of the current value to reduce the output voltage drop. It is possible to realize a withstand voltage test device for correction. 2) The output voltage can be corrected regardless of the resistance component or capacitance component of the sample. 3) Even if the resistance value of the copper wire of the secondary winding of the transformer increases due to the temperature rise, it is possible to realize a stable withstand voltage test device with little output temperature dependency. 4) It is possible to avoid the problem of unstable operation due to abnormal oscillation due to the feedback method.
【図面の簡単な説明】[Brief description of drawings]
【図1】請求項1の発明の一実施例FIG. 1 is an embodiment of the invention of claim 1;
【図2】請求項2の発明の一実施例FIG. 2 is an embodiment of the invention of claim 2;
【図3】請求項3の発明の一実施例FIG. 3 is an embodiment of the invention of claim 3;
【図4】絶対値変換回路の一実施例FIG. 4 shows an embodiment of an absolute value conversion circuit.
【図5】位相検出器の一実施例FIG. 5: One embodiment of phase detector
【図6】(A)位相検波回路の一実施例FIG. 6A shows an example of a phase detection circuit.
【図6】(B)0°位相及び90°位相の検出電流波形
及び位相検波回路における電流波形とタイミング関係図FIG. 6B is a timing relationship diagram of detected current waveforms of 0 ° phase and 90 ° phase and current waveforms in the phase detection circuit.
【図7】レギュレーション特性と補正の関係[Fig. 7] Relationship between regulation characteristics and correction
【図8】出力等価回路と合成電流IoFIG. 8 is an output equivalent circuit and a synthetic current Io.
【図9】従来技術1FIG. 9 Prior Art 1
【図10】従来技術2FIG. 10 Related Art 2
【図11】温度検出回路の一実施例FIG. 11 is an example of a temperature detection circuit.
【図12】ローパスフィルタの一実施例FIG. 12 is an example of a low-pass filter.
1 :発振部 2 :巻線抵抗 3 :供試物 4 :可変抵抗器 6 :電圧設定器 7 :図10に示す乗算器 10:信号発生器 11:第1の加算器 13:積分器 14:増幅器 15:位相検波回路 16:位相検出器 20:乗算器 21:第2の加算器 22:調整回路 23:温度/電圧変換器 24:温度検出素子 30:電力増幅器 40:電流検出器 100:出力部 Vi:出力設定電圧 Vo:出力電圧 Io :出力電流 Rr :銅線抵抗 Rf :可変帰還抵抗 Rg :抵抗器 Rs :サーミスタ抵抗器 Rt :供試物3の抵抗成分 Ct :供試物3の容量成分 T、T1:トランス Ta、Tb:出力端子 1: Oscillator 2: Winding resistance 3: Sample 4: Variable resistor 6: Voltage setting device 7: multiplier shown in FIG. 10: Signal generator 11: first adder 13: integrator 14: Amplifier 15: Phase detection circuit 16: Phase detector 20: Multiplier 21: Second adder 22: Adjustment circuit 23: Temperature / voltage converter 24: Temperature detecting element 30: Power amplifier 40: Current detector 100: output section Vi: Output setting voltage Vo: Output voltage Io: Output current Rr: Copper wire resistance Rf: Variable feedback resistor Rg: resistor Rs: Thermistor resistor Rt: Resistance component of DUT 3 Ct: Volume component of DUT 3 T, T1: Transformer Ta, Tb: Output terminal
─────────────────────────────────────────────────────
─────────────────────────────────────────────────── ───
【手続補正書】[Procedure amendment]
【提出日】平成13年9月20日(2001.9.2
0)[Submission date] September 20, 2001 (2001.9.2)
0)
【手続補正2】[Procedure Amendment 2]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】図面の簡単な説明[Name of item to be corrected] Brief description of the drawing
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【図面の簡単な説明】[Brief description of drawings]
【図1】は請求項1の発明の一実施例を示す図である。 FIG. 1 is a diagram showing an embodiment of the invention of claim 1 ;
【図2】は請求項2の発明の一実施例を示す図である。 FIG. 2 is a diagram showing an embodiment of the invention of claim 2 ;
【図3】は請求項3の発明の一実施例を示す図である。 FIG. 3 is a diagram showing an embodiment of the invention of claim 3 ;
【図4】は絶対値変換回路の一実施例を示す図である。 FIG. 4 is a diagram showing an embodiment of an absolute value conversion circuit .
【図5】は位相検出器の一実施例を示す図である。 FIG. 5 is a diagram showing an embodiment of a phase detector .
【図6】(A)は位相検波回路の一実施例を示す図であ
る。(B)は0°位相及び90°位相の検出電流波形及
び位相検波回路における電流波形とタイミング関係を示
す図である。 6 (A) FIG der showing an embodiment of a phase detector circuit
It (B) shows the detected current waveform of 0 ° phase and 90 ° phase and the current waveform in the phase detection circuit and the timing relationship .
It is a figure.
【図7】はレギュレーション特性と補正の関係を示す図
である。 FIG. 7 is a diagram showing a relationship between regulation characteristics and correction .
Is.
【図8】は出力等価回路と合成電流Ioを示す図であ
る。 FIG. 8 is a diagram showing an output equivalent circuit and a combined current Io .
It
【図9】は従来技術1を示す図である。 FIG. 9 is a diagram showing Prior Art 1 .
【図10】は従来技術2を示す図である。 FIG. 10 is a diagram showing Prior Art 2 .
【図11】は温度検出回路の一実施例を示す図である。 FIG. 11 is a diagram showing an embodiment of a temperature detection circuit .
【図12】はローパスフィルタの一実施例を示す図であ
る。 FIG. 12 is a diagram showing an example of a low-pass filter .
It
【符号の説明】 1 :発振部 2 :巻線抵抗 3 :供試物 4 :可変抵抗器 6 :電圧設定器 7 :図10に示す乗算器 10:信号発生器 11:第1の加算器 13:積分器 14:増幅器 15:位相検波回路 16:位相検出器 20:乗算器 21:第2の加算器 22:調整回路 23:温度/電圧変換器 24:温度検出素子 30:電力増幅器 40:電流検出器 100:出力部 Vi:出力設定電圧 Vo:出力電圧 Io :出力電流 Rr :銅線抵抗 Rf :可変帰還抵抗 Rg :抵抗器 Rs :サーミスタ抵抗器 Rt :供試物3の抵抗成分 Ct :供試物3の容量成分 T、T1:トランス Ta、Tb:出力端子[Explanation of symbols] 1: Oscillator 2: Winding resistance 3: Sample 4: Variable resistor 6: Voltage setting device 7: multiplier shown in FIG. 10: Signal generator 11: first adder 13: integrator 14: Amplifier 15: Phase detection circuit 16: Phase detector 20: Multiplier 21: Second adder 22: Adjustment circuit 23: Temperature / voltage converter 24: Temperature detecting element 30: Power amplifier 40: Current detector 100: output section Vi: Output setting voltage Vo: Output voltage Io: Output current Rr: Copper wire resistance Rf: Variable feedback resistor Rg: resistor Rs: Thermistor resistor Rt: Resistance component of DUT 3 Ct: Volume component of DUT 3 T, T1: Transformer Ta, Tb: Output terminal
Claims (3)
磁して交流の高出力電圧を得、該出力電圧を供試物に印
加して電流検出器に流れる電流により耐電圧性能を試験
する耐電圧試験装置において、 前記電流検出器にて検出された検出値を直流化する直流
化手段を備え、 電圧設定手段及び第1の加算手段を備え、 前記直流化手段からの直流値と前記電圧設定手段からの
出力電圧を前記第1の加算手段にて加算し、 該加算値と前記交流信号源からの出力信号を乗算して出
力電圧を補正する乗算手段を備えることを特徴とする耐
電圧試験装置1. A high output voltage of an alternating current is obtained by exciting a transformer with an output signal of an alternating current signal source, the output voltage is applied to a sample, and a withstand voltage performance is tested by a current flowing through a current detector. In the withstanding voltage test apparatus, a direct current converting means for converting the detected value detected by the current detector into a direct current is provided, a voltage setting means and a first adding means are provided, and the direct current value from the direct current converting means and the voltage A withstand voltage, characterized in that the output voltage from the setting means is added by the first adding means, and a multiplying means for correcting the output voltage by multiplying the added value by the output signal from the AC signal source is provided. Test equipment
前記電流検出器からの検出値を整流する整流手段を備
え、 前記整流手段からの出力を前記直流化手段にて直流化
し、 該直流値と前記電圧設定手段からの出力電圧を前記第1
の加算手段にて加算することを特徴とする耐電圧試験装
置2. The rectifying means for rectifying a detection value from the current detector by a signal in phase with the output signal of the alternating current signal source, according to claim 1, wherein the output from the rectifying means is converted into the direct current. Means for converting the direct current value and the output voltage from the voltage setting means to the first
Withstanding voltage test device characterized by adding by means of adding means
段にて電圧変換し、 前記温度/電圧変換手段の出力と前記直流化手段からの
直流値を前記第2の加算手段にて加算し、 該加算値を前記第1の加算手段に入力することを特徴と
する耐電圧試験装置3. The method according to claim 1, further comprising: a temperature detecting unit and a temperature / voltage converting unit, a second adding unit, and a detection value from the temperature detecting unit to the temperature / voltage converting unit. Voltage conversion is performed, the output of the temperature / voltage conversion means and the DC value from the DC conversion means are added by the second addition means, and the added value is input to the first addition means. Withstanding voltage test equipment
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2001242957A JP4320695B2 (en) | 2001-07-05 | 2001-07-05 | Withstand voltage test equipment |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2001242957A JP4320695B2 (en) | 2001-07-05 | 2001-07-05 | Withstand voltage test equipment |
Publications (2)
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103675625A (en) * | 2013-12-12 | 2014-03-26 | 国家电网公司 | Alternating-current voltage withstand test device of converter valve with direct-current offset and test method of alternating-current voltage withstand test device |
KR101844825B1 (en) * | 2017-03-31 | 2018-04-04 | 한국전력공사 | Non-destructive safety eqiupment dielectric test apparatus and method |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103744003B (en) * | 2013-12-23 | 2016-10-19 | 广东威奇电工材料有限公司 | Automatically enamel-covered wire continuous detection apparatus and the method for detection enamel-covered wire breakdown voltage |
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JPS6125612U (en) * | 1984-07-18 | 1986-02-15 | 日置電機株式会社 | AC constant voltage constant current generator |
JPH03178555A (en) * | 1989-12-01 | 1991-08-02 | Matsushita Electric Ind Co Ltd | Inductance circuit and switching power source using the same |
JPH06121529A (en) * | 1992-10-01 | 1994-04-28 | Nemitsuku Ramuda Kk | Switching power supply |
JPH08160099A (en) * | 1994-12-06 | 1996-06-21 | Toshiba Corp | Dielectric strength testing device |
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JPH10336476A (en) * | 1997-05-28 | 1998-12-18 | Victor Co Of Japan Ltd | Horizontal deflection high voltage generating circuit |
JPH1113698A (en) * | 1997-06-27 | 1999-01-19 | Mitsubishi Electric Corp | Blower |
JPH11136938A (en) * | 1997-10-31 | 1999-05-21 | Fujitsu Denso Ltd | Dc-dc converter |
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JPS5388172U (en) * | 1976-12-22 | 1978-07-19 | ||
JPS6125612U (en) * | 1984-07-18 | 1986-02-15 | 日置電機株式会社 | AC constant voltage constant current generator |
JPH03178555A (en) * | 1989-12-01 | 1991-08-02 | Matsushita Electric Ind Co Ltd | Inductance circuit and switching power source using the same |
JPH06121529A (en) * | 1992-10-01 | 1994-04-28 | Nemitsuku Ramuda Kk | Switching power supply |
JPH08160099A (en) * | 1994-12-06 | 1996-06-21 | Toshiba Corp | Dielectric strength testing device |
JPH0934561A (en) * | 1995-07-17 | 1997-02-07 | Nec Corp | Load voltage stabilizing power unit |
JPH10336476A (en) * | 1997-05-28 | 1998-12-18 | Victor Co Of Japan Ltd | Horizontal deflection high voltage generating circuit |
JPH1113698A (en) * | 1997-06-27 | 1999-01-19 | Mitsubishi Electric Corp | Blower |
JPH11136938A (en) * | 1997-10-31 | 1999-05-21 | Fujitsu Denso Ltd | Dc-dc converter |
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Publication number | Priority date | Publication date | Assignee | Title |
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CN103675625A (en) * | 2013-12-12 | 2014-03-26 | 国家电网公司 | Alternating-current voltage withstand test device of converter valve with direct-current offset and test method of alternating-current voltage withstand test device |
KR101844825B1 (en) * | 2017-03-31 | 2018-04-04 | 한국전력공사 | Non-destructive safety eqiupment dielectric test apparatus and method |
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