JP2003018208A - Qos controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To practically improve the throughput of packets outputted from a single queue with respect to a QoS controller which is provided with a discrimination means which discriminates the service class of an input packet, a queuing means which enqueues it in a queue corresponding to the service class discrimination result, and a scheduler which calculates the interval and the sequence of packet dequeuing on the basis of parameters of lengths and arrival times of enqueued packets and controls dequeuing of packets. SOLUTION: The queuing means is provided with a distributed queuing means which dispersedly enqueues packets of a specific service class in many queues, and the scheduler is provided with an operation control means which dequeues packets while keeping the queuing sequence of dispersed enqueuing in many queues.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resource allocation method for guaranteeing QoS (Quality of Service) in a packet transfer device.

[0002] Against the backdrop of rapidly prevailing LAN and Internet, a router device (L
The market size of 3 switches (also called 3 switches) is expected to expand. Furthermore, not only data communication but also streaming services such as voice and video (moving images) are included.
Various applications are expected to be integrated and services provided on the IP network.

Required traffic characteristics (allowable discard rate, delay, etc.) such as data transfer such as FTP (File Transfer Protocol) and telephone service (VoIP: Voice Over IP)
In order to provide various different services in the IP network without stress, it is necessary to perform priority control according to the traffic flow and QoS control for bandwidth control in the router device or the like so as not to deteriorate the quality of each.

[0004]

2. Description of the Related Art FIG. 8 is a diagram showing the principle of QoS control, which will be described in the order of operation. Flow identification is performed on the input IP packet 80,
The IP address in the packet, the MAC address (Ethernet (registered trademark) address), and the TOS field (TypeOfService: information indicating the quality of the IP service included in the IP header, information about the priority and delay,
The flow number and the quality of each application are identified by referring to the information about throughput, the information about reliability, etc.). The IP packet is distributed (queued) to one queue 81 corresponding to the identified flow number. Priorities and bandwidths are set for the respective queues 81, and the order and timing of dequeuing the first packet of each queue are scheduled according to the length and queuing time of the first packet of the queue 81. The head packet of the queue determined by this scheduling is read (dequeued). By such processing, it becomes possible to perform QoS control for each flow distributed to the queue.

FIG. 9 shows the overall structure of the QoS control device.
In the figure, 90 is a packet (including an IP packet), 91 is a time stamp section for adding a time stamp (arrival time) to the input packet, and 92 is flow identification based on header information such as the destination of the input packet, It is a conversion table that has the function of allocating to an appropriate queue.
It is composed of M (Content Address Memory) and generates a queue number when header information is input. Reference numeral 93 is a queue management unit that logically links packet information for each queue and determines and manages a memory storage pointer for packet data. The queue management unit 93 stores a vacant position (queuing pointer) in each queue and each queue. The head position (dequeue pointer) of the packet is managed. 94 is the queue management unit 9
A memory control unit for receiving a pointer (address) of a packet to be queued (synonymous with enqueue) / dequeued in 3 and performing read / write control of a frame memory 95, which will be described later, and 95 is a physical memory forming a queue. A frame memory for storing the main body of packet data to be received, and 96 is a scheduler for inputting the schedule parameters of the first packet of the queue and calculating the order and timing for dequeue. The processing flow of this configuration is as follows (1) to (8).

(1) The time stamp unit 91 adds the arrival time to the input packet.

(2) The header information of the input packet and the schedule parameters (packet size, arrival time, etc.) are input to the conversion table 92, QoS identification is performed, and an appropriate queue number is obtained.

(3) The queue management unit 93 links the packet information to the designated queue, outputs the storage pointer of the queuing packet body to the frame memory 95, and gives a write instruction.

(4) By the processing of the memory control unit 94, the packet data is written to the designated queuing pointer.

(5) When the queued packet is at the head of the queue in the queue management unit 93, the schedule parameters (packet size, arrival time, etc.) of the packet are output to the scheduler 96.

(6) The scheduler 96 performs a scheduling process based on the schedule parameter information of the head packet of each queue, determines the order and timing of dequeue, and outputs the queue number.

(7) The queue management unit 93 receives a queue number to be dequeued, outputs a pointer in which the head packet of the queue exists, and gives a read instruction from the memory. Also, operate the link structure of queue management,
When there is a packet following the dequeued packet in the queue, the packet is regarded as the head and the schedule parameter of the packet is sent to the scheduler 96.

(8) By the processing of the memory control unit 94, the packet data is read from the dequeue pointer designated by the packet data.

FIG. 10 shows an example of the configuration of the conversion table 92 in the QoS control device shown in FIG. In the example of FIG. 10, the QoS flow identification process for allocating the destination IP address of the input packet to the six queues is performed.
For example, when the IP address is between 0010 and 00FF, the queue number is # 2.

The function of the scheduler 96 shown in FIG. 9 will be described.

The scheduler algorithm has a plurality of
There is a method, but here is the algorithm for bandwidth control.
An example is shown. Bandwidth control is preset for each queue
Dequeue packets in queue to protect reserved bandwidth
Control of the timing. Reserved bandwidth for each queue (fast
Degree, φ, the packet to be scheduled (at the head of the queue
(Packet) is L, and the length is φ.
The time required to send L packets depends on L / φ
Desired. Bandwidth control method is to complete transmission of each packet
Calculate the scheduled time (let's call it F) and
With a run timer (a timer that displays the current absolute time)
By comparing and allowing sending at the scheduled time
is there. That is, do not dequeue until the scheduled time
The bandwidth is controlled by controlling the packet interval. i number
F is the estimated time to complete the transmission of the packet _iThen, F_iIs
It is calculated by the following equation (1).

F _i = max {F _i-1 M _i } + Li / φi (1) where M _i is the time when the _i- th packet is queued, and F _i-1 is the transmission completion of the previous packet. Scheduled time, L
i / φi is the i-th packet (packet length Li, speed φ
i) represents the time it takes to send out.

FIG. 11 shows the concept of bandwidth control and shows two cases for protecting the reserved bandwidth.

Referring to FIG. Is Mi <F _i−1 , and the transmission completion scheduled time F of the previous packet (i−1th packet) is
Current packet (i-th packet) at time Mi before _i-1
Is queued. In this case, the transmission completion time of the current packet is added to the transmission completion time F _{i-1 of} the previous packet by adding the time Li / φi (indicated by L / φ in the figure, the same applies hereinafter) required to transmit the current packet. Calculate F _i . B. of FIG. In the case of Mi ≧ F _i−1 , the current packet is queued at time Mi after the scheduled transmission completion time F _i−1 of the previous packet. In this case, as shown in the figure, L / φ is added to the time Mi to calculate the transmission completion scheduled time F _i of the current packet.

In this way, the queue targeted by the scheduler A.A of FIG. Or B. Is calculated and is constantly compared with the timer, and dequeue processing is performed on the queue when the scheduled time arrives. When packets can be output simultaneously from a plurality of queues, the scheduler performs priority control arbitration so that the queue with the smallest F _i is dequeued, and outputs the arbitration result.

FIG. 12 shows an example of the configuration of a conventional scheduler having such a function. In the figure, 960 is the above formula (1)
Represents an arithmetic unit for performing the above calculation, and the arithmetic unit is provided for each queue. In this example, 6 of # 1 to # 6 are associated with 6 queues.
It is provided individually. The inside of each computing unit is the same 961
˜965. 961 is the reciprocal of the packet length (represented by L (a)) and speed (represented by φ (a)) (1 /
φ (a)) and outputs the time required to transmit the packet (represented by MUL), 962 indicates the queuing time of the current packet (represented by M (a)) and the transmission of the previous packet. A maximum value selection unit (denoted by MAX) that compares the scheduled time (F _i-1 ) with the larger time, 963 is an adder, and 964 is a holding unit that holds the time output from the adder 963. (Represented by FF), 965 is a comparator (indicated by CMP) for detecting whether the time of the holding unit 964 coincides with the time of the free-run timer 966, 966 counts by the master clock, and counts in each arithmetic unit 960. It is a free-run timer that outputs a value (timer value). Also, 9
Reference numeral 67 denotes a minimum value selection unit that selects the minimum value from the output F (n) values that represent the valid time input from each computing unit 960 and outputs a dequeue instruction.

The operation of the configuration example of the conventional scheduler shown in FIG. 12 will be described. A new packet schedule parameter (packet length L (a) and queuing time M) is added.
(a)) is input from the queue management unit (93 in FIG. 9), the time required for transmission calculated by the multiplier 961 from the packet length L (a) and the reciprocal of the speed (1 / φ (a)) ( L (a) /
φ (a)) is calculated, M (a) (queuing time) and F _i-1 (scheduled transmission completion time of the previous packet) are compared by the maximum value selection unit 962, and the larger one is selected. At this time, the A. In case of _F.sub.i-1 , _F.sub.i-1 is selected, and B.I. In the case of, M (a) is selected. In the adder 963, L (a) / φ (a) from the multiplier 961 and M (a) from the maximum value selection unit 962
Or F _i-1 is added, F _i in the formula (1) is held by the holding portion 964 is demanded, transmission completion scheduled before the packet to the maximum value selection unit 962 is output to the comparator 965 time F Supplied as _i-1 . The comparator 965 compares the F _i value with the timer value, and when the sending time comes, outputs a flag (valid flag) that permits sending to the minimum value selecting unit 967. The minimum value selection unit 967 selects the arithmetic unit having the smallest scheduled transmission completion time F _i from the arithmetic units 960 in which the valid flag is asserted, and outputs the number (queue number) of the arithmetic unit. The computing unit that outputs the queue number
Negate the valid flag.

The above is the configuration of the scheduler for realizing the band control and the processing contents thereof. In order to perform this arithmetic processing, a processing latency (delay) of several clocks is usually required.

When the above bandwidth control is performed, the queue management unit (93 in FIG. 9) controls the packet in order to store it in the queue (queuing) or output it (dequeue). In queue management, the packet link structure in each queue is managed by the packet storage address (pointer) to the frame memory (95 in FIG. 9).

FIG. 13 shows the configuration of the queue management unit. In the figure, reference numeral 930 denotes an enqueue (or queuing) control unit for controlling the storage of the packet in the queue when the queue number and the schedule parameter of the packet are input. 931 indicates the top (Top) and the end (En) of each queue.
d) Queue Top / End pointer memory that stores the storage position (pointer) of the packet, 932 is a pointer link memory that stores the pointer link structure in the queue and the schedule parameter of the packet, and 933 is a control that extracts the packet from each queue. Dequeue control unit,
An empty pointer memory 934 stores an empty pointer of each queue (a pointer that can store a packet next).

FIG. 14 shows a link structure of packet information, which includes the pointer memories 931 and 932 of the queue management unit shown in FIG.

FIG. 14A. Shows an example of packet queuing of queue number #n, in which the packets of pointers b to g are queued in order with the pointer a as the leading pointer. B. of FIG. ~ D. A of FIG. The packet link structure of the queue number #n of B. Corresponds to the queue Top / End pointer memory 930 shown in FIG. The pointer a is stored in the Top pointer memory and the pointer g is stored in the End pointer memory corresponding to the queuing of the queue number #n. C. of FIG. Is a pointer memory, D. Is a parameter memory, and both correspond to the pointer link memory 932 in FIG. The pointer link memory is the above T
A pointer b in which the next packet is stored is set in the pointer a indicated by the op pointer memory, and a pointer c in which the next packet is further stored in the position indicated by the pointer b.
Is set, and the above A. The next pointer is set in order up to the last pointer g indicated by the End pointer memory.
Also, as shown in FIG. Each parameter (packet length, arrival time, etc.) of the packet is stored in the parameter memory of B. The pointer memory is linked to the packet pointer and set in order. The empty pointer memory 934 of FIG. 13 is not shown in FIG.

In the configuration of FIG. 13, when performing queuing processing, the queue Top / End pointer memory 93
The End pointer of the queue number to be queued from 1 is taken out, the link pointer of the pointer link memory 932 indicated by the pointer is taken out, the parameter is further stored at the address indicated by the pointer, and the queue Top
/ End pointer The process of updating the End pointer in the memory 931 is performed. When dequeuing, queue Top /
The Top pointer is taken out from the End pointer memory 931 and the processing for updating the link structure is performed. Although detailed processing during queuing / dequeuing is omitted, memory access is required several times to perform queue management processing. That is, the queue management process requires a processing latency of several clocks.

[0029]

As described above, both the scheduler process and the queue management process require a processing latency of several clocks. Here, the processing when the packets staying in a certain single queue are continuously dequeued will be described.

When the dequeue instruction is output from the scheduler, the queue instructed by the queue management unit is dequeued, and the packet queued next to the dequeued packet is at the head of the queue. Output to the scheduler. If continuous,
This process is repeated. As can be seen, even if the speed (throughput) of the continuous dequeuing from a single queue is the fastest, the processing latency (denoted by B) in the scheduler and the dequeuing instruction in the queue management unit are received. It is not possible to reduce the packet interval below the total latency (A) before the scheduler parameter of the next packet is output to the scheduler.

FIG. 15 shows a processing sequence for continuous dequeuing from a single queue. That is, when the headers of four packets 1 to 4 are sequentially input to the same queue (same destination) to the queue management unit, the queue management unit supplies the schedule parameter of packet 1 to the scheduler. The scheduler processes the packet 1, and after the latency B, the packet 1 is dequeued. The scheduler thereby sends the queue management unit an instruction 1'for dequeuing the next packet. Upon receiving this, the queue management unit outputs the schedule parameter of the next packet 2 to the scheduler after the process requiring the latency A, and the scheduler dequeues the packet 2 after the latency B. Hereinafter, similarly, the packets 2 to 4 are dequeued at the dequeue interval A + B.

Even when high throughput (keeping the interval between packets in a single queue) is required as described above, the latency is limited by A + B. this is,
Although it is a physical limitation, in some cases, throughput may be required rather than elaborate QoS control (that is, QoS control including calculation for performing bandwidth control). If both bandwidth control and throughput are not compatible,
It is desired that the flow that performs bandwidth control based on the flow identification result and the flow that does not perform bandwidth control but can ensure throughput be able to perform QoS control that meets each request with a single device. Could not be realized.

The present invention is based on the realization of bandwidth control for packet transfer, and can substantially improve the throughput of packets output from a single queue.
An object is to provide a control device.

[0034]

FIG. 1 is a diagram showing the principle configuration of the present invention. In the figure, 1 is a flow identifying means for identifying a flow and generating a queue number assigned to the flow, 2 is a queuing means for queuing a packet to the queue number generated by the flow identifying means 1, 20 Is a distributed queuing means for distributing and queuing packets having the same flow number to a plurality of queues, 3 is a queue, 3-1, 3-2, ... 3-m are individual queue numbers, and 3- 21 to 3-2n are a plurality of distributed queues provided for queue numbers (3-2 in this example) assigned to a certain flow. Reference numeral 4 denotes a scheduler that controls dequeuing of packets queued in the normal queue and the distributed queue.

Since the present invention cannot achieve the bandwidth control and the throughput at the same time, the QoS control according to each request is performed by the flow identification. That is, a flow for which bandwidth control is desired is queued in a normal bandwidth control queue, and a flow for which throughput is desired is to be processed by stopping bandwidth control and ensuring throughput.
Specifically, ensuring the throughput with a single queue is shown in FIG.
Since it is impossible as shown in 5, the principle is to improve the apparent throughput by distributing the processing to a plurality of queues.

The flow identification means 1 identifies a flow number from the header of an input packet and converts it into a queue number assigned corresponding to each flow characteristic (destination, application, QoS characteristic, etc.). When a queue number (3-2 in this example) corresponding to a specific flow number required to ensure throughput occurs, the distributed queuing means 20 is driven and a queue corresponding to a specific input flow number is input. The first queue 3-21 in the number n of distributed queues 3-21-3-2n
Is assigned to queue the corresponding packet, and the next input packet with the same flow number as above is assigned to the next queue 3-22. Below, the packets with the same flow number are sequentially 3-23, 3-24. ,, ..., 3-
When n is reached, the process returns to the first queue 3-21. Queues are assigned by assigning queues 3-1, 3-3, ... To each flow number for which throughput control is not required. That is, a plurality of distributed queues are regarded as one virtual queue and distributed queuing is performed for a packet of a specific flow number for which a throughput is required to be secured. However, with this measure alone, the packets are dequeued because the order of the packets is changed because they are distributed to multiple queues. In order to prevent this, the distributed queue 3-21, 3-2
2, ... 3-2n scheduler 4 includes arithmetic control means 40
The queue is selected from a large number of queues and dequeued by one of the following methods by the arithmetic control in.

With respect to the distributed queue, the arithmetic control means 40 of the scheduler 4 uses the bandwidth control algorithm to set the reserved bandwidth of the distributed queue to the same, ignores the packet length of the processing packet, and regards it as fixed and performs processing.

With respect to the distributed queue, the scheduler 4 determines the order of dequeuing the packet from the earliest (smaller) time queued in the distributed queue.

Packets to be queued in the distributed queue by the distributed queuing means 20 are sequentially numbered in the order of input, and the scheduler 4 of the distributed queue performs a process of determining the dequeue order based on the size relationship of the numbers.

By the processing of the distributed queue scheduler 4 as described above, it is possible to dequeue while maintaining the order of queuing in the distributed queue. Distributing a flow into n queues makes it possible to dequeue with apparently n times the throughput of a single queue.

[0041]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 2 shows the construction of a destination address conversion table according to an embodiment. In the figure, 10 is a first conversion table for converting a destination IP address into a queue number, and 20 is a second conversion table for converting a queue number into a queue number including a distributed queue.
It is a conversion table. In this embodiment, six queues are used, but three of them are used as one virtual queue, and the physical queue numbers # 4 to # 6 are used as the queue number # 4.
Used as a virtual single queue for.

When the destination IP address included in the header of the input packet is detected, the first conversion table 10 is searched for the destination IP address. If the destination IP address is in the range of "0000 to 000F", the queue number is #
1 is output, and when the destination IP address is within the range of “0010 to 00FF”, # 2 is output as the queue number, and the destination IP
If the address is in the range of "0100-01FF", # 4 is output as the queue number, and the destination IP address is "0200-FF".
If it is within the range of "FF", # 3 is output as the queue number. For the flow whose destination IP address is in the range of “0100 to 01FF”, when the virtual queue number # 4 is output for queuing to the virtual queue, the second conversion table 20 at the subsequent stage further outputs. , The virtual queue number # 4 is sequentially converted into the distributed physical queue numbers # 4 to # 6. The conversion algorithm of the second conversion table 20 is shown in FIG.

FIG. 3 is a flowchart for converting a virtual queue number into a distributed physical queue number. When the queue number (virtual queue number) is obtained from the packet flow number by the first conversion table of FIG. 2, the processing of FIG. 3 is started. However, i is a variable (initial value is 0) and q is a queue number (virtual queue number and physical queue number). Q, which is the queue number (virtual queue number) input first
Is # 4 (S1 in FIG. 3). If q is not # 4, the process ends without converting the queue number.
When q = # 4, i is incremented by 1 (S2 in FIG. 3), i> 2
If it is assumed that i is 0 at first, it is determined to be no (No), the value of q is updated to q + i (S5), q + 1 = 5 is obtained, and distributed physics is obtained. # 5 is output as the queue number, and the process ends. Thus, the first packet is assigned to the distributed physical queue # 5. Next, when the queue with the virtual queue number # 4 is input, the i = i + 1 process is executed according to the flow chart of FIG.
= 2, but no (N
o), q = 6, and the distributed queue is #
6 is assigned. Next, when the packet of # 4 is input, i = 3 by the calculation of i = i + 1 (S2 in FIG. 3). In this case, when it is determined whether i> 2 (S3 in FIG. 3), it is determined to be Yes, and i = 0 is set (at the same S
4), q = q + i results in # 4 + 0, and the distributed physical queue number becomes # 4.

In this way, the flow of the virtual queue number of # 4 for which the throughput is desired to be secured (single flow number)
Only the packets of # 4 are distributed and queued in a plurality of queues # 4 to # 6.

Next, the configuration of each embodiment of the scheduler according to the present invention will be shown.

FIG. 4 shows the configuration of the scheduler according to the first embodiment. In the figure, 40-1 to 40-6 are arithmetic units (corresponding to the arithmetic units # 1, ...
The arithmetic units # 1 to # 3 are not associated with the distributed physical queue but are assigned to the queue numbers corresponding to the flows.
60), and the arithmetic units # 4 to # 6 are configured as distributed physical queues. In the computing units # 1 to # 3,
Multiplier (MUL) 41, maximum value selection unit (MAX) 42,
The adder 43, the holding unit 44, the comparator (CMP) 45, the free-run timer 47, and the minimum value selecting unit 48 are the same as the circuits represented by the reference numerals 961 to 967 in FIG. Since # 1 to # 3 perform the same operation as the above-described conventional one, the description thereof will be omitted.

The computing units # 4 to # 6 are assigned the virtual queue number 4 (# 4) for storing a packet of a certain single flow, as described with reference to FIGS. 2 and 3, and assign this to three distributed physical queues. Performs an operation for dequeuing after distributed storage. These arithmetic units # 4 to # 6 are the arithmetic units # 1 to #.
A selection unit (SEL) represented by reference numeral 46 is added to the configuration of FIG. These selectors 46 send packet lengths (L (d), L
(e), L (f)) or "0" is selected by the virtual queue switching control signal.

When constructing the distributed physical queue for the virtual queue according to the present invention, the packet length is compulsorily switched to "0" by the virtual queue switching control signal. Note that a fixed packet length may be input instead of this “0”.

According to the second conversion table of FIG. 2, the queuing to the virtual queue # 4 is actually queued to the distributed physical queue numbers # 4 to # 6. In # 4 to # 6, the packet length is considered to be zero, so in the above equation (1), Fi = Mi
Becomes However, F _i represents the scheduled transmission completion time of the i-th packet, and M _i represents the time when the i-th packet was queued. Therefore, the minimum value selection unit 48, which is in the subsequent stage of the arithmetic units # 1 to # 6, selects and outputs the one having the smallest F _i value, and therefore the dequeuing order of the queue numbers # 4 to # 6 is
The order of the time M _i queued in each queue will be followed. In other words, the same operation as in the case of queuing in a single queue can be obtained by distributed queuing in a plurality of queues. In this example, by performing distributed queuing on three queues, it is possible to process with a throughput three times higher than that when queuing on a single queue. Further, when the flow requiring throughput is not handled, the selection unit (SEL) 46 in the arithmetic units # 4 to # 6 in FIG. 4 sets the packet length (L (d), L (e), L (f )) Can be switched so that a bandwidth-controllable arithmetic unit can be configured and can be selected as required.

FIG. 5 shows the configuration of the scheduler of the second embodiment. In the figure, 40-1 to 40-3 are arithmetic units (arithmetic unit # 1, arithmetic unit # 1) provided corresponding to each of the three queues.
2, the computing unit # 3) is provided for each queue number corresponding to the flow. 48-1 is a first minimum value selection unit. The configuration inside the computing units # 1 to # 3 is the same as that of the computing units # 1 to # 3 in the configuration of the first embodiment shown in FIG. 4, and the same operation as the conventional computing unit (960 in FIG. 12) is performed. , The first minimum value selection unit 48-1 has valid indications from the arithmetic units # 1 to # 3 and at the same time the scheduled transmission completion time F (a)
Outputs the queue number having the smallest value in F (c) as a result of bandwidth control.

The structure that characterizes this second embodiment is 49-
The point is that a register represented by 1 to 49-3, a second minimum value selection unit represented by 48-2, and a priority control selection unit represented by 50 are provided. Registers 49-1 to 49-3 are used for arrival times (M) of packets input to the virtual distributed queues (# 4 to # 6).
Only (d), M (e) and M (f)) are retained. The queue having the earliest arrival time is the second minimum value selection unit 48-2.
To output the cue number. The output of the result of the bandwidth control from the first minimum value selection unit 48-1 and the output of the queue numbers in the order of arrival time from the second minimum value selection unit 48-2 are sent to the priority control selection unit 50. Input, select the queue number with the priority according to the system request, and output.
As a result, it is possible to configure a highly flexible scheduler that can switch between the case where the queue for which the throughput is desired to be prioritized and the case where the bandwidth control is prioritized according to the request of the system. The register 49
When the contents of -1 to 49-3 are dequeued, they are updated at the queuing time of the subsequent packet of the same flow.

FIG. 6 shows the configuration of the scheduler of the third embodiment. In the figure, 40-1 to 40-3 are the second embodiment (FIG. 5).
Arithmetic units (# 1 to # 3) having the same configuration as the above, 48-1
Is a first minimum value selection unit similar to the second embodiment.

The constitution which is characteristic of the third embodiment is 51-
1 to 51-3, a third minimum value selection unit represented by 48-3, and a priority control selection unit represented by 52. The registers 51-1 to 51-3 hold, as an input parameter of the virtual distributed queue (# 4 to # 6), the sequential numbers added to the packets queued in the virtual distributed queue. In this case, since the packets belong to the same flow number, the sequential number represents the arrival order. The third minimum value selection unit 48-3 selects the queue number to be dequeued according to the order of being queued in the virtual distributed queue by the sequential number. The priority control selection unit 52 uses the queue number selected by the first minimum value selection unit 48-1 and the queue number from the third minimum value selection unit 48-3 to request the system in the same manner as in the second embodiment. Priority according to the following (when the priority is given to the bandwidth control, the queue number from the first minimum value selection unit 48-1 is given priority, and when the throughput is given priority, the queue from the third minimum value selection unit 48-3 is given. Select the control with (number has priority).

FIG. 7 shows an example of the processing sequence of the scheduler of the embodiment. This is a processing sequence when a single flow (virtual queue number # 4) is distributed to three distributed queues (# 4 to # 6) by the schedulers of the above-described first to third embodiments. The same processing sequence is used in each embodiment.

In FIG. 7, six packets belonging to the same flow number (# 4) are distributed queues # 4 to # 6.
It is an example in which it is distributed and stored in "1", "2",
Packets of "3" are stored in the distribution queues # 4 to # 6 in the order in which they arrive at each of the distributed queues # 4 to # 6 with a slight time interval under the control of the queue management unit (93 and FIG. 13 in FIG. 9). Packets of "4", "5", and "6" input thereafter are similarly stored in the distribution queues # 4 to # 6. The packets of the distributed queues # 4 to # 6 are provided for the distributed queues provided in the scheduler by the arithmetic unit (Embodiment 1 of FIG. 4).
Either the register for storing the queuing time (Embodiment 2 in FIG. 5) or the sequential number (Embodiment 3 in FIG. 6) is used to store the packet of “1” in distributed queue # 4. The queue is dequeued after the processing latency B in the scheduler, and at the same time, a dequeue completion notification (denoted by 1 ') is sent to the queue management unit. Following this, the distributed queue # 5 stores the packet of "2" and then dequeues after the time B, and the distributed queue # 6 also dequeues the packet of "3" after the time B. Then, in the distributed queue # 4, after the notification 1'of the dequeuing completion of the packet of "1", the processing time A of the queue management unit has elapsed and the packet of "4" is stored, and the processing time B of the scheduler Later, it is dequeued. Below, each distributed queue #
5 and # 6, the packet of "5" and the packet of "6" are dequeued with the same latency.

In this way, "1" ...
Compared to the case of storing and dequeuing "6" packets, by performing parallel processing with three queues, three packets can be dequeued within the processing latency of A + B, and triple throughput can be obtained. I understand that.

(Supplementary Note 1) Identification means for identifying the service class of the input packet, queuing means for queuing in a queue according to the service class identification result, and parameters for the length and arrival time of the queued packet Q having a scheduler that performs packet dequeue control by calculating the packet dequeue interval and order based on the original
In the oS control device, the queuing means includes a distributed queuing means that distributes and queues packets of a specific service class into a plurality of queues, and the scheduler distributes and queues the packets in the plurality of queues. A QoS control device comprising arithmetic control means for dequeuing packets while maintaining the queuing order at time.

(Supplementary Note 2) In Supplementary Note 1, the arithmetic control means provided in the scheduler regards the packet lengths of all target packets as fixed, with the reserved bandwidths set for a plurality of distributed queues being the same. A QoS control device characterized by determining the order of dequeuing according to the above.

(Supplementary Note 3) In Supplementary Note 2, the QoS control is characterized in that the dequeuing order is determined based on the queuing time of each packet by setting 0 when the packet length is fixed. apparatus.

(Supplementary Note 4) In any one of Supplementary Notes 2 or 3, the dequeue instruction generated from the arithmetic control means provided in each of the distributed queues is input and has the minimum value among the plurality of dequeue instructions. A QoS control device comprising a minimum value selection unit that selects an instruction and outputs information of a corresponding queue.

(Supplementary Note 5) In Supplementary Note 1, the arithmetic control means provided in the scheduler receives the queuing time for each queue as information for determining the queuing order for a plurality of distributed queues. Qo characterized by including a selection unit for selecting the minimum value from
S control device.

(Supplementary Note 6) In Supplementary Note 1, when the distributed queuing means distributes and queues a specific flow in a plurality of queues, sequential numbers are added to the packets in the order of arrival, and the scheduler described above. A QoS control device, characterized in that the dequeuing order is determined by detecting the magnitude relationship of the sequential numbers added to the packets of each distributed plurality of queues.

(Supplementary Note 7) Identification means for identifying the service class of the input packet, queuing means for queuing in the queue according to the service class identification result, and parameters for the length of the queued packet and the arrival time. In a QoS control device having a scheduler for performing packet dequeue control by calculating a packet dequeue interval and order based on the above, the service class identified by the identifying means gives priority to bandwidth control or to ensure throughput. The queuing means assigns an individual queue to a service class that prioritizes bandwidth control, queues packets, and queues packets for a service class that prioritizes ensuring throughput. And the queues are distributed to A QoS control device for dequeuing packets queued in a queue in a queuing order.

[0064]

According to the present invention, the throughput can be improved by allocating a plurality of distributed queues to the packet of the designated flow with a simple structure. In addition, it becomes possible to select whether to perform bandwidth control or throughput control for the flow according to the system requirements.

[Brief description of drawings]

FIG. 1 is a diagram showing a principle configuration of the present invention.

FIG. 2 is a diagram showing a configuration of a destination address conversion table according to the embodiment.

FIG. 3 is a diagram showing a flowchart for converting a virtual queue number into a distributed physical queue number.

FIG. 4 is a diagram showing a configuration of a scheduler according to the first embodiment.

FIG. 5 is a diagram showing a configuration of a scheduler according to a second embodiment.

FIG. 6 illustrates a configuration of a scheduler according to a third exemplary embodiment.

FIG. 7 is a diagram showing an example of a processing sequence of a scheduler of the embodiment.

FIG. 8 is a diagram showing the principle of QoS control.

FIG. 9 is a diagram showing an overall configuration of a QoS control device.

FIG. 10 is a diagram showing a configuration example of a conversion table in the QoS control device.

FIG. 11 is a diagram showing a concept of band control.

FIG. 12 is a diagram showing a configuration example of a conventional scheduler.

FIG. 13 is a diagram showing a configuration of a queue management unit.

FIG. 14 is a diagram showing a link structure of packet information.

FIG. 15 is a diagram showing a processing sequence during continuous dequeuing from a single queue.

[Explanation of symbols]

1 Flow identification means 2 queuing means 20 distributed queuing means 3-1, 3-2, ... 3-m cue 3-21-3-2n distributed queue 4 scheduler 40 arithmetic control means

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Takahiro Kobayakawa             3-22-8, Hakata Station, Hakata-ku, Fukuoka City, Fukuoka Prefecture             Issue Fujitsu Kyushu Digital Technology Co., Ltd.             Inside the company F term (reference) 5K030 HA08 HB15 KA03 KX18 LE01                       MB15

Claims (5)

[Claims] 1. An identification unit for identifying a service class of an input packet, a queuing unit for queuing in a queue according to a service class identification result, and parameters of a length and an arrival time of a queued packet. In a QoS controller provided with a scheduler for calculating packet dequeue interval and order to perform packet dequeue control, the queuing means distributes packets of a specific service class to a plurality of queues and queues them. A QoS control apparatus comprising: an queuing means, and the scheduler comprising an arithmetic control means for dequeuing a packet while maintaining a queuing order when distributed and queued in the plurality of queues. 2. The arithmetic control means provided in the scheduler according to claim 1, wherein the reserved bandwidths set for a plurality of distributed queues are the same, and the packet lengths of all target packets are regarded as fixed. A QoS controller characterized by determining the order of dequeuing. 3. The arithmetic control means provided in the scheduler according to claim 1, wherein the queuing time for each queue is input as information for determining the queuing order for a plurality of distributed queues, and the A QoS control device comprising a selection unit for selecting a minimum value. 4. The distributed queuing means according to claim 1, wherein when a specific flow is distributed and queued in a plurality of queues, sequential numbers are added to packets in order of arrival, and the scheduler is configured to A QoS control device, characterized in that the dequeuing order is determined by detecting the magnitude relation of the sequential numbers added to the packets of a plurality of distributed queues. 5. An identification unit for identifying a service class of an input packet, a queuing unit for queuing in a queue according to a service class identification result, and parameters of a length and an arrival time of the queued packet. In a QoS control device provided with a scheduler for calculating packet dequeue interval and sequence to perform packet dequeue control, it is determined whether the service class identified by the identifying means gives priority to bandwidth control or to ensure throughput. The queuing means allocates an individual queue to a service class that prioritizes bandwidth control, queues packets, and distributes the packets to a plurality of queues for a service class that prioritizes ensuring throughput. And the scheduler is
A QoS control device for dequeuing packets queued in each of the queues while maintaining a queuing order.