JP2003017686A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device compensating negative fixed electric charges generated in a gate insulation film in the case of using Al2 O3 and Ln2 O3 for the film and suppressing the shift of a flat band voltage, and to provide the manufacturing method. SOLUTION: In the semiconductor device provided with the gate insulation film on a silicon single crystal substrate, the gate insulation film is provided with the composition of A1-x Bx Oy (x=0.01 to 0.3, y=1.5 to 3.0, A is a group III metal, B is at least one of a group V metal and a group VI metal) and is also composed of the multiple layers of the layer composed of one or more kinds of a silicon oxidie and a silicon nitride and the layer provided with the composition of A1-x Bx Oy (x=0.01 to 0.3, y=1.5 to 3.0, A is the group III metal, B is one or more kinds of the group V metal and the group VI metal).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a novel semiconductor device and a method for manufacturing the same, and more particularly to an M having a gate insulating film.
The present invention relates to an IS type transistor element and a manufacturing method thereof.

[0002]

2. Description of the Related Art In recent years, MIS (Metal Insul)
The miniaturization of attor semiconductor (transistor) type transistor devices is in the situation of approaching to a gate length of <0.1 μm. With such miniaturization, MIS
As a material for the gate insulating film of the p-type transistor element, use of a material having a relative dielectric constant of 3.9 and a higher dielectric constant than that of SiO ₂ has been studied. Since these materials have a high relative dielectric constant, the same gate capacitance as that of SiO ₂ can be obtained while the physical film thickness is large. Therefore, it is considered that even when the element is miniaturized according to the scaling rule, the leak current between the gate and the substrate due to the direct tunneling in the gate insulating film can be suppressed.

From the viewpoint of high thermal stability on the Si substrate, Schottky barrier, and oxygen diffusion, it is considered that the oxide of the group III element is effective for the gate insulating film having a high dielectric constant. A
L ₂ O ₃ and Ln ₂ O ₃ (Ln: rare earth element) are known to have a relative dielectric constant of about 10 and 10 to 20, respectively. By replacing the conventional SiO ₂ with the above materials, the physical film thickness can be increased to about 2.5 times and 2.5 to 5 times.

[0004]

However, when Al ₂ O ₃ and Ln ₂ O ₃ (Ln: lanthanoid element) are used for the gate insulating film, a negative effect caused by defects in the film or at the Si interface is generated. The problem is that fixed charges are generated and the flat band voltage shifts. The shift of the flat band voltage shifts the threshold value of the MIS transistor.

Further, in a gate insulating film using Al ₂ O ₃ and Ln ₂ O ₃ , a fixed charge is generated in the film due to a moisture absorption reaction, and similarly, a flat band voltage shifts. . Furthermore, in order to satisfy the demand for further miniaturization, a gate insulating film having a higher dielectric constant is required.

An object of the present invention is to use Al ₂ O as a gate insulating film.
₃ and Ln ₂ O ₃ are used to compensate for the negative fixed charges generated in the film and to provide a semiconductor device in which the shift of the flat band voltage is suppressed and a manufacturing method thereof.

[0007]

The present invention relates to a semiconductor device having a gate insulating film on a silicon single crystal substrate, and more specifically, an element isolation insulating film and a gate insulating film on a silicon single crystal substrate. A gate electrode formed on the gate insulating film, source and drain regions formed on both sides of the gate insulating film between the element separating insulating film and the gate insulating film, and the element separating An insulating film, a gate insulating film, a gate electrode, a protective film for protecting the source and drain regions, a plug electrode formed in contact with each of the source and drain regions and penetrating the protective film, and a plug electrode In the semiconductor device having a wiring formed in contact with the protective film, the gate insulating film is A
_{1-x B x O y (} x = 0.01~0.3, y = 1.5~
3.0, A is a group III metal, and B is one or more of group V metal and group VI metal).

That is, a feature of the present invention is that, in a MIS type transistor device using a silicon single crystal substrate as a base material, x is 0.01 to 0.3, preferably 0.01 or more and 0.3 as a gate insulating film. less, y is 1.5 to 3.0, preferably has a composition of _{a 1-x} B _{x O y} is less than 1.5 to 3.0, wherein a is group III metal, the B group V Metal and V
There is at least one, and preferably one, Group I metal.

Generally, the group III metal in the oxide is +
Although it is a trivalent ion, it is possible to add a positive charge by compensating a group V or group VI metal element having a valence of +5 or +6 to compensate for a fixed negative charge.
This effect can be obtained when the element ratio of the group V and group VI metal elements to be dissolved is 0.01 or more.

On the other hand, the oxide of the group III element has a high thermal stability on the Si substrate, whereas the oxide of the group V and VI elements which form a solid solution has a high thermal stability on the Si substrate. Low. Therefore, when the oxides of the V group and VI group elements are formed on the Si substrate, a SiO ₂ layer having a low dielectric constant is formed at the Si interface. When the ratio of the group V or group VI metal elements to be dissolved is set to 0.3 or more in terms of element ratio, the group III element oxide loses thermal stability on the Si substrate, and SiO at the Si interface.
_This promotes the growth of the _two layers and effectively lowers the relative dielectric constant. From the above, the ratio of the group V or group VI metal element to be solid-solved is 0.01 or more and less than 0.3 in terms of element ratio.

Group III gold constituting the gate insulating film of the present invention
As a genus, Al, Sc, Y and Ln (Ln: rare earth element
1) or more, and more preferably 1)
Especially. Al among group III element oxides_TwoO_Three,
Sc_TwoO_Three, Y_TwoO_ThreeAnd Ln _TwoO_ThreeOn the Si substrate
It is thermodynamically very stable. Therefore, the low dielectric constant Si
O_TwoGrowth can be suppressed and a sharp interface with Si can be formed.
And are possible.

The group V metal constituting the gate insulating film of the present invention is preferably one or more of Ta and Nb, more preferably one, and the group VI metal is preferably W. Ta ₂ O ₅ and Nb ₂ O ₅ which are oxides of each metal
The relative permittivities of WO ₃ and WO ₃ are about 25 to 50, 50 and 300, respectively, and the solid permittivity of these metal elements can improve the relative permittivity of the gate insulating film.

In the semiconductor device according to the present invention, the gate insulating film may be a layer composed of at least one of silicon oxide and silicon nitride, and A _1−x B _x O _y (x
= 0.01 to 0.3, y = 1.5 to 3.0, A is a group III metal, B is a group V metal and a group VI metal). Is characterized by.

That is, M using a silicon single crystal substrate as a base material
In the IS type transistor device, the gate insulating film is one or more of silicon oxide and silicon nitride, preferably 1 or more.
A layer composed of seeds, preferably A _1-x in which x is 0.01 or more and less than 0.3 and y is 1.5 or more and less than 3.0
It has a composition of B _x O _y, the A is a group III metal, and the B is a multi-layer, preferably a two-layer structure with a layer composed of a group V metal or a group VI metal. By arranging a layer made of silicon oxide or silicon nitride at the interface of the Si substrate, the barrier height of the electron conduction band can be increased and the leak current can be greatly reduced. It is also possible to reduce the interface state which deteriorates the characteristics of the MIS transistor.

Furthermore, the present invention is a method for manufacturing a semiconductor device in which a gate insulating film is formed on a silicon single crystal substrate, more specifically, a step of forming an element isolation insulating film on the silicon single crystal substrate, A step of forming a gate insulating film, a step of forming a gate electrode on the gate insulating film, and a source and drain region on both sides with the gate insulating film sandwiched between the element isolation insulating film and the gate insulating film. Forming a protective film for protecting the element isolation insulating film, the gate insulating film, the gate electrode, and the source and drain regions, and penetrating the protective film in contact with each of the source and drain regions. In the method for manufacturing a semiconductor device, which sequentially includes a step of forming a plug electrode and a step of forming a wiring on the protective film in contact with the plug electrode, the gate insulating film is A _{1- x B x O y (x =} 0.01~0.3,
y = 1.5 to 3.0, A is a group III metal, B is a composite oxide having a composition of at least one of a group V metal and a group VI metal), and is formed by a CVD method.

Further, according to the present invention, in the above-mentioned method for manufacturing a semiconductor device, a layer formed of at least one of silicon oxide and silicon nitride and the above-mentioned CVD method are used.
In which a multilayer of _{1- x} B _x O _y layer.

According to the present invention, Al ₂ O _{3 is} formed on the gate insulating film.
And a high dielectric constant gate that compensates for negative fixed charges generated by moisture absorption in the film when Ln ₂ O ₃ is used to suppress the shift of the flat band voltage and further satisfies the demand for further miniaturization. An insulating film can be obtained.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (Embodiment 1) FIG. 1 is a sectional view showing a method for manufacturing a MIS transistor according to the present invention.
The Si single crystal substrate 101 of FIG. 1A is p-type,
The substrate has a (100) plane orientation and a resistivity of 10 to 15 Ω · cm. The element isolation region 102 shown in FIG. 1B is formed by forming a groove having a depth of about 0.4 μm on a 101Si single crystal substrate and then performing CVD.
(Chemical Vapor Deposition
n) method, a SiO ₂ film is formed on the entire surface, and then CMP is performed.
(Chemical Mechanical Poli
It was prepared by flattening with a shin.

Next, an Al-Ta-O film to be the gate insulating film 103 was formed by the CVD method shown in FIG. Al (CH ₃ ) ₃ was used as the Al raw material. A Ta (OC ₂ H ₅ ) ₅ raw material was used as the Ta raw material. Each raw material was supplied to the substrate by a bubbling method using an argon carrier gas.
The argon carrier gas was transported at 50 sccm. O ₂ gas for decomposing the raw material was also supplied to the substrate at 50 sccm. The pressure of the reaction vessel was 0.1 torr and the substrate temperature was 500 ° C. Film formation time is 1 to 5 minutes and film thickness is 4
A complex oxide layer of ~ 20 nm was obtained.

ICPS (Inductively Co)
upd Plasma Spectrometer
y) When the elements of Al and Ta were examined by analysis,
The respective element ratios were 85%: 15%. Next, FIG.
The polycrystalline Si film to be the gate electrode 104 in FIG.
nm, and a gate electrode 104 shown in FIG. 1E is obtained.

Thereafter, phosphorus is added to the n-channel region and p
Boron is injected into the channel region to 800
Activated by heat treatment in a nitrogen atmosphere at a temperature of 10 to 30 minutes. As shown in FIG. 2F, the gate electrode 104 is formed by patterning a polycrystalline Si film using a normal photolithography method and etching by RIE by self-alignment, and similarly processing a 103 gate insulating film. did.
Next, by masking the 104 gate electrode, the atoms (P, As, Sb) of Group 5 of the periodic table are formed in the 105 source / drain regions.
Alternatively, Group 3 atoms (B, Al, Ga, In) are ion-implanted and subjected to heat treatment in Ar at 800 ° C. for 30 sec to form a low resistance diffusion region. Next, FIG.
The SiO ₂ protective film 106 was formed by the CVD method (g). Furthermore, after forming a through hole on the source / drain 105 of FIG. 2H, a W-plug electrode 107 was formed by the CVD method. Finally, the Al wiring 10 of FIG.
8 was manufactured on the W-plug 107 to manufacture a MIS type transistor element.

FIG. 3 is a line showing the result of calculating the EOT (SiO ₂ converted film thickness) from the CV characteristics when one of the Al wirings 108 is grounded and the gate electrode 104 is changed by −2 to 2V. It is a figure. The gradient obtained by the method of least squares between the film thicknesses of 4 to 20 nm means the dielectric constant and was about 15.
Further, when the physical film thickness is zero, the EOT is about 0.4 nm, and the formation of the SiO ₂ layer having a low dielectric constant at the interface between the gate insulating film 103 and the Si single crystal substrate 101 can be suppressed thin. In addition, in the CV characteristics, the shift of the flat band voltage was 0.02V.

As a comparative example, Al (C
H_Three)_ThreeSupply only to the substrate,_Two/ (Ar + O_Two)ratio
Under the same conditions,_TwoO_ThreeA film was formed. Substrate temperature, etc.
The conditions were also fixed to the same. Deposition time from 1
After 5 minutes, a film thickness of 3 to 15 nm was obtained. Similar C-V measurement
The result of calculating the EOT from the measurement is also shown in FIG. Al_Two
O _ThreeThe dielectric constant of the film was about 9. Also, C of 3 nm film
In the -V characteristic, the flat band voltage is 0.35V
Shift was recognized.

Thus, it was found that the solid permittivity of Ta ₂ O ₅ in Al ₂ O ₃ improves the relative dielectric constant from 9 to 15. Furthermore, it was found that the solid fixed solution of Ta ₂ O ₅ made it possible to compensate for the negative fixed charge generated in the Al ₂ O ₃ film because the flat band voltage shift was not observed.

Furthermore, it is possible to obtain a high-permittivity gate insulating film that suppresses the shift of the flat band voltage and satisfies the requirements for further miniaturization, and obtain a MIS transistor having a gate length of 0.1 μm or less. Do you get it.

In this embodiment, Al (CH
_Three)_Three, Ta as raw material Ta (OC _TwoH₅)₅Used
However, other raw materials may be used. In addition, as a raw material supply method
Bubbling method was used, but the liquid raw material is directly vaporized.
Any method may be used. Also, Al_TwoO_ThreeMaterial that dissolves in
Is not only Ta mentioned above but also V group such as Nb and W.
It has been confirmed that the same effect can be obtained with Group VI and Group VI elements.
It was

Polycrystalline Si is used as the gate electrode, but a metal that does not react with the dielectric material, such as W, Mo or T, is used.
iN, may be used TiSi ₂ or the like. Furthermore, polycrystalline S
The i may be doped with phosphorus. Al wiring was explained,
A low resistance metal material may be used, and for example, a Cu material may be used.

According to this embodiment, Al_TwoO_ThreeGroup V and group VI
By dissolving the elements in solid solution, Al _TwoO_ThreeOccurs in the membrane
The ability to compensate for negative fixed charges and improve the relative permittivity
I was able to confirm that

(Example 2) An Al-Ta-O film in which the elemental ratio of Ta was changed to 0 to 50% was prepared in the same manner as in Example 1. The elemental ratio of Ta was adjusted by the flow rate ratio of the CVD raw material. An Au upper electrode was formed on the obtained sample by a vacuum vapor deposition method, and the relative dielectric constant was determined by measuring the high frequency capacitance-voltage (CV) of the Au / Al-Ta-O / Si capacitor. In addition, by TEM analysis, SiO _{2 at} the Si interface
The film thickness was measured. The element ratio in the obtained film is IC
It was determined by PS analysis.

FIG. 4 is a diagram showing the dependence of the relative dielectric constant and the SiO ₂ film thickness at the Si interface on the element ratio in the film.
The relative permittivity was improved as the solid solution ratio of the Ta element was increased. However, the film thickness of SiO ₂ formed at the Si interface increased. Particularly, when the solid solution amount of Ta exceeds 30%, Si
The thickness of O ₂ tends to increase rapidly, and the thickness is 1
up to about nm, and the thermal stability on the Si interface of the formed gate insulating film deteriorates.

FIG. 5 is a diagram showing the shift value (ΔV _FB ) of the flat band voltage with respect to the solid solution amount of Ta. T
ΔV _FB asymptotically approached zero as the solid solution amount of a increased. Therefore, the negative fixed charge generated in the Al ₂ O ₃ film can be compensated by the solid solution amount of Ta.

According to the above embodiment, the solid solution amount of Ta in Al ₂ O _{3 is set} to 0.3 or less in terms of element ratio,
While maintaining the thermal stability of ₂ O ₃ , it is possible to compensate the negative fixed charges generated in the film and improve the relative dielectric constant, and obtain a MIS transistor having a gate length of 0.1 μm or less. It was confirmed.

Further, Al ₂ O ₃ and Ln ₂ O ₃ (Ln:
It was confirmed that the generation of fixed charges due to moisture absorption was suppressed in the gate insulating film using a rare earth element).

[0034]

As described above, according to the present invention, in a MIS type transistor device using a silicon single crystal substrate as a base material, a specific A _1-x B _x O _{y is used} as a gate insulating film.
(A is a group III metal, B is a group V metal, and group VI metal), the negative fixed charges generated in the film can be compensated, a high dielectric constant can be realized, and the gate length can be 0. .1
It was possible to provide a MIS transistor having a thickness of μm or less.

[Brief description of drawings]

FIG. 1 is a sectional view showing a manufacturing process of a MIS transistor element according to an embodiment of the present invention.

FIG. 2 is a sectional view showing a manufacturing process of the MIS transistor element according to the embodiment of the present invention.

FIG. 3 is a physical film thickness and EO of the Al—Ta—O film of the present invention.
The diagram which shows the relationship of T.

FIG. 4 shows Ta / in the Al—Ta—O film according to the present invention.
Relative permittivity to (Al + Ta) ratio and Si interface SiO ₂
The diagram which shows the relationship with a film thickness.

FIG. 5 shows Ta / in the Al—Ta—O film according to the present invention.
The figure which shows the relationship of the shift value of a flat band voltage with respect to (Al + Ta) ratio.

[Explanation of symbols]

101 ... Si single crystal substrate, 102 ... Element isolation region, 10
3 ... Gate insulating film, 104 ... Gate electrode, 105 ... Source / drain region, 106 ... SiO ₂ protective film, 107 ...
Plug electrode, 108 ... Al wiring.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Takaaki Suzuki             7-1-1, Omika-cho, Hitachi-shi, Ibaraki Prefecture             Inside the Hitachi Research Laboratory, Hitachi Ltd. (72) Inventor Yasuhiko Murata             7-1-1, Omika-cho, Hitachi-shi, Ibaraki Prefecture             Inside the Hitachi Research Laboratory, Hitachi Ltd. F-term (reference) 4K030 AA11 AA14 AA16 BA42 CA04                       FA10 LA15                 5F058 BA01 BA11 BC03 BD01 BD04                       BD05 BD10 BF04 BF27 BF29                       BJ01                 5F140 AA00 AA06 AA39 BA01 BD01                       BD05 BD07 BD13 BE10 BF01                       BF04 BF05 BF07 BF08 BF10                       BG38 BG43 BG44 BH21 BJ01                       BJ05 BJ07 BJ27 BK13 BK21                       BK25 BK30 BK38 CA03 CB04                       CC03 CC12 CE05

Claims (10)

[Claims] 1. In a semiconductor device having a gate insulating film on a silicon single crystal substrate, the gate insulating film is A
_{1-x B x O y (} x = 0.01~0.3, y = 1.5~
3.0, A is a group III metal, and B is a group V metal and a group VI metal). 2. A semiconductor device having a gate insulating film on a silicon single crystal substrate, wherein the gate insulating film comprises a layer made of at least one of silicon oxide and silicon nitride, and A
_{1-x B x O y (} x = 0.01~0.3, y = 1.5~
3.0, A is a group III metal, and B is a multilayer having a layer having a composition of one or more of a group V metal and a group VI metal). 3. The semiconductor device according to claim 1, wherein the gate insulating film has a length of 0.1 μm or less. 4. The semiconductor device according to claim 1, wherein an element isolation insulating film, a gate insulating film, and a gate electrode formed on the gate insulating film are formed on a silicon single crystal substrate. Source and drain regions formed on both sides of the gate insulating film between the element isolation insulating film and the gate insulating film, the element isolation insulating film, the gate insulating film, the gate electrode, and the source and drain region And a plug electrode formed in contact with each of the source and drain regions and penetrating the protective film, and a wiring formed on the protective film in contact with the plug electrode. A semiconductor device characterized by the above. 5. The method according to claim 1, wherein the II
Group I metal is Al, Sc, Y, Ln (Ln: rare earth element)
1. A semiconductor device comprising one or more of 6. The V according to any one of claims 1 to 5.
A semiconductor device, wherein the group metal is at least one of Ta and Nb. 7. The VI according to any one of claims 1 to 6.
A semiconductor device, wherein the group metal is W. 8. A method of manufacturing a semiconductor device, wherein a gate insulating film is formed on a silicon single crystal substrate, wherein the gate insulating film is A _1-x B _x O _y (x = 0.01 to 0.3, y = 1.
5 to 3.0, A is a group III metal, B is a composite oxide having a composition of at least one of a group V metal and a group VI metal), and the composite oxide is formed by a CVD method. Method for manufacturing semiconductor device. 9. A method of manufacturing a semiconductor device, comprising a step of forming a gate insulating film on a silicon single crystal substrate, wherein the gate insulating film comprises a layer made of at least one of silicon oxide and silicon nitride, and A _1-x. B _x O _{y (x} = 0.01~
0.3, y = 1.5 to 3.0, A is a group III metal, B is V
A method for manufacturing a semiconductor device, comprising a multi-layer including a complex oxide layer having a composition of one or more of group metals and group VI metals), the complex oxide layer being formed by a CVD method. 10. The method according to claim 8, wherein before the step of forming the gate insulating film, a step of forming an element isolation insulating film on the silicon single crystal substrate, and the gate insulating film are formed. After the step, a step of forming a gate electrode on the gate insulating film, and a step of forming source and drain regions on both sides with the gate insulating film sandwiched between the element isolation insulating film and the gate insulating film. Forming a protective film that protects the element isolation insulating film, the gate insulating film, the gate electrode, and the source and drain regions; and forming a plug electrode by contacting each of the source and drain regions and penetrating the protective film. A method of manufacturing a semiconductor device, comprising: a forming step and a step of forming a wiring on the protective film in contact with the plug electrode.