JP2003017661A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the crosstalk between capacitors and to reduce the area and interval of array while keeping the reliability in memory operation of each capacitor. SOLUTION: A semiconductor device comprises capacitors 43A-43D on a silicon oxide film 23. The capacitors 43A-43D comprise a node electrode 3A provided on the silicon oxide film 23, a silicon oxide film 29 selectively provided on the node electrode 3A for forming a capacitor region, an SBT film 31 provided at least on the node electrode 3A between the silicon oxide films 29, and plate electrodes 5A-5D so provided on the SBT film 31 as to cross the node electrode 3A. Thus, such capacitor is provided as no SBT film 31 is present between the node electrode 3A and the silicon oxide film 29 except for the capacitor region while the SBT film 31 is held in such part as the node electrode 3A crosses the plate electrodes 5A-5D.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device which is suitable for being applied to an IC memory which is mounted on electronic equipment such as a personal computer and which performs high-speed read / write operation, and a manufacturing method thereof. More specifically, a ferroelectric film is provided between the insulating members for defining the capacitor region selectively provided on the first wiring member, and the ferroelectric film is provided so as to intersect with the first wiring member. By providing the second wiring member on the upper side, the interaction between the capacitors can be prevented.

[0002]

2. Description of the Related Art In recent years, the performance of electronic devices such as personal computers has been increasing at an accelerating pace, and along with this, demands for further miniaturization and higher performance of semiconductor devices mounted on personal computers have increased day by day. It's starting. Under such circumstances, a ferroelectric (Dynamic Random
FRAM (Ferro electric Random Access Memory), which has a higher memory function than Access Memory), is becoming widespread.

FIG. 9 is a sectional view showing a structural example of a semiconductor device 90 according to a conventional method. This semiconductor device 90 is an FRA
M, the semiconductor substrate 81 and the field oxide film 82.
, A gate oxide film (not shown), a word line 83, a source diffusion layer 84, a drain diffusion layer 85, and a bit line 86.
For connecting the bit line 86 and the source diffusion layer 84 to each other.
Plug electrode 87, an insulating film 88 for protecting the word line 83, the bit line 86, etc., and a second plug electrode 89 provided so as to reach the upper surface of the insulating film 88 from above the drain diffusion layer 85. There is.

The semiconductor device 90 is provided with a plurality of capacitors 96A to 96D on the insulating film 88 so as to be connected to the plug electrode 89. These capacitors 96
A to 96D are the node electrode 91 provided on the insulating film 88 including the plug electrode 89, the ferroelectric SBT film 92 provided on the node electrode 91, and the SBT film 92.
The insulating member 93 for selectively defining the capacitor region and the node electrode 91 are provided so as to intersect with the SB.
Plate electrodes 94A to 94D provided on the T film 92 are provided. In the semiconductor device 90, an arbitrary capacitor is selected from the plurality of capacitors 96A to 96D and accessed.

[0005]

By the way, according to the conventional semiconductor device 90, when the semiconductor device 90 is reduced in size, the area of the capacitor will eventually become smaller than the domain (small crystal grain size) of the SBT film 92. As a result, the capacitors become smaller and adjacent capacitors share one domain.

In such a state, for example, the capacitor 9
When the signal charge is stored in 6B, the adjacent capacitor 96
An electric charge may be induced in C through the SBT film 92 on the node electrode, and an interaction (hereinafter, also referred to as crosstalk) may occur between the capacitors 96B and 96C. Therefore, the size of the capacitors 96A to 96D is
The size of the domain of the SBT film 92 cannot be reduced to a size equal to or smaller than the domain size, which hinders miniaturization of the semiconductor device 90.

Therefore, the present invention solves such a problem by making it possible to prevent crosstalk between capacitors and to maintain the reliability of the memory operation of each capacitor while maintaining its area and An object of the present invention is to provide a semiconductor device capable of further reducing the arrangement interval and a manufacturing method thereof.

[0008]

SUMMARY OF THE INVENTION The above-described problems are, in a semiconductor device having a plurality of capacitors on a predetermined base member, the capacitors being provided on the base member.
Wiring member, an insulating member for defining a capacitor region selectively provided on the first wiring member, and a ferroelectric film provided on the first wiring member at least between the insulating members. And a second wiring member provided on the ferroelectric film so as to intersect with the first wiring member.

According to the semiconductor device of the present invention, the ferroelectric film does not exist between the insulating member other than the capacitor region and the first wiring member, and the first wiring member and the second wiring member are provided. It is possible to provide a capacitor in which a ferroelectric film is sandwiched at a portion where members cross each other.

A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device having a plurality of capacitors on a predetermined base member, and a step of forming a first wiring member on the base member. A step of selectively forming an insulating member for defining a capacitor region on the first wiring member, and a step of forming a ferroelectric film at least on the first wiring member between the insulating members. And a step of forming a second wiring member on the ferroelectric film so as to intersect with the first wiring member having the ferroelectric film formed thereon. is there.

According to the method of manufacturing a semiconductor device of the present invention, the ferroelectric film does not exist between the insulating member other than the capacitor region and the first wiring member, and the first wiring member and the first wiring member are not formed. A capacitor having a ferroelectric film sandwiched at the intersection of two wiring members can be manufactured with good reproducibility.

Therefore, when the first wiring member is commonly used and a plurality of capacitors are selectively operated, the ferroelectric film can be formed on the first wiring member at a predetermined interval, so that the first wiring member can be formed. Crosstalk between adjacent capacitors can be prevented as compared with the case where a ferroelectric film is continuously formed on a wiring member.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device and a method of manufacturing the same according to embodiments of the present invention will be described below with reference to the drawings. In this embodiment, a ferroelectric film is provided between the insulating members for defining the capacitor region, which are selectively provided on the first wiring member, and the ferroelectric film is provided so as to intersect with the first wiring member. By having a capacitor formed of the second wiring member provided on the film, the crosstalk between the capacitors can be prevented, and the area of the capacitor can be reduced while maintaining the reliability of the memory operation of each capacitor. The arrangement interval can be further reduced.

FIG. 1 is a plan view showing a configuration example of a semiconductor device 100 according to an embodiment of the present invention. This semiconductor device 1
00 is a ferroelectric film provided between the plurality of node electrodes 3A and 3B, which is an example of the first wiring member, and the plurality of plate electrodes 5A to 5D, which is an example of the second wiring member. , A ferroelectric memory (FRAM) configured to include a plurality of capacitors.

FIG. 2 is a sectional view taken along the line X1-X2 showing an example of the structure of the semiconductor device 100 shown in FIG. First, the semiconductor device 100 has a semiconductor substrate 1. The semiconductor substrate 1 is, for example, a p-type silicon wafer doped with a slight amount of boron. A field oxide film 7 for element isolation is provided in a predetermined region of the semiconductor substrate 1. This field oxide film 7 is LOCOS (Lo
It is formed by the cal oxidization of silicon) method and has a thickness of about 600 nm.

An n-type source diffusion layer 9 and a drain diffusion layer 11 are provided on the surface of the semiconductor substrate 1 and in the vicinity thereof, in a region surrounded by the field oxide film 7. These source diffusion layer 9 and drain diffusion layer 1
The junction depth of 1 is, for example, about 250 nm. Also,
The width of the channel region between the source diffusion layer 9 and the drain diffusion layer 11 is about 1 μm. A gate oxide film (not shown) is provided on this channel region. This gate oxide film is provided by thermally oxidizing the semiconductor substrate 1 made of silicon and has a thickness of about 15 nm.

A word line 15A is provided on the gate oxide film. The word line 15A inverts the surface of the channel region and its vicinity from p-type to n-type to electrically connect the source diffusion layer 9 and the drain diffusion layer 11. Hereinafter, the word line, the gate oxide film, the source diffusion layer and the drain diffusion layer are collectively referred to as a transistor. The word line 15A is, for example,
It has a structure in which tungsten silicide (WSi ₂ ) is laminated on polysilicon doped with phosphorus. Word line 1
The line width of 5A is about 0.5 μm, and its thickness is about 0.2.
It is about μm.

Further, a first plug electrode 19 made of phosphorus-doped polysilicon is provided on the source diffusion layer 9, and a bit line 21 is provided on the plug electrode 19.
Is provided. The bit line 21 is a wiring for inputting / outputting signal charges to / from the capacitor. The bit line 21 is made of aluminum or the like and has a line width of about 0.5 μm and a thickness of about 0.2 μm.

A silicon oxide film 23, which is an example of a predetermined base member, is provided on the semiconductor substrate 1 so as to cover the word lines 15A, the bit lines 21, etc. described above. The silicon oxide film 23 has a thickness of about 1200 nm. Further, an opening is provided on the drain diffusion layer 11 of the silicon oxide film 23, and the second plug electrode 25 is provided in the opening. The plug electrode 25 is made of phosphorus-doped polysilicon,
The upper surface of the drain diffusion layer 11 is formed to reach the upper surface of the silicon oxide film 23.

In FIG. 2, a node electrode 3A is provided on the silicon oxide film 23. This node electrode 3A
Are configured to be connected to the plug electrode 25. The node electrode 3A is, for example, CoS from the plug electrode 25 side.
It has a laminated structure of i / TiN / Ir. The thickness of the node electrode 3A is 30 nm / 50 nm / 100 n, respectively.
The line width is about 0.13 μm.

Further, a silicon oxide film 29, which is an example of an insulating member for defining a capacitor region, is provided on the node electrode 3A. The silicon oxide film 29 is provided with a plurality of openings at regular intervals, so that the node electrode 3A is exposed from the silicon oxide film 29. The region exposed from the silicon oxide film 29 is the capacitor region.

The silicon oxide film 29 has, for example, 20
It has a thickness of about 0 nm. Further, the size of the opening provided in the silicon oxide film 29 is 0.13 μm × length.
The width is about 0.13 μm and the depth is about 200 nm. Such an opening is formed in the silicon oxide film 29 by about 0.13 μm.
A plurality of grids are provided at intervals of m.

The node electrode 3A defined on the silicon oxide film 29 and by the opening of the silicon oxide film 29.
An SBT film 31, which is an example of a ferroelectric film, is provided on the top. The SBT film 31 is formed of Sr _x Bi _y (Ta, N
b) a ferroelectric material having a composition of ₂ O _{9 + z} , the composition ratio of which is 0.6 ≦ x ≦ 1.2, 1.7 ≦ y ≦ 2.5, 0
It is set within the range of ≦ z ≦ 1.

This SBT film 31 is the semiconductor device 10 concerned.
0 is a ferroelectric substance of a plurality of capacitors, and the thinner the film thickness and the larger the dielectric polarization value, the larger the capacitance of the capacitor can be. The SBT film 31 has a thickness of, for example, about 100 nm. The dielectric polarization value is about several hundreds although it depends on the above composition ratio.

A plurality of plate electrodes 5A to 5D, which are second wiring members, are provided on the SBT film 31 provided in the opening of the silicon oxide 29. These plate electrodes 5A to 5D are arranged so as to intersect the node electrode 3A in the capacitor region, and as shown in FIG. 1, the plate electrodes 5A to 5D are substantially parallel to each other in the same plane. It is arranged. Plate electrode 5
A to 5D are made of, for example, Ir and have a thickness of 100 n.
It is about m.

The node electrode 3A and the SBT film 31
The plate electrodes 5A to 5D form capacitors 43A to 43D as shown in FIG. Compared to the conventional method, between the capacitors 43A to 43D,
The node electrode 3A and the SBT film 31 are isolated by the silicon oxide film 29. That is, the capacitors 43A to 43A
In regions other than D, the node electrode 3A and the SBT film 31 are separated by the insulating silicon oxide film 29.

Although the capacitors 43A to 43D provided on the node electrode 3A have been described with reference to FIG. 2, a capacitor having the same structure is provided on the node electrode 3B shown in FIG. There is.

FIG. 3 shows an FRA to which the semiconductor device 100 is applied.
It is a circuit diagram which shows the structural example of M. In FIG. 3, the node electrode 3A is provided with capacitors 43A to 43D, and the node electrode 3B is provided with capacitors 43E to 43H. These node electrodes 3A and 3B are connected to the sense amplifier 53 having a signal amplifying function via the transistors 51A and 51B, respectively.

The word lines 15A and 15B are connected to the word line decoder 55.
The word line decoder 55 has a function of selectively turning on / off the transistors 51A and 51B via the word lines 15A and 15B and selecting the plate electrodes 3A and 3B. Further, the plate electrodes 5A to
5D is connected to the plate line decoder 57. The plate line decoder 57 has a function of selecting the plate electrodes 5A to 5D.

Since the semiconductor device 100 has such a circuit configuration, each capacitor 43A is formed by a matrix of the node electrodes 3A and 3B and the plate electrodes 5A to 5D.
.About.43H can be arbitrarily selected and accessed. Then, the plate electrode 3 other than the capacitor region
The SBT film 31 is not provided on A and 3B.

Therefore, for example, the word line decoder 55 selects the word line 15A and the plate line decoder 57 selects the plate electrode 43B.
Even when the capacitor 43B is accessed, crosstalk between the capacitors 43A and 43B and between the capacitors 43B and 43C can be prevented.

Thus, the semiconductor device 10 according to the present invention
According to 0, the SBT film 31 is provided between the silicon oxide films 29 for defining the capacitor regions, which are selectively provided on the node electrodes 3A and 3B, and the SBT film 31 is formed so as to intersect with the node electrodes 3A and 3B. It has a capacitor composed of the plate electrodes 5A to 5D provided above.

Therefore, the SBT is provided between the silicon oxide film 29 other than the capacitor region and the node electrodes 3A and 3B.
It is possible to provide capacitors 43A to 43H in which the SBT film 31 is sandwiched at the intersections of the node electrodes 3A and 3B and the plate electrodes 5A to 5D without the film 31.

As a result, when the node electrodes are shared and the plurality of capacitors are selectively operated, the node electrodes 3A
Since the SBT film 31 can be selectively provided in the capacitor region on and 3B, crosstalk between capacitors via the SBT film 31 can be prevented. Therefore, as compared with the conventional method, while maintaining the reliability of the memory operation of each of the capacitors 43A to 43H, the area and the arrangement interval can be further reduced, and the number of capacitors of the semiconductor device can be surely increased.

Although the semiconductor device 100 exemplifies the two node electrodes 3A and 3B as the first wiring member and the five plate electrodes 5A to 5D as the second wiring member, the present invention is not limited to this. However, the number of electrodes can be freely set as required.

FIG. 4 is a sectional view showing a structural example of the semiconductor device 200 according to the embodiment of the present invention. This semiconductor device 2
00 is an application of the semiconductor device 100 described above, in which an insulating film is provided above the capacitors 43A to 43H described above, and a plurality of capacitors are further stacked on the insulating film. Therefore, those having the same reference numeral have the same function, and the description thereof will be omitted.

In FIG. 4, the semiconductor device 200 has another drain diffusion layer 61 in a predetermined region of the semiconductor substrate 1. The drain diffusion layer 61 has the same structure as the n-type drain diffusion layer 11 described above. A gate oxide film (not shown) is provided on the channel region between the drain diffusion layer 61 and the source diffusion layer 9. Further, another word line 6 is formed on the gate oxide film.
5A is provided. This word line 65A also has the same structure as the above-mentioned word line 15A.

Further, the semiconductor device 200 includes the capacitor 4
An interlayer insulating film 35, which is an example of an insulating film, is provided so as to cover 3A to 43H (43E to 43H are not shown). The interlayer insulating film 35 is made of silicon oxide and has a thickness of about 1200 nm. The interlayer insulating film 35 is formed by CMP (Chemical Mechanical Poli).
The upper surface is made flat by sh) etc.

A third layer is formed on the interlayer insulating film 35.
The node electrode 37A, which is an example of the wiring member, is provided. The node electrode 37A has the same structure as the node electrode 3A which is an example of the first wiring member. For example, the node electrode 37A is formed of CoSi from the side of the interlayer insulating film 35.
It has a laminated structure of / TiN / Ir. A plurality of node electrodes 37A are provided on the interlayer insulating film 35 and are arranged substantially in parallel with other node electrodes (not shown) in the same plane.

The node electrode 37A is the interlayer insulating film 35.
The drain diffusion layer 61 below is connected. As a result, when a predetermined voltage is applied to the word line 65A, the channel region between the source diffusion layer 9 and the drain diffusion layer 61 is inverted, and the bit line 21 and the node electrode 37A.
Are configured to be electrically connected.

A silicon oxide film 39, which is an example of another insulating member for defining the capacitor region, is provided on the node electrode 37A. This silicon oxide film 39 is
It has the same structure as the silicon oxide film 29 described above. For example, the silicon oxide film 39 has a thickness of 0.13 μm.
A plurality of openings are provided at intervals of, and the size of the openings is about 0.13 μm in length × 0.13 μm in width.
As a result, a capacitor region having an area of vertical 0.13 μm × horizontal 0.13 is formed on the node electrode 37A by 0.13 μm.
A plurality of m intervals are defined.

Further, an SBT film 41, which is an example of another ferroelectric film, is provided in the capacitor region on the node electrode 37A defined by the silicon oxide film 39. The SBT film 41 also has the same structure as the SBT film 31 described above. For example, this SBT film 41
Is a ferroelectric material having a composition of Sr _x Bi _y (Ta, Nb) ₂ O _{9 + z} , the composition ratio of which is 0.6 ≦ x ≦ 1.
2, 1.7 ≦ y ≦ 2.5, 0 ≦ z ≦ 1.

Plate electrodes 45A to 45D, which are an example of a fourth wiring member, are provided on the SBT film 41 provided in the opening of the silicon oxide film 39.
These plate electrodes 45A to 45D have the same configuration as the plate electrodes 5A to 5D. For example, the plate electrodes 45A to 45D are arranged so as to intersect the plurality of node electrodes 37A in the capacitor region, and each plate electrode 45A to 45D is arranged substantially parallel to the other plate electrodes in the same plane. There is. These plate electrodes 45A to 45D are made of, for example, Ir and have a thickness of 1
It is about 00 nm.

Thus, the semiconductor device 200 according to the present invention
According to the above, the interlayer insulating film 35 is provided on the above-mentioned capacitors 43A to 43H, and the capacitor 6 having the same configuration as the capacitors 43A to 43H is formed on the interlayer insulating film 35.
7A to 67D are further provided. Therefore,
Mutual interference between the capacitors 67A to 67D can be prevented,
A stable memory operation can be obtained. Moreover, since a plurality of capacitors can be stacked in the upward direction, the memory capacity of the semiconductor device can be reliably increased.

Incidentally, the semiconductor device 100 and the semiconductor device 20.
In No. 0, the SBT film is illustrated as an example of the ferroelectric film, but the ferroelectric film is not limited to this. For example, Pb (Zr,
Ti) O ₃ and the composition ratio is 0.1 ≦ Zr /
A composite oxide film in the range of Pb ≦ 0.6 and 0.4 ≦ Ti / Pb ≦ 0.9 may be used. Alternatively, (Bi, La) ₄ T
A composite oxide film having a composition of i ₃ O ₁₂ and having a composition ratio within the range of 0 ≦ La ≦ 1 may be used.

Further, in the semiconductor device 200, one node electrode 37A is illustrated as the third wiring member and five plate electrodes 45A to 45D are illustrated as the fourth wiring member, but the present invention is not limited to this. The number of electrodes can be freely set as needed.

Next, a method of manufacturing the semiconductor device according to the present invention will be described. Here, it is assumed that the semiconductor device 100 shown in FIGS. 1 and 2 is manufactured. 5 to 8
FIG. 6A is a process diagram showing the manufacturing method (parts 1 to 4) of the semiconductor device 100. First, as shown in FIG. 5A, a field oxide film 7 and a gate oxide film (not shown) are formed on a semiconductor substrate 1, and a word line 15A is formed on this gate oxide film. Next, an impurity such as As is ion-implanted into a predetermined region of the semiconductor substrate 1 to form the source diffusion layer 9 and the drain diffusion layer 1.
1 is formed.

Then, a silicon oxide film of about 700 nm is formed on the semiconductor substrate 1 so as to cover the word lines 15A and the field oxide film 7. Further, a contact hole is formed on the source diffusion layer 9, and polysilicon doped with an impurity such as phosphorus is deposited so as to fill the contact hole. The deposited polysilicon is processed into a predetermined shape to form the first plug electrode 19 on the source diffusion layer 9.

After forming the plug electrode 19, the bit line 21 is formed on the plug electrode. Then, a silicon oxide film is further deposited to a thickness of about 500 nm above the semiconductor substrate 1 so as to cover the bit line 21, and the silicon oxide film 23 shown in FIG. 5A is formed. After that, a contact hole is formed on the drain diffusion layer 11 and polysilicon doped with an impurity such as phosphorus is deposited so as to fill the contact hole. This polysilicon is processed into a predetermined shape to form the second plug electrode 25.
Up to this point, the process is the same as the normal CMOS process flow.

Next, C is formed on the silicon oxide film 23 so as to be connected to the plug electrode 25 on the drain diffusion layer 11.
oSi is formed to a thickness of about 30 nm. And this CoSi
TiN is formed to a thickness of about 50 nm, and Ir is formed on this TiN.
Of about 100 nm is formed. As a result, as shown in FIG. 5B, a node electrode film (hereinafter referred to as a node electrode film) 69 made of CoSi / TiN / Ir can be formed. In the step of forming the node electrode film 69, for example, C
A VD device is used. This node electrode film 69 has Pt
Etc. may be used. Other materials can be selected, provided that oxygen is not taken from the ferroelectric film and the stoichiometry (stoichiometry) thereof is not broken.

Next, as shown in FIG. 6A, a first resist pattern 70 having a predetermined shape is formed on the node electrode film 69 by photolithography. Then, using the resist pattern 70 as a mask, the node electrode film 69 is subjected to dry etching such as RIE (reactive ion etching). As a result, a node electrode having a predetermined shape can be formed. The line width of this node electrode is
For example, it is about 0.13 μm.

After forming the node electrode by dry etching, a silicon oxide film for defining the capacitor region is deposited to a thickness of 300 nm on the node electrode and the silicon oxide film 23. The deposition of this silicon oxide film is performed using, for example, a CVD device. The insulating member for defining the capacitor region is not limited to silicon oxide (SiO ₂ ), but may be Al ₂ O ₃ , CeO ₂ , TiO ₂ , ZrO ₂ , Ta ₂ O.
₅ , Y ₂ O ₃ or the like may be used.

After depositing the silicon oxide film, the surface of the silicon oxide film is polished and flattened to form a silicon oxide film 29 shown in FIG. 6B. As a result, a plurality of openings having a substantially constant size can be formed in the silicon oxide film 29 in a later step, and the area of the capacitor region can be made more uniform. In this flattening step, for example, CMP
To use. The film thickness of the flattened silicon oxide film 29 is, for example, about 200 nm.

After forming the silicon oxide film 29, FIG.
As shown in, a second resist pattern 71 having a predetermined shape is formed on the silicon oxide film 29. The resist pattern 71 is formed so as to expose the silicon oxide film 29 on the capacitor region.

Then, using the resist pattern 71 as a mask, the silicon oxide film 29 is subjected to dry etching such as RIE. Thereby, a plurality of openings can be formed in the silicon oxide film 29. The surface of the node electrode 3A is exposed on the bottom surface of this opening, and this exposed portion becomes a capacitor region. The opening has a length of 0.13 μm, for example.
B has a width of about 0.13 μm, and a plurality of them are provided at intervals of 0.13 μm.

Next, as shown in FIG. 7B, about 100 nm of SBT film 31 is deposited on the silicon oxide film 29 and on the openings 72 to 72D formed in the silicon oxide film 29, and processed into a predetermined shape. To do. The deposition of the SBT31 film is performed by MOCVD (metal organic chemical vapor deposition). The SBT film 31 is a ferroelectric material having a composition of Sr _x Bi _y (Ta, Nb) ₂ O _{9 + z} , and its composition ratio is 0.
It is desirable to set within the ranges of 6 ≦ x ≦ 1.2, 1.7 ≦ y ≦ 2.5, and 0 ≦ z ≦ 1.

On the silicon oxide film 29 and the openings 72A ...
After the SBT film 31 is formed on 72D, the SBT film 31 is formed.
Annealing is performed at about 700 ° C. for 1 hour in an oxygen atmosphere. By this annealing treatment, the composition ratio in the SBT film 31 can be made uniform and its domain (small crystal grain size) can be increased.

Thereafter, as shown in FIG. 8, a plate electrode film (hereinafter referred to as a plate electrode film) 73 is formed on the SBT film 31 so as to fill the openings 72A to 72D which define the capacitor region. It is formed on the SBT film 31. The material of the plate electrode film 73 is Ir, for example, and the film thickness thereof is about 100 nm. The material of the plate electrode film 73 is not limited to Ir, and Pt or the like may be used, for example. Other materials can be freely selected, provided that oxygen is not taken from the SBT film 31 and the stoichiometry thereof is not broken.

Next, a third resist pattern 74 having a predetermined shape is formed on the plate electrode film 73.
The resist pattern 74 is formed in the opening so as to intersect the node electrode 3A.
It is shaped so as to cover 3. Then, using the resist pattern 74 as a mask, the plate electrode film 73 is formed.
When dry etching such as RIE is performed, a plate electrode that intersects the node electrode 3A in the capacitor region and sandwiches the node electrode 3A and the SBT film 31 in this capacitor region can be formed.

As a result, the SBT film 31 is provided between the silicon oxide film 29 and the node electrode 3A other than the capacitor region.
Is not present, a plurality of capacitors can be formed with the SBT film 31 sandwiched between the node electrodes 3A and the plate electrodes. After forming the plate electrode, an interlayer insulating film for protecting the capacitor is formed on the plate electrode. The interlayer insulating film is made of, for example, silicon oxide and has a thickness of about 600 nm. Next, a contact hole is formed on the plate electrode. Then, a conductive film such as Al is formed on the interlayer insulating film so as to fill this contact hole, and this conductive film is processed into a wiring pattern shape by dry etching such as RIE. This allows
The semiconductor device 100 shown in FIGS. 1 and 2 is completed.

The interlayer insulating film 3 shown in FIG. 1 is formed by the method described above.
By further forming a capacitor on the semiconductor device 5, the semiconductor device 200 shown in FIG. 4 can be completed. That is, the interlayer insulating film 3
5, another node electrode 37A composed of three layers of CoSi / TiN / Ir is formed, a silicon oxide film 39 for defining a capacitor is formed on this node electrode 37A, and a capacitor region is formed on this silicon oxide film 39. By forming an opening for demarcation, forming another SBT film 41 at least in this opening, and forming another plate electrode 45 made of Ir on this SBT film 41, two layers are laminated in the upward direction. The semiconductor device 200 having a capacitor can be formed. Furthermore, by repeating this method a plurality of times, it is possible to manufacture a semiconductor device having capacitors stacked in many layers.

As described above, according to the semiconductor device manufacturing method of the present invention, the openings 72A to 72A of the silicon oxide film 29 for defining the capacitor region, which are formed on the node electrode 3A, are formed.
A ferroelectric SBT film 31 is formed on 72D, and plate electrodes 5A to 5D are formed on the SBT film 31 so as to intersect with the node electrode 3A to form a capacitor. Therefore, the SBT film 31 is provided between the silicon oxide film 29 and the node electrode 3A other than the capacitor region.
Not present, the node electrode 3A and the plate electrodes 5A to 5D
Capacitors having the SBT film 31 sandwiched at the intersections of can be manufactured with good reproducibility.

Thus, when the node electrode 3A is shared and a plurality of capacitors are selectively operated, the SBT films 31 can be formed on the node electrode 3A with a predetermined interval, so that the SBT film 31 is continuously formed on the node electrode 3A. Crosstalk between capacitors via the SBT film 31 can be prevented as compared with the case where the film 31 is formed. Therefore, these capacitors can be further miniaturized without being restricted by the size of the ferroelectric domain.

In this embodiment, the silicon oxide film 29 for defining the capacitor region and this silicon oxide film 2 are formed.
Although the case where the SBT film 31 is deposited in the openings 72 to 72D provided in No. 9 has been described, the SBT film 31 on the silicon oxide film 29 may be removed. This allows
A semiconductor device having the SBT film 31 only in the capacitor region can be manufactured, and crosstalk between capacitors via the SBT film 31 can be further prevented.

[0065]

According to the semiconductor device of the present invention, the first
A ferroelectric film is provided between the insulating members for demarcating the capacitor region, which are selectively provided on the wiring member, and is provided on the ferroelectric film so as to intersect the first wiring member. And a capacitor formed of a second wiring member. With this configuration, there is no ferroelectric film between the insulating member other than the capacitor region and the first wiring member,
It is possible to provide a capacitor in which a ferroelectric film is sandwiched at the intersection of the first wiring member and the second wiring member.

Therefore, when the first wiring member is commonly used and a plurality of capacitors are selectively operated, the first wiring member is provided with the ferroelectric film at a predetermined interval, and thus the first wiring member is provided. Crosstalk between adjacent capacitors can be prevented as compared with a case where a ferroelectric film is continuously provided on a wiring member. As a result, the area and arrangement interval of the capacitors can be further reduced while the reliability of the memory operation of each capacitor is maintained, and the capacitance of the capacitors of the semiconductor device can be reliably increased.

Further, according to the method of manufacturing a semiconductor device of the present invention, a ferroelectric film is formed between the insulating members for defining the capacitor region, which are selectively formed on the first wiring member, A second wiring member is formed on the ferroelectric film so as to intersect with the first wiring member to form a capacitor. With this configuration, there is no ferroelectric film between the insulating member other than the capacitor region and the first wiring member, and the ferroelectric film is present at the intersection of the first wiring member and the second wiring member. Capacitors sandwiching the film can be manufactured with good reproducibility.

Therefore, when the first wiring member is commonly used and a plurality of capacitors are selectively operated, the ferroelectric film can be formed on the first wiring member at a predetermined interval, and thus the first wiring member can be formed. Crosstalk between adjacent capacitors can be prevented as compared with the case where a ferroelectric film is continuously formed on a wiring member. As a result, the area of each capacitor and the arrangement interval of the capacitors can be reduced while maintaining the reliability of the memory operation, and the manufacturing cost of the semiconductor device can be reduced.

The present invention is extremely suitable when applied to an electronic device such as a personal computer or the like, which is applied to an IC memory or the like for performing high-speed read / write operation.

[Brief description of drawings]

FIG. 1 is a plan view showing a configuration example of a semiconductor device 100 according to the present invention.

2 is a cross-sectional view taken along arrow X1-X2 showing a configuration example of the semiconductor device 100 shown in FIG.

FIG. 3 is a circuit diagram showing a configuration example of an FRAM to which the semiconductor device 100 is applied.

FIG. 4 is a sectional view showing a configuration example of a semiconductor device 200 according to the present invention.

5A and 5B are process diagrams showing a manufacturing method (1) of the semiconductor device 100.

6A and 6B are process diagrams showing a manufacturing method (2) of the semiconductor device 100.

7A and 7B are process diagrams showing a manufacturing method (3) of the semiconductor device 100.

FIG. 8 is a process chart showing the manufacturing method (4) of the semiconductor device 100.

FIG. 9 is a cross-sectional view showing a configuration example of a semiconductor device 90 according to a conventional example.

[Explanation of symbols]

1 ... Semiconductor substrate, 3A, 3B ... Node electrode, 5
A to 5D ... Plate electrode, 15A, 15B ... Word line, 21 ... Bit line, 29 ... Silicon oxide film, 31 ... SBT film, 43A-43H ... Capacitor, 100, 200 ... Semiconductor device

Claims (9)

[Claims] 1. A semiconductor device comprising a plurality of capacitors on a predetermined base member, wherein the capacitors are provided on the base member and selectively on the first wiring member. An insulating member for demarcating the capacitor region provided in, a ferroelectric film provided on at least the first wiring member between the insulating members, and so as to intersect with the first wiring member, A semiconductor device, comprising: a second wiring member provided on the ferroelectric film. 2. The semiconductor device according to claim 1, wherein the ferroelectric film is provided on the first wiring member between the insulating members and on the insulating member. 3. An insulating film provided on at least the second wiring member and the insulating member for defining a capacitor, a third wiring member provided on the insulating film, Another insulating member for selectively defining a capacitor region, which is selectively provided on the third wiring member, and another ferroelectric film provided on the third wiring member at least between the other insulating members. 2. The semiconductor device according to claim 1, further comprising: a fourth wiring member provided on the other ferroelectric film so as to intersect with the third wiring member. . 4. The ferroelectric film has a composition of Sr _x Bi _y (Ta, Nb) ₂ O _{9 + z} , and the composition ratio thereof is 0.6 ≦ x ≦ 1.2 1.7. The semiconductor device according to claim 1, wherein the semiconductor device is set within a range of ≦ y ≦ 2.5 0 ≦ z ≦ 1. 5. The ferroelectric film has a composition of Pb (Zr, Ti) O ₃ , and its composition ratio is 0.1 ≦ Zr / Pb ≦ 0.6 0.4 ≦ Ti / Pb The semiconductor device according to claim 1, wherein the semiconductor device is set within a range of ≦ 0.9. 6. The ferroelectric film has a structure of (Bi, La) ₄ Ti ₃ O ₁₂ , and its composition ratio is set within a range of 0 ≦ La ≦ 1. The semiconductor device according to claim 1. 7. A method of manufacturing a semiconductor device having a plurality of capacitors on a predetermined underlying member, the method comprising: forming a first wiring member on the underlying member; and forming a capacitor on the first wiring member. A step of selectively forming an insulating member for defining a region; a step of forming a ferroelectric film on at least the first wiring member between the insulating members; and a step of forming the ferroelectric film. And a step of forming a second wiring member on the ferroelectric film so as to intersect with the first wiring member. 8. A first step of forming a first wiring member on the base member, and a second step of selectively forming an insulating member for defining a capacitor region on the first wiring member. A third step of forming a ferroelectric film on at least the first wiring member between the insulating members, and crossing the first wiring member on which the ferroelectric film is formed. And a fourth step of forming a second wiring member on the ferroelectric film, and a fifth step of forming an insulating film on the second wiring member. 8. The method of manufacturing a semiconductor device according to claim 7, wherein the steps from step 5 to step 5 are repeated a predetermined number of times to stack the capacitors. 9. An insulating film is formed on the first wiring member, a resist pattern having a predetermined opening is formed on the insulating film, and the insulating pattern is formed by using the resist pattern as a mask. 8. The method of manufacturing a semiconductor device according to claim 7, wherein the insulating member is formed by subjecting a conductive film to reactive ion etching.