JP2003015955A - Cache controller and computer system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce useless transactions in a computer system having a cache controller that generates a prefetch transaction by itself based on a processor- originated transaction. SOLUTION: The cache controller 102 is provided with: means 121, 125 for holding the processing state, the transaction type, the address or the like of the prefetch transaction generated from the processor-originated transaction; a means 123 for determining whether the access of subsequent processor- originated transaction regarding the address same with that for the advance prefetch transaction is to be retried or waited according to the transaction type of the both; and a means 124 for holding the subsequent processor- originated transaction to be waited until the processing of the advance prefetch transaction is completed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer system having a cache memory between a processor and a main memory, and particularly to a prefetch request (prefetch) autonomously based on an access request (transaction) from the processor to the main memory. The present invention relates to a cache controller for generating and issuing transactions) and a computer system to which the cache controller is applied.

[0002]

2. Description of the Related Art In recent years, in a computer system in which a cache is provided between a processor and a main memory for the purpose of filling a performance difference, in order to effectively use a cache memory and reduce a data read latency from the main memory,
Before the data read request of the processor is received, the prefetch request is used to improve the data that may be used in the future from the main memory to the cache memory in advance.

As a conventional technique of a prefetch request generation circuit, for example, a technique described in Japanese Patent Laid-Open No. 62-192831 is known. This is that the processor issues a prefetch request for data that may be used in the future to the cache controller (cache memory chip), and the cache controller generates another prefetch request based on this prefetch request. .

FIG. 5 is a schematic block diagram of a computer system including a cache controller of this type of prior art. In FIG. 5, 201 is a processor, 2
02 is a cache controller, 205 is main memory, 2
Reference numeral 06 is a cache memory. The cache controller 202 includes a prefetch control unit 203 that generates a prefetch request, a cache memory 206, and a main memory 20.
Cache control unit 204 for reading data from
Composed of.

The prefetch control section 203 receives an address register 209 for latching address data output from the processor 201 via a path 250, a line size register 207 for storing a cache line width (or block width), and a path 256. Address signal received from the address register 209 and the line size received from the line size register 207 via the path 251 and the select signal received via the path 257 to the address data received via the paths 256 and 252. And a transaction selection unit 210 that issues address data to the cache control unit 204 via the path 253, and an access request or prefetch request from the processor 201 via the path 250. And a control unit 211 which generates a select signal for-transactions selector 210.

The operation of the cache controller 202 will be described below. Processor 201 is pass 2
A prefetch request is issued to the cache controller 202 along with a data read request via 50. Prefetch control unit 203 of cache controller 202
Then, the control unit 211 receives the request from the processor 201, and its address is the address register 209.
Is set to. The adder 252 uses the address register 2
The line size of the line size register 205 is added to the address of 09. The control unit 211 first generates a select signal via the path 257 so that the transaction selection unit 210 selects the address from the address register 209. At the same time, the control unit 211 issues a data read request to the cache control unit 204 via the path 254. The transaction selection unit 210 selects the address of the address register 209 and sends it to the cache control unit 204 via the path 253.

The cache control unit 204 determines whether the data corresponding to the read request is already stored in the cache memory 206. If the data is stored, the cache control unit 204 reads the data from the cache memory 206 via the path 258, and the path 259. To the processor 201, the control unit 211 is notified of the completion of data reading via the path 254, and the processing is ended. On the other hand, when the data corresponding to the read request is not stored in the cache memory 206, the cache control unit 204 reads the data from the main memory 205 via the path 257, writes the data in the cache memory 206 via the path 258, and simultaneously writes the path 259. The read data from the main memory 205 is sent to the processor 201 via the
The completion of data reading is notified via 4. At this point, the control unit 211 selects the next prefetch address via the path 257 so as to select the next prefetch address.
Send a select signal to 10. Transaction selection part 2
10 passes the address data from the adder 208 to the path 252
Via the path 253 and output to the cache control unit 204. The cache control unit 204 uses the path 2
The data next to the previous read request is read from the main memory 257 via 57, written to the cache memory 206 via the path 258, and when the data is completed, the control unit 211 is notified of the completion of the data read.
The control unit 211 reports the completion of the prefetch operation to the processor 201 via the path 255.

[0008]

In the above-mentioned prior art, when there is a prefetch request, the data read into the cache memory is only two lines of the data requested by the processor and the next data on condition of a cache miss. However, in order to prefetch data other than the 2-line data, there is a drawback that the processor must repeatedly issue the prefetch request. Further, when the processor does not have a function of issuing a prefetch request, the cache controller does not generate the prefetch request by itself, so that the prefetch does not occur and the cache memory cannot be effectively used.

On the other hand, for example, Japanese Patent Laid-Open No. 2001-601
In Japanese Patent Laid-Open No. 69, the cache controller itself generates a plurality of prefetch requests (prefetch transactions) in response to a prefetch request issued from the processor or a request other than the prefetch to the main memory, and more data is stored in the cache memory. Writing enables effective use of cache memory.
However, here, it is not taken into consideration that a wasteful transaction is issued to the system when a processor-originated transaction and a prefetch transaction access (compete with) the same address.

It is an object of the present invention, in a computer system having a cache memory between a processor and a main memory, to generate a prefetch transaction in the cache controller itself and realize effective use of the cache memory, in order to effectively utilize the cache memory. Avoiding transaction conflicts and reducing wasted transactions in the system.

[0011]

In order to achieve the above object, the present invention has a processing state and a transaction type of a prefetch transaction which the cache controller itself generates from an access request (processor originating transaction) to a main memory issued from a processor. , A means for holding an address, etc., and a means for judging whether to retry or wait the access of a subsequent processor-originated transaction to the same line as the preceding prefetch transaction. Further, a means is provided for holding a subsequent processor-originated transaction that is decided to wait until the processing of the predecessor prefetch transaction is completed.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be specifically described below with reference to FIGS. FIG. 1 is a block diagram showing an embodiment of a cache controller of the present invention and a computer system to which the cache controller is applied.
In FIG. 1, 101 is a processor, 102 is a cache controller according to the present invention, 103 is main memory, 104
Is a cache memory. Cache controller 1
Reference numeral 02 denotes a prefetch control unit 105 that generates and controls a prefetch transaction, and a cache memory 104.
And a cache control unit 106 that controls access to the main memory 103. Cache control unit 106
Is basically the same as the conventional one.

The prefetch control unit 105 generates a prefetch transaction (prefetch request) from a transaction (access request) addressed to the main memory 103 issued from the processor 101, and a prefetch transaction generated by the prefetch generation unit 122. Multiple-entry prefetch transaction type & address register 121 for storing types and addresses, the prefetch transaction type &
The prefetch transaction processing status register 125, the prefetch transaction processing status register 124, the prefetch transaction processing status register 124, and the prefetch transaction type & address register 121 that hold the processing status (unprocessed, processing completed, etc.) of the prefetch transaction corresponding to each entry of the address register 121. Wa that determines whether to wait or retry a transaction addressed to the main memory 103 originating from the processor 101 based on the information Wa
It determination unit 123, a plurality of entries of NTHI for temporarily holding a transaction (NTHIT transaction) destined for the main memory 103 from the processor 101, which has been decided to wait according to the determination result of the Wait determination unit 123.
T transaction Wait register 124, NTHI
T transaction Wait register 124, prefetch transaction type & address register 121, and arbitration of a transaction from processor 101 addressed to main memory 103, and the transaction is cache control unit 10.
6 is included in the transaction issuing unit 126. For the registers 121, 124, and 125, for example, a FIFO stack memory is used. Also, the prefetch transaction type & address register 12
By adding a processing state flag to each entry of 1,
Prefetch transaction processing status register 125
May be omitted.

First, the prefetch operation of the cache controller 102 will be described. The transaction issuing unit 126 of the prefetch control unit 105 uses the path 159.
The prefetch transaction processing status register 125 is monitored via, and if there is an unprocessed prefetch transaction, the prefetch transaction type &
The prefetch transaction of the corresponding entry of the address register 121 is issued to the cache control unit 106 via the paths 160 and 161. Cache control unit 106
Determines whether the data for the prefetch transaction already exists in the cache memory 104 (cache hit determination), and if it already exists (cache hit), does nothing and sends the processing completion notification directly to the path 163.
To the prefetch transaction processing status register 125, and the status of the corresponding entry in the register is updated to processing completion. On the other hand, when the data for the prefetch transaction does not exist in the cache memory 104 (cache miss), the cache control unit 10
6 reads the corresponding data from the main memory 103 via the path 164, and the cache memory 10 via the path 162.
4, and updates the status of the corresponding entry of the prefetch transaction processing status register 125 to the processing completion via the path 163. This prefetch operation is normally performed subsequent to the processing of a transaction from the processor 101 addressed to the main memory 103.

Next, the operation of the cache controller 102 when a transaction is issued from the processor 101 according to the present invention to the main memory 103 will be described. FIG. 2 particularly illustrates the prefetch control unit 105 in this case.
The processing flowchart of is shown.

It is assumed that the processor 101 issues a transaction addressed to the main memory 103 to the cache controller 102 via the path 155. In the cache controller 102, the prefetch generation unit 122 and the Wait determination unit 123 of the prefetch control unit 105 receive the transaction from the processor 101 addressed to the main memory 103 (step 11). Prefetch generation unit 122
When the transaction addressed to the main memory 103 originating from the processor 101 is Read, a prefetch transaction with a different address is generated by the same transaction type as the transaction originating from the processor 101, and the prefetch transaction type & address register 121 via the path 154. And the prefetch transaction processing status register 125 (step 12).
At the same time, the processing status of the corresponding entry of the prefetch transaction processing status register 125 is unprocessed. The prefetch address is, for example, Japanese Patent Laid-Open No. 2001-601.
As described in Japanese Patent Publication No. 69, one or more addresses are generated based on the address of a transaction issued by the processor 101 and a predetermined variable (block size, strite value, etc.).

On the other hand, the Wait determining unit 123 refers to the prefetch transaction type & address register 121 and the prefetch transaction processing status register 125 via the paths 152 and 153 to refer to the processor 10.
It is determined whether or not there is an unprocessed start prefetch transaction having the same address as the address of the transaction addressed to the main memory 103 (step 13). Then, when there is no advance prefetch transaction of the same address, the Wait determination unit 123 sends the transaction addressed to the main memory 103 from the processor 101 to the transaction issuing unit 126 via the path 156, and the transaction issuing unit 126 causes the processor 101 to issue the transaction. Is issued to the cache control unit 106 via the path 161 (step 14).

The cache control unit 106, which has received the transaction addressed to the main memory 103 from the processor 101, makes a cache hit determination, and in the case of a cache miss, reads / writes data from the main memory 103 via the path 164. To do. In the case of a cache hit, data is read / written from the cache memory 104 via the path 162. When the transaction issued by the processor 101 is Read, return data is returned to the processor 101 via the path 151, and in the case of a cache miss, it is also registered in the cache memory 104 via the path 162. If the transaction issued by the processor 101 is Write, the completion of data writing is reported to the processor 101 via the path 151. When the processing of the transaction originating from the processor 101 and addressed to the main memory 103 is completed, the prefetch operation is started.

If there is an unprocessed prefetch transaction with the same address as the address of the transaction addressed to the main memory 103 issued by the processor 101, Wa
The it determining unit 123 compares the transaction type of the subsequent transaction issued by the processor 101 (latest NTHIT transaction) with the transaction type of the competing previous prefetch transaction (step 15). Here, the transaction issued by the later processor 101 is Read & INV, and the unprocessed earlier prefetch transaction of the same address as that of Read & INV is Rea.
In the case of d (Case 1), the Wait determination unit 123 determines the path 1 for the subsequent Read & INV transaction.
A retry request is issued to the processor 101 via 65 to retry (step 19). In the case of other combinations (case 2), the Wait determination unit 123 determines that the subsequent transaction from the processor 101 (the later NTHI
T transaction) to NTHIT transaction W
The subsequent NT is registered in the ait register 124 until the processing of the conflicting first prefetch transaction is completed.
The issuance of the HIT transaction is awaited (step 16). After that, NTHIT transaction Wai
When the t register 124 receives the processing completion of the predecessor prefetch transaction from the prefetch transaction processing status register 125 via the path 157, the t register 124 sends the corresponding late NTHIT transaction to the transaction issuing unit 126 via the path 158. , Issues a subsequent processor-originated NTHIT transaction to the cache control unit 106 via the path 161 (step 1
7, 18).

NT of late processor transaction
The cache control unit 10 that has received the HIT transaction
6 judges the cache hit, but since the corresponding pre-fetch transaction has been completed,
The relevant data is read from the cache memory 104 and returned to the processor 101 via the path 151.
Then, the prefetch operation starts again.

The combination of transaction types in the case where the late processor-originated transaction and the predecessor prefetch transaction compete with each other and the operation of the late-origin processor-originated transaction at that time are summarized as shown in FIG.

In this embodiment, a single processor system is used for simplicity of explanation, but the present system can be extended to a multiprocessor system, and the cache state is operated using MESI. Generally, the cache memory sets the state of the cache line (block) to "M" for cache coherency control.
"modified" (changed), "Exclusiv"
e ”(exclusive),“ Shared ”(shared),“ Inv ”
It is managed in four states (MESI) of "alid" (invalid). “Invalid” (I) indicates that the cache line does not contain valid data.
“Shared” (S) has the same data (clean data) as the main memory in the cache line,
It indicates that this data exists (is shared) in other caches. “Exclusive” (E) indicates that the cache line contains the same data (clean data) as the main memory and this data does not exist in another cache. "Modify
“D” (M) indicates that data (dirty data) that may be different from the main memory is stored in the cache line, and this data does not exist in another cache. That is, when the data is written in the cache line, the data becomes dirty and may be different from the main memory. For the MESI algorithm,
For example, it is described in detail in Japanese Patent Laid-Open No. 9-293060.

The Read transaction originating from the processor 101 is a transaction for changing the cache state to the exclusive (E) or share (S) state. The Read & INV transaction issued from the processor 101 is generally issued prior to Write, and is a transaction for setting the cache state to E and invalidating (I) the cache state of another processor. The cache controller 102 generates the same kind of transaction as the transaction issued by the processor 101 when generating the prefetch transaction. Therefore, the transaction issued by the later processor is Read
& INV causes the prefetch transaction to be Re
If unprocessed in ad, the subsequent Read & INV transaction causes reprocessor 101 to try via path 165. In the case of other combinations, it is stored in the NTHIT transaction Wait register 124 and is issued after the corresponding prefetch transaction is completed.

Next, using the multiprocessor system of FIG. 4, the pre-started prefetch transaction is read.
And the transaction issued by the processor is Read & I
Details of the retry operation in the case of NV will be described.

FIG. 4 shows a multiprocessor system in which the processors 101 and 301 share the main memory 103 via the cache controllers 102 and 30, respectively. Since the configurations of the cache controllers 102 and 302 are the same as those of the system of FIG. 1, description thereof will be omitted.

From the processor 301 to Read & INV
When a transaction is issued, data is read from the main memory 103, the cache state of the cache memory 104 is invalidated, the cache state of the cache memory 304 is set to exclusive (E), and the data is returned to the processor 301. This operation enables the processor 301 to modify the data.
After that, the cache controller 102 responds to the Read transaction issued from the processor 101.
Issues a prefetch transaction to the same address as the transaction issued by the processor 301 described above. The prefetch transaction changes the cache state of the cache memories 104 and 304 to the shared state and registers the data in the cache memory 104. When the Read & INV transaction is issued from the processor 101 before the completion of this prefetch transaction, the cache controller 102 outputs W
The ait determination unit 123 sends a path 16 to the processor 101.
A retry request is returned via 5. The prefetch transaction shares the cache state, but the subsequent Read & INV transaction from the processor 101 has to invalidate the cache state of the cache memory 304. For this reason, even if the prefetch transaction is issued in advance, the subsequent transaction can be processed in the main memory 103 and the cache memory 304.
Is reissued to the processor 101, and is returned to the processor 101 via the path 165.

It should be noted that the transaction type of the predecessor prefetch transaction is compared with the transaction type of the late processor, and the prefetch transaction type of the predecessor is Read and the transaction of the late processor is Rea.
In the case of d & INV, the cache controller 102
Returns a retry to the processor 101, and N
The transaction issued from the THIT transaction Wait register 124 is the local cache memory 104.
It can be limited to only the address.

[0028]

As described above, according to the present invention,
When a subsequent processor originating transaction for the same address as the preceding prefetch transaction occurs, the number of useless memory-addressed transactions can be reduced by making the latter processor originating transaction wait until the beginning prefetch transaction is completed or retrying.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration example of a computer system to which the present invention is applied.

FIG. 2 is a processing flowchart of main operations in the cache controller according to the present invention.

FIG. 3 is a diagram showing case classification of an operation of a late-origin processor-originated transaction according to the present invention.

FIG. 4 is a block diagram showing a configuration example of a computer system when the present invention is applied to a multiprocessor system.

FIG. 5 is a diagram showing a configuration example of a computer system to which a conventional technique is applied.

[Explanation of symbols]

101 Processor 102 Cache Controller 103 Main Memory 104 Cache Memory 105 Prefetch Control Unit 106 Cache Control Unit 121 Prefetch Transaction Type & Address Register 122 Prefetch Generation Unit 123 Wait Determination Unit 124 NTHIT Transaction Wait Register 125 Prefetch Transaction Processing Status Register 126 Transaction Issuing Unit

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Claims (3)

[Claims] 1. A main memory and a cache memory are access-controlled, a prefetch transaction is autonomously generated from a transaction from a processor to the main memory (hereinafter, a processor-originated transaction), and data is prefetched from the main memory to a cache memory. In the cache controller equipped with the means, it is determined whether the subsequent processor-originated transaction and the predecessor prefetch transaction access the same address. A cache controller having means for waiting for a transaction originating from a processor or for retrying by the processor. 2. The cache controller according to claim 1, wherein a transaction type issued by a processor that is subsequently issued is R.
A cache controller characterized by causing a subsequent processor-initiated transaction to be retried by the processor when the predecessor prefetch transaction type is read in READ & INV, and waiting for the later-initiated processor-initiated transaction otherwise. 3. A cache controller in a computer system comprising a processor, a main memory, a cache memory for storing a part of data stored in the main memory, and a cache controller for controlling access to the main memory and the cache memory. Is a means for autonomously generating a prefetch transaction from a transaction from the processor to the main memory (a transaction originating from the processor); a means for prefetching data from the main memory into the cache memory based on the generated prefetch transaction; It is determined whether the processor-originated transaction and the predecessor prefetch transaction access the same address. Processor system, characterized in that it comprises means for retry at the kind or wait for processor onset transaction late depending on the processor of transfection.