JP2003008901A - Image processing method and device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image processing method and device that can emphasize a recording density of only one pixel of consecutive serial image signals. SOLUTION: The image processor comprises a shift register circuit 1 for receiving an image signal S1 before correction and an image transfer clock CLK, a NOT circuit 2 for detecting an image signal of only one pixel from an output of the shift register circuit 1, a 3-input OR circuit 3, a delay circuit 4 for delaying an output of the 3-input OR circuit 3 and an OR circuit 5 for receiving an output of the delay circuit 4 and an output of the shift register circuit 1. An image signal S2 after correction is obtained from the OR circuit 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing method and apparatus, and more particularly to an image processing method and apparatus for recording an image signal converted into an electric signal on a recording medium such as a film by a laser beam.

[0002]

2. Description of the Related Art With the development of computer technology and communication technology, needs for electrically transmitting various image information (data) through a transmission path, performing necessary processing, and recording an image are increasing. . One example thereof is a laser beam printer that records image information on a recording medium such as a film using a laser beam.

The prior art of the image processing system in such a technical field is disclosed, for example, in "Image Processing System" of Japanese Patent Laid-Open No. 61-114652. In this conventional technique, an image processing apparatus for processing an image signal uses a density adjusting circuit for adjusting the density in the main scanning direction. This concentration adjusting circuit has a switch for switching in units of one line, a RAM (random access memory) for storing the output thereof, a parallel serial register for converting the output of the RAM, and a line after one line. A parallel serial register for converting data, an OR circuit or an AND circuit for inputting the outputs of these registers, and this AN
A switch for switching the output of the D circuit in units of one line,
A counter circuit for outputting the switch switching signal is provided. With this configuration, the image signal written in the recording medium is output as an image whose density is changed.

Further, in the conventional image processing method, generally, an input image signal is defined by using an image processing unit constituted by a monostable multivibrator for an input serial image signal. By ensuring the above, the recording reproducibility of fine dots and fine lines is improved.

[0005]

However, in the above-mentioned conventional image processing method, since a uniform signal width is added to the image signal in order to change the density, the halftone dot portion (photograph) in the recorded image (photograph) is added. There was a problem that parts) etc. would be crushed. Further, when recording an image signal subjected to error diffusion processing, since the recording reproducibility of one pixel of the image signal is important, it is possible to secure the signal width above the regulation only for the image signal width of one pixel of the image signal. There was a problem that I could not.

[0006]

SUMMARY OF THE INVENTION It is an object of the present invention to improve the recording reproducibility by recording a signal width of one pixel of the image signal, which is equal to or more than a prescribed value, in recording the image signal subjected to error diffusion processing. An object of the present invention is to provide an image processing method and apparatus capable of performing the image processing.

[0007]

An image processing method of the present invention is an image processing method for receiving a serial image signal transmitted through a transmission path and recording the serial image signal on a recording medium, and a continuous serial image signal An image signal for recording only one pixel is found, the signal width is delayed by a predetermined delay amount only for this image signal, and the received image signal is output for the image signal of two pixels or more. The feature is that it is output as it is. According to the preferred embodiment, the delay amount can be set arbitrarily. The corrected image signal is used to record on a recording medium with a laser beam.

The image processing apparatus of the present invention is an image processing apparatus that corrects an image signal input as a serial image signal and outputs the corrected image signal to a recording means, and a shift register circuit that receives the input image signal as an input. And detecting an image signal of only one pixel from the output of this shift register circuit
A T circuit, a NOR circuit that receives the output of the NOT circuit and the shift register circuit as an input, a delay circuit that delays the output of the NOR circuit, and an output of the delay circuit and an output of the shift register circuit after the correction. And an OR circuit for obtaining an image signal. According to a preferred embodiment, the shift register circuit has three output terminals,
One output terminal of these three output terminals is directly connected to the NOR circuit through the NOT circuit, and the output of the delay circuit and the one output of the shift register circuit are input to the OR circuit. The delay circuit can control the delay amount by receiving a delay amount set value from the outside. The laser beam of the laser beam recorder is controlled by the corrected image signal from the OR circuit.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration and operation of a preferred embodiment of an image processing method and apparatus according to the present invention will be described in detail below with reference to the accompanying drawings.

First, FIG. 1 is a block diagram showing a main part configuration of a preferred embodiment of an image processing apparatus according to the present invention.
This image processing apparatus includes a shift register circuit 1 and a NOT
(Inversion) circuit 2, 3-input NOR circuit 3, delay circuit 4 and OR circuit 5.

The shift register circuit 1 includes a data input terminal D, a clock input terminal CLK and three output terminals Q.
a, Qb, Qc. The image signal S1 before correction is input to the data input terminal D of the shift register circuit 1,
The image signal transfer clock C is connected to the clock input terminal CLK.
LK is input. Then, output signals having different phases are output from the output terminals Qa-Qc of the shift register circuit 1 as described later.

The output terminals Qa and Qc of the shift register circuit 1 are directly connected to the 3-input NOR circuit 3. On the other hand, the output terminal Qb of the shift register circuit 1 is input to the 3-input NOR circuit 3 via the NOT circuit 2. This 3
The output of the input NOR circuit 3 is input to the delay circuit 4.
A delay amount set value for controlling the delay time is input to the delay circuit 4. Further, the output terminal of the delay circuit 4 and the output terminal Qb of the shift register circuit 1 are connected to the OR circuit 5. Then, the corrected output signal S2 is output from the output terminal of the OR circuit 5.

In the block diagram of FIG. 1, the 3-input NOR circuit 3 and the OR circuit 5 are respectively represented by a single NOR element and an OR element for the sake of convenience. However, it is also possible to configure the plurality of logic circuits to take the NOR condition and the OR condition.

Next, FIG. 2 is a timing chart for explaining the image processing operation of the image processing apparatus according to the present invention shown in FIG. In FIG. 2, (a) is the image signal transfer clock CLK, (b) is the image signal S1 before correction, (c),
(D) and (e) are output signals SQa, SQb, SQ of the output terminals Qa, Qb, Qc of the shift register circuit 1, respectively.
c, (f) are output signals Snor of the NOR circuit 3, (g)
The output signals Sdey of the delay circuit 4 and (h) are examples of the corrected image signal S2 output from the OR circuit 5.

In this image processing apparatus, the image signal S1 before correction (see FIG. 2A) is input to the data input terminal D of the shift register circuit 1. Then, the image signal transfer clock CLK (see FIG. 2B) that rises and changes at the logical change point of the image signal S1 before correction is input to the clock terminal CLK of the shift register circuit 1.

From the output terminals Qa, Qb and Qc of the shift register circuit 1, the image signal S shifted by one clock by the image transfer clock CLK is provided.
Qa, SQb, and SQc (see FIGS. 2C, 2D, and 2E) are output. The NOT circuit 2 and the 3-input NOR circuit 3 output the output signals SQa to SQ from the Qa, Qb and Qc output terminals of the shift register circuit 1.
The output logic of c is SQa at "L" level, SQa
The output signal Snor of the 3-input NOR circuit 3 outputs the “H” level for one pixel only when b is at the “H” level and SQc is at the “L” level (see FIG. 2F).

Then, the output signal Sdey of the delay circuit 4
Outputs the output of the 3-input NOR circuit 3 after delaying the delay set value (td) (see FIG. 2 (g)). The OR circuit 5 outputs the output Sde of the delay circuit 4 described above.
y and the output SQb of the Qb terminal of the shift register circuit 1 are input, and the calculation result is output as the corrected image signal S2 (see FIG. 2 (h)). Here, by inputting a delay amount set value from the outside to the delay circuit 4 and varying the set value, the delay time (or the extension of the signal width of one pixel data) td shown in FIG. It is possible to control.

The image processing apparatus of this preferred embodiment is a CTS (Comput) that enables distributed printing in, for example, a newspaper company.
erized Typesetting System (CTP), which is one of the image processing devices used when outputting a printing plate set on a rotary press in a typesetting system.
to Plate). In this CTP, paper image data and parameters are received via a dedicated line. Then, a configuration is adopted in which the image data of the paper surface is recorded on the printing plate plate by a semiconductor laser (laser beam) and the printing plate plate is sent to the automatic developing machine. In this type of image processing apparatus, even if the recording resolution of one pixel is deteriorated due to the effect of the color development characteristics of the photosensitive material of the printing plate, recording of one pixel is performed by using the image processing apparatus of the embodiment of the present invention. The reproducibility of resolution can be improved.

The configuration and operation of the preferred embodiment of the image processing method and apparatus according to the present invention have been described above in detail. However, such an embodiment is merely an example of the present invention,
It does not limit the present invention in any way. Those skilled in the art can easily understand that various modifications and changes can be made according to a specific application without departing from the gist of the present invention. The present invention can be applied to, for example, a laser beam printer, a copying machine, a facsimile machine, and the like that use a laser beam.

[0020]

As can be understood from the above description, according to the image processing method and apparatus of the present invention, the following remarkable practical effects can be obtained. That is, even when the image signal subjected to the error diffusion processing is recorded, the signal reproducibility can be improved as a result of ensuring that the signal width of the image signal of one pixel of the image signal exceeds the regulation. Further, the specific means therefor is composed of a shift register, a logic circuit and a delay circuit, so that it is extremely simple and inexpensive. Further, the delay amount of the delay circuit can be appropriately set by a delay amount set value from the outside.

[Brief description of drawings]

FIG. 1 is a block diagram showing a main part configuration of a preferred embodiment of an image processing apparatus according to the present invention.

FIG. 2 is a timing chart explaining the operation of the image processing apparatus shown in FIG.

[Explanation of symbols]

1 shift register circuit 2 NOT circuit 3 3-input NOR circuit 4 delay circuits 5 OR circuit Image signal before S1 correction Image signal after S2 correction CLK Image transfer clock Output signal of Snor NOR circuit Output signal of Sdey delay circuit SQa to SQc Output signal of shift register circuit

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H04N 1/23 103 B41J 3/00 MF term (reference) 2C062 AA34 AA49 2C362 CA05 CA14 CB37 CB71 CB74 CB78 2H084 AA14 AA30 AE03 AE05 AE06 BB02 BB04 BB13 CC05 5C074 AA02 AA08 BB02 BB03 DD01 DD07 EE12 HH02 5C077 LL08 LL19 MP02 NN11 NN17 PP03 PP28 PP43 PP51 PP57 PQ05 TT03

Claims (7)

[Claims] 1. An image processing method for receiving a serial image signal transmitted via a transmission path and recording the serial image signal on a recording medium, wherein an image signal for recording only one pixel of the continuous serial image signals is found, An image processing method, which delays a signal width by a predetermined delay amount only for an image signal and outputs the image signal having two or more pixels without changing the signal width of the received image signal. . 2. The image processing method according to claim 1, wherein the delay amount can be set arbitrarily. 3. The image processing method according to claim 1, wherein the corrected image signal is recorded on the recording medium with a laser beam. 4. An image processing device for correcting an image signal input as a serial image signal and outputting the corrected image signal to a recording device. A shift register circuit to which the input image signal is input, and an output of the shift register circuit. A NOT circuit that detects an image signal of only one pixel, a NOR circuit that receives the outputs of the NOT circuit and the shift register circuit, a delay circuit that delays the output of the NOR circuit, an output of the delay element and the An image processing apparatus, comprising: an OR circuit that receives an output of the shift register circuit and outputs a corrected image signal. 5. The shift register circuit has three output terminals, one of the three output terminals being the NOT terminal.
The other two output terminals are directly connected to the NOR circuit via a circuit, and the output of the delay circuit and the one output of the shift register circuit are input to the OR circuit. Image processing device. 6. The image processing apparatus according to claim 4, wherein the delay circuit is capable of controlling the delay amount by receiving a delay amount set value from the outside. 7. The image processing device according to claim 4, 5 or 6, wherein the laser beam of the laser beam recording device is controlled by using the corrected image signal from the OR circuit.