JP2003008363A - Wide band amplification circuit - Google Patents

Wide band amplification circuit

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Publication number
JP2003008363A
JP2003008363A JP2001188969A JP2001188969A JP2003008363A JP 2003008363 A JP2003008363 A JP 2003008363A JP 2001188969 A JP2001188969 A JP 2001188969A JP 2001188969 A JP2001188969 A JP 2001188969A JP 2003008363 A JP2003008363 A JP 2003008363A
Authority
JP
Japan
Prior art keywords
stage
amplifier circuit
mesfet
mesfets
transformer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001188969A
Other languages
Japanese (ja)
Inventor
Akihito Nagamatsu
昭仁 永松
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP2001188969A priority Critical patent/JP2003008363A/en
Publication of JP2003008363A publication Critical patent/JP2003008363A/en
Pending legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To enable hybrid constitution by mounting MESFETs or the like for constituting a wide band amplification circuit on a single layer board. SOLUTION: This wide band amplification circuit is provided with a first amplification circuit 25 and a second amplification circuit 26 which are push-pull connected between an input transformer 20 and an output transformer 22 and constituted of a plurality of stages of MESFETs 27a, 27b, 28a, 28b, 29a, 29b. A plurality of stages of the MESFETs, wide band blocking inductors 32a, 32b and other chip components are attached on the single layer board. Gate bias wires 30 of the MESFETs are made to pass under the inductors 32a, 32b.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、CATV等の多チ
ャンネル広帯域に亘り信号を安定に増幅する広帯域増幅
回路に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wide band amplifier circuit for stably amplifying a signal over a multi-channel wide band such as CATV.

【0002】[0002]

【従来の技術】CATV等においては、100チャンネ
ル以上の映像信号チャンネルを実現することが試みられ
ている。通常1チャンネルの周波数帯域は約6MHzで
あるから、100チャネルの多チャンネル化するには約
600MHzの広い周波数帯域に亘って低ひずみで、且
つ一様な高利得で増幅できる広帯域増幅回路が必要とさ
れる。
2. Description of the Related Art In CATV and the like, it has been attempted to realize more than 100 video signal channels. Normally, one channel has a frequency band of about 6 MHz, so in order to increase the number of channels to 100 channels, a wide-band amplifier circuit capable of amplifying with low distortion and uniform high gain over a wide frequency band of about 600 MHz is required. To be done.

【0003】図3は従来の広帯域増幅回路である。入力
端子INに接続された入力トランス等の電力分配器1と
出力端子OUTに接続された出力トランス等よりなる電
力結合器2との間には第1の増幅回路3と第2の増幅回
路4とがプッシュプルに接続されている。
FIG. 3 shows a conventional wide band amplifier circuit. A first amplifier circuit 3 and a second amplifier circuit 4 are provided between a power distributor 1 such as an input transformer connected to the input terminal IN and a power combiner 2 including an output transformer connected to the output terminal OUT. And are connected to push-pull.

【0004】前記第1の増幅回路3は第1段目増幅用の
MESFET5aと、該MESFET5aのドレイン電
極にゲート電極が接続された第2段目増幅用のMESF
ET6aおよび第2段目増幅用のMESFET6aのド
レイン電極にソース電極が接続された3段目増幅用のM
ESFET7aとよりなる。前記第1段目増幅用のME
SFET5aのドレイン電極とゲート電極間には抵抗8
a及びコンデンサ9aなる第1帰還回路10aが接続さ
れている。又第3段目増幅用のMESFET7aのドラ
イン電極と第2段目増幅用のMESFET6aのゲート
電極には抵抗11aとコンデンサ12aとよりなる第2
帰還回路13aが接続されている。
The first amplification circuit 3 includes a MESFET 5a for the first-stage amplification and a MESF for the second-stage amplification in which the gate electrode is connected to the drain electrode of the MESFET 5a.
ET6a and MESFET6a for the second stage amplification. M for the third stage amplification in which the source electrode is connected to the drain electrode.
It is composed of ESFET 7a. ME for the first-stage amplification
A resistor 8 is provided between the drain electrode and the gate electrode of the SFET 5a.
The first feedback circuit 10a including the capacitor a and the capacitor 9a is connected. Further, the drain electrode of the third-stage amplification MESFET 7a and the gate electrode of the second-stage amplification MESFET 6a have a second resistor 11a and a capacitor 12a.
The feedback circuit 13a is connected.

【0005】前記第2の増幅回路4も第1の増幅回路3
と同様な構成をなし、第1段目増幅用のMESFET5
bと、該MESFET5bのドレイン電極にゲート電極
が接続された第2段目増幅用のMESFET6bおよび
第2段目増幅用のMESFET6bのドレイン電極にソ
ース電極が接続された3段目増幅用のMESFET7b
とよりなる。
The second amplifier circuit 4 is also the first amplifier circuit 3
MESFET5 for the first stage amplification with the same configuration as
b, a MESFET 6b for second-stage amplification in which the gate electrode is connected to the drain electrode of the MESFET 5b, and a MESFET 7b for third-stage amplification in which the source electrode is connected to the drain electrode of the MESFET 6b for second-stage amplification
And consists of.

【0006】前記第1段目増幅用のMESFET5bの
ドレイン電極とゲート電極間には抵抗8b及びコンデン
サ9bなる第3帰還回路10bが接続されている。又第
3段目増幅用のMESFET7bのドレイン電極と第2
段目増幅用のMESFET6bのゲート電極には抵抗1
1bとコンデンサ12bとよりなる第4帰還回路13b
が接続されている。
A third feedback circuit 10b consisting of a resistor 8b and a capacitor 9b is connected between the drain electrode and the gate electrode of the first stage amplification MESFET 5b. In addition, the drain electrode of the MESFET 7b for the third amplification and the second
A resistor 1 is connected to the gate electrode of the MESFET 6b for the stage amplification
Fourth feedback circuit 13b including 1b and capacitor 12b
Are connected.

【0007】前記第1段目増幅用のMESFET5aと
MESFET5bのソース電極とは抵抗15で結合さ
れ、同様に前記第2段目増幅用のMESFET6aとM
OSFET6bのソース電極とは抵抗16で結合されて
いる。さらに前記第3段目増幅用のMESFET7aと
MESFET7bのゲート電極とは抵抗17で結合され
ている。
The source electrodes of the first-stage amplification MESFET 5a and MESFET 5b are coupled by a resistor 15, and similarly, the second-stage amplification MESFET 6a and M are also connected.
The source electrode of the OSFET 6b is coupled with the resistor 16. Furthermore, the third-stage amplification MESFET 7a and the gate electrode of the MESFET 7b are connected by a resistor 17.

【0008】前記第1段目増幅用のMESFET5aと
MESFET5b及び前記第2段目増幅用のMESFE
T6aとMESFET6bのソース電極とは夫々抵抗1
5及び抵抗16で仮想的に接地され、これらMESFE
T5a、MESFET5bとMESFET6a、MES
FET6bとの特性のバラツキによる二次ひずみを除去
し、安定性を向上している。また前記第3段目増幅用の
MESFET7aとMESFET7bのゲート電極とは
抵抗17でバイアス電圧を供給し、高周波側の利得を抑
えゲイン接地動作の安定化を図っている。
The first stage MESFET 5a and MESFET 5b for amplification and the second stage MESFE for amplification.
The source electrodes of T6a and MESFET6b have a resistance of 1
5 and resistor 16 are virtually grounded, and these MESFE
T5a, MESFET5b and MESFET6a, MES
The secondary distortion due to the variation in the characteristics with the FET 6b is removed, and the stability is improved. A bias voltage is supplied to the gate electrodes of the third-stage amplification MESFET 7a and MESFET 7b by a resistor 17 to suppress the gain on the high frequency side and stabilize the gain grounding operation.

【0009】従って入力端子INに加えられた入力信号
は前記第1段目増幅用のMESFET5aとMESFE
T5b及び前記第2段目増幅用のMESFET6aとM
ESFET6bで増幅され、さらに第3段目増幅用のM
ESFET7aとMESFET7bで増幅される。前記
第3段目増幅用のMESFET7aとMESFET7b
で増幅された高周波出力信号は電力結合器2を介して出
力端子OUTに取り出される。
Therefore, the input signal applied to the input terminal IN is supplied to the MESFET 5a for amplifying the first stage and MESFE.
T5b and the second stage MESFET 6a for amplification and M
Amplified by ESFET6b, M for the third stage amplification
It is amplified by the ESFET 7a and the MESFET 7b. The third stage amplification MESFET 7a and MESFET 7b
The high frequency output signal amplified by is output to the output terminal OUT via the power combiner 2.

【0010】[0010]

【発明が解決しようとする課題】従来の広帯域増幅回路
は上述のように、第1段目増幅用のMESFET5a
と、第2段目増幅用のMESFET6aおよび3段目増
幅用のMESFET7aとよりなる第1の増幅回路3
と、同じく第1段目増幅用のMESFET5bと、第2
段目増幅用のMESFET6bおよび3段目増幅用のM
ESFET7bとよりなる第2の増幅回路4とをプッシ
ュプルに接続している。
As described above, the conventional wide-band amplifier circuit uses the MESFET 5a for the first-stage amplification.
And a first amplification circuit 3 including a second-stage amplification MESFET 6a and a third-stage amplification MESFET 7a.
Similarly, MESFET 5b for the first stage amplification, and the second
MESFET 6b for the third stage amplification and M for the third stage amplification
The ESFET 7b and the second amplifier circuit 4 including the ESFET 7b are connected to each other by push-pull.

【0011】このように6個のMESFETの他、接地
抵抗やバイアス抵抗の回路部品を1チップで構成してい
るため高度な技術が必要とした。また前記チップを取り
付けた基板上の配線の引き回しがやや複雑になる。さら
に1チップICを実装するための専用のパッケージが必
要である。
As described above, in addition to the six MESFETs, the circuit components such as the ground resistance and the bias resistance are composed of one chip, so that a high level of technology is required. In addition, the wiring of the wiring on the substrate to which the chip is attached becomes a little complicated. Furthermore, a dedicated package for mounting a one-chip IC is required.

【0012】[0012]

【課題を解決するための手段】本発明は高周波信号が加
えられる入力トランスと、前記高周波信号を取り出す出
力トランスと、前記入力トランスと出力トランス間にプ
ッシュプル接続され複数段のMESFETを有する第1
の増幅回路と第2の増幅回路とよりなり、単層基板に前
記複数段のMESFET及び広帯域阻止インダクタを取
り付け、前記MESFETのゲートバイアス線を広帯域
阻止インダクタの下を通過させる広帯域増幅回路を提供
する。
The first aspect of the present invention includes an input transformer to which a high frequency signal is applied, an output transformer for extracting the high frequency signal, and a plurality of stages of MESFETs which are push-pull connected between the input transformer and the output transformer.
And a second amplifying circuit, the multistage MESFET and the wideband blocking inductor are mounted on a single-layer substrate, and a wideband amplifying circuit is provided in which the gate bias line of the MESFET is passed under the wideband blocking inductor. .

【0013】又本発明は高周波信号が加えられる入力ト
ランスと、前記高周波信号を取り出す出力トランスと、
前記入力トランスと出力トランス間にプッシュプル接続
され複数段のMESFETを有する第1の増幅回路と第
2の増幅回路とよりなり、前記第1の増幅回路と第2の
増幅回路はゲート電極に高周波入力信号が加えられソー
ス電極を抵抗で結合し仮想的に接地した上下1対の第1
段目MESFETと、ゲート電極が共通のゲートバイア
ス線でバイアス源に接続されソース電極が抵抗および広
帯域阻止インダクタを介して第1段目MESFETのド
レイン電極に第1段目MESFETに夫々接続された上
下1対の第2段目MESFETとを備え、単層基板に複
数段のMESFET、回路部品及び高周波阻止インダク
タンスを取り付け、前記第2段目MESFETのゲート
バイアス線を第1段目MESFETと第2段目MESF
ETを接続する広帯域阻止インダクタの下を通過させる
広帯域増幅回路を提供する。
According to the present invention, an input transformer to which a high frequency signal is applied, an output transformer for extracting the high frequency signal,
It comprises a first amplifier circuit and a second amplifier circuit having a plurality of stages of MESFETs which are push-pull connected between the input transformer and the output transformer, and the first amplifier circuit and the second amplifier circuit have a high frequency at their gate electrodes. An input signal is applied, the source electrodes are coupled with a resistor, and the pair of upper and lower first electrodes are virtually grounded.
The top and bottom of which the gate electrode and the gate electrode are connected to a bias source by a common gate bias line, and the source electrode is connected to the drain electrode of the first stage MESFET through the resistor and the broadband blocking inductor to the first stage MESFET, respectively. A pair of second-stage MESFETs, a plurality of stages of MESFETs, circuit components, and high-frequency blocking inductance are attached to a single-layer substrate, and the gate bias lines of the second-stage MESFETs are connected to the first-stage MESFETs and the second-stage MESFETs. Eye MESF
A wideband amplifier circuit is provided that passes under a wideband blocking inductor connecting ET.

【0014】さらに本発明は前記第1の増幅回路と第2
の増幅回路の利得が一様な周波数帯域と広帯域阻止イン
ダクタンスの阻止周波数帯域が略同一である広帯域増幅
回路を提供する。
Furthermore, the present invention provides the first amplifier circuit and the second amplifier circuit.
A wide-band amplifier circuit in which the gain band of the amplifier circuit is uniform and the stop band of the wide-band blocking inductance is substantially the same.

【0015】[0015]

【発明の実施の形態】本発明の広帯域増幅回路を図1及
び図2に従って説明する。
BEST MODE FOR CARRYING OUT THE INVENTION A wide band amplifier circuit according to the present invention will be described with reference to FIGS.

【0016】図1において、入力トランス20は巻線2
0a、20b、20c、20dを有する。巻線20aの
一端はCATV等の高周波入力信号が加えられる入力端
子21に接続され、他端は巻線20dの一端に接続さ
れ、また巻線20bと巻線20cの一端とは接続されて
いる。
In FIG. 1, the input transformer 20 is a winding 2
0a, 20b, 20c, 20d. One end of the winding 20a is connected to the input terminal 21 to which a high frequency input signal such as CATV is applied, the other end is connected to one end of the winding 20d, and the windings 20b and 20c are connected to each other. .

【0017】出力トランス22は巻線22a、22b、
22c、22dを有する。巻線22aの出力端は出力端
子23に接続されると共に巻線22dの出力端に接続さ
れ、また巻線20bと巻線20cの出力端とは接続され
ている。
The output transformer 22 includes windings 22a, 22b,
22c and 22d. The output end of the winding wire 22a is connected to the output terminal 23 and the output end of the winding wire 22d, and the output ends of the winding wire 20b and the winding wire 20c are connected to each other.

【0018】前記入力トランス20と出力トランス22
間には第1増幅回路25と第2増幅回路26とが接続さ
れている。第1増幅回路25は第1段目MESFET2
7a、第2段目MESFET28aと第3段目MESF
ET29aとよりなる。
The input transformer 20 and the output transformer 22
A first amplifier circuit 25 and a second amplifier circuit 26 are connected in between. The first amplifier circuit 25 is the first stage MESFET2
7a, second stage MESFET 28a and third stage MESF
It consists of ET29a.

【0019】前記第1段目MESFET27aのゲート
電極は入力トランス20の巻線20bと巻線20cとが
結合された一端に接続されている。前記第1段目MES
FET27aのドレイン電極と第2段目MESFET2
8aのゲート電極はコンデンサ30aと抵抗30bを介
して接続されている。
The gate electrode of the first stage MESFET 27a is connected to one end where the winding 20b and the winding 20c of the input transformer 20 are connected. The first stage MES
The drain electrode of the FET 27a and the second stage MESFET2
The gate electrode of 8a is connected to the capacitor 30a through the resistor 30b.

【0020】又前記第2段目MESFET28aのゲー
ト電極は抵抗30c及び30dを有するゲートバイアス
線30を介しバイアス源31に接続されている。さらに
第1段目MESFET27aのドレイン電極と第2段目
MESFET28aのソース電極は広帯域阻止インダク
タ32aと抵抗33aとを介して直流的に接続されてい
る。
The gate electrode of the second stage MESFET 28a is connected to a bias source 31 via a gate bias line 30 having resistors 30c and 30d. Further, the drain electrode of the first-stage MESFET 27a and the source electrode of the second-stage MESFET 28a are DC-connected via the broadband blocking inductor 32a and the resistor 33a.

【0021】前記ゲート接地された第3段目MESFE
T29aのソース電極と第2段目MESFET28aの
ドレイン電極は接続されると共に、前記第3段目MES
FETのドレイン電極はインダクタ35aを介して出力
トランス22の巻線22cに接続されている。
The third stage MESFE with the gate grounded
The source electrode of T29a and the drain electrode of the second stage MESFET 28a are connected, and the third stage MES is connected.
The drain electrode of the FET is connected to the winding 22c of the output transformer 22 via the inductor 35a.

【0022】前記第1段目MESFET27aのドレイ
ン電極とゲート電極間には抵抗37aとコンデンサ38
aとなる第1帰還回路39aが接続され、また第3段目
MESFET29aのソース電極と第2段目MESFE
T28aのゲート電極間には抵抗40a、41a及びコ
ンデンサ42aよりなる第2帰還回路43aが接続され
ている。
A resistor 37a and a capacitor 38 are provided between the drain electrode and the gate electrode of the first stage MESFET 27a.
The first feedback circuit 39a serving as a is connected to the source electrode of the third stage MESFET 29a and the second stage MESFE.
A second feedback circuit 43a including resistors 40a and 41a and a capacitor 42a is connected between the gate electrodes of T28a.

【0023】第2増幅回路26も第1増幅回路25と同
様な回路構成をなし、第1段目MESFET27b、第
2段目MESFET28bとゲート接地された第3段目
MESFET29bとよりなる。
The second amplifier circuit 26 also has a circuit configuration similar to that of the first amplifier circuit 25, and comprises a first stage MESFET 27b, a second stage MESFET 28b and a third stage MESFET 29b whose gate is grounded.

【0024】前記第1段目MESFET27bのゲート
電極は入力トランス20の巻線20aと20dとが結合
された一端に接続されている。前記第1段目MESFE
T27bのドレイン電極と第2段目MESFET28b
のゲート電極はコンデンサ30eと抵抗30fで接続さ
れている。
The gate electrode of the first stage MESFET 27b is connected to one end where the windings 20a and 20d of the input transformer 20 are coupled. The first stage MESFE
The drain electrode of T27b and the second stage MESFET 28b
The gate electrode of is connected to the capacitor 30e and the resistor 30f.

【0025】第2段目MESFET28bのゲート電極
は抵抗30c及び30dを有する前記ゲートバイアス線
30を介しバイアス源31に接続されており、また第1
段目MESFET27bのドレイン電極と第2段目ME
SFET28bのソース電極は広帯域阻止インダクタ3
2bと抵抗33bとを介して直流的に接続されている。
The gate electrode of the second stage MESFET 28b is connected to the bias source 31 through the gate bias line 30 having the resistors 30c and 30d, and the first
The drain electrode of the second-stage MESFET 27b and the second-stage ME
The source electrode of the SFET 28b is the broadband blocking inductor 3
It is connected in a direct current manner via 2b and a resistor 33b.

【0026】前記ゲート接地された第3段目MESFE
T29bのソース電極と第2段目MESFET28bの
ドレイン電極は接続されると共に、前記第3段目MES
FET29bのドレイン電極はインダクタンス35bを
介して出力トランス22の巻線22dに接続されてい
る。
Third stage MESFE with the gate grounded
The source electrode of T29b and the drain electrode of the second stage MESFET 28b are connected to each other, and the third stage MES is connected.
The drain electrode of the FET 29b is connected to the winding 22d of the output transformer 22 via the inductance 35b.

【0027】前記第1段目MESFET27bのドレイ
ン電極とゲート電極間には抵抗37bとコンデンサ38
bとなる第1帰還回路39bが接続され、また第3段目
MESFET29bのドレイン電極と第2段目MESF
ET28bのゲート電極間には抵抗40b、41b及び
コンデンサ42bよりなる第2帰還回路43bが接続さ
れている。
A resistor 37b and a capacitor 38 are provided between the drain electrode and the gate electrode of the first stage MESFET 27b.
b is connected to the first feedback circuit 39b, and the drain electrode of the third stage MESFET 29b and the second stage MESF are connected.
A second feedback circuit 43b including resistors 40b and 41b and a capacitor 42b is connected between the gate electrodes of the ET 28b.

【0028】前記第1増幅回路25と第2増幅回路26
とはプッシュプル接続されている。即ち前記第1段目M
ESFET27aとMESFET27b及び前記第2段
目MESFET28aとMESFET28bのソース電
極とは夫々抵抗45及び抵抗46で仮想的に接地され、
これらMESFET27a、MESFET27bとME
SFET28a、MESFET28bとの特性のバラツ
キによる二次ひずみを除去し、安定性を向上している。
また前記第3段目MESFET29aとMESFET2
9bのゲート電極とは抵抗47、48でバイアス電圧を
供給し、高周波側の利得を抑えゲイン接地動作の安定化
を図っている。
The first amplifier circuit 25 and the second amplifier circuit 26.
And are push-pull connected. That is, the first stage M
The ESFET 27a and the MESFET 27b and the source electrodes of the second stage MESFET 28a and the MESFET 28b are virtually grounded by a resistor 45 and a resistor 46, respectively.
These MESFET 27a, MESFET 27b and ME
The secondary distortion due to the variation in the characteristics of the SFET 28a and the MESFET 28b is removed, and the stability is improved.
Also, the third stage MESFET 29a and MESFET 2
A bias voltage is supplied to the gate electrode of 9b by resistors 47 and 48 to suppress the gain on the high frequency side and stabilize the gain grounding operation.

【0029】本発明の広帯域増幅回路では前記ベアをな
す6個のMESFET27a、27b、28a、28b
と29a、29b、広帯域阻止インダクタ32a、32
b及びその他の抵抗、コンデンサ等のチップ部品40個
余りを表面が絶縁されたアルミ単板又はアルミナ(AL
23)或いは窒化アルミナ(ALN)の基板に実装し低
コスト化を図っている。
In the wide band amplifier circuit of the present invention, the six bare MESFETs 27a, 27b, 28a, 28b are formed.
And 29a, 29b, broadband blocking inductors 32a, 32
b and other 40 chip parts such as resistors and capacitors, a single aluminum plate or alumina (AL
It is mounted on a substrate of 2 O 3 ) or alumina nitride (ALN) to reduce the cost.

【0030】しかも前記第1増幅回路25と第2増幅回
路26とはプッシュプル接続されており対称に配置され
る。特に広帯域阻止インダクタ32a、32bはスペー
スを取り、配線上問題となる。
Moreover, the first amplifying circuit 25 and the second amplifying circuit 26 are push-pull connected and arranged symmetrically. In particular, the broadband blocking inductors 32a and 32b take up space and pose a wiring problem.

【0031】図2に示すように、前記第1の増幅回路2
5と第2の増幅回路26の利得は10MHz〜1GNz
に亘りほぼ一様である。一方広帯域阻止インダクタンス
32aと32bの阻止周波数帯域は前記第1増幅回路2
5と第2増幅回路26の利得の周波数帯域と略同じ10
MHz〜1GHzであるそこで本発明では前記第2段目
MESFET28aとMESFET28bのゲート電極
を結合すると共にバイアス源31に接続されるゲートバ
イアス線30を広帯域阻止インダクタンス32aと32
bの下を通過させ配線している。
As shown in FIG. 2, the first amplifier circuit 2
5 and the gain of the second amplifier circuit 26 are 10 MHz to 1 GHz
It is almost uniform over the entire range. On the other hand, the blocking frequency band of the broadband blocking inductances 32a and 32b is set to the first amplification circuit 2
5 and the frequency band of the gain of the second amplifying circuit 26, which is substantially the same as 10
Therefore, according to the present invention, the gate bias line 30 which connects the gate electrodes of the second stage MESFET 28a and MESFET 28b and is connected to the bias source 31 is connected to the wide band blocking inductances 32a and 32.
The wiring is made to pass under b.

【0032】このように、広帯域阻止インダクタンス3
2aと32bには10MHz〜1GHzの周波数帯域で
は信号が流れないので、またゲートバイアス線にも信号
が流れないので、広帯域阻止インダクタンス32aと3
2bの下に前記ゲートバイアス線30を配線しても、相
互の干渉は殆んど無い。
Thus, the broadband blocking inductance 3
Since no signal flows in the frequency band of 10 MHz to 1 GHz in 2a and 32b, and also no signal flows in the gate bias line, the broadband blocking inductances 32a and 32b.
Even if the gate bias line 30 is provided under 2b, there is almost no mutual interference.

【0033】本発明の広帯域増幅回路は上述のごとき構
成をなしている。入力端子21に加えられたCATV等
の高周波信号は入力トランス20を介して第1段目ME
SFET27a、27bで歪みがなく、更に第2段目M
ESFET28a、28b及び第3段目MESFET2
9a、29bで増幅される。前記増幅された高周波出力
信号は出力トランス22から出力端子23に取り出され
る。
The wide band amplifier circuit of the present invention has the above-mentioned configuration. A high frequency signal such as CATV applied to the input terminal 21 is transmitted through the input transformer 20 to the first stage ME.
There is no distortion in the SFETs 27a and 27b, and the second stage M
ESFETs 28a, 28b and the third stage MESFET2
It is amplified by 9a and 29b. The amplified high frequency output signal is taken out from the output transformer 22 to the output terminal 23.

【0034】[0034]

【発明の効果】本発明の広帯域増幅回路は入力トランス
と出力トランス間にプッシュプル接続され複数段のME
SFETよりなる第1の増幅回路と第2の増幅回路とを
備え、単層基板に前記複数段のMESFET及び広帯域
阻止インダクタを取り付け、前記MESFETのゲート
バイアス線を広帯域阻止インダクタの下を通過させるよ
うにしたので、ハイブリッドで構成できる。
The wideband amplifier circuit of the present invention is push-pull connected between the input transformer and the output transformer and has a plurality of ME stages.
A first amplifying circuit and a second amplifying circuit made of SFET are provided, and the plurality of stages of MESFETs and the broadband blocking inductor are mounted on a single layer substrate so that the gate bias line of the MESFET passes under the broadband blocking inductor. Because it is set, it can be configured with hybrid.

【0035】しかも前記第1の増幅回路と第2の増幅回
路の利得が一様な周波数帯域と広帯域阻止インダクタン
スの阻止周波数帯域が略同一であるので、ゲートバイア
ス線を広帯域阻止インダクタの下を通過するように配線
しても、信号ラインに影響を線が高周波信号の受ける安
定した増幅動作が実現できる。
Moreover, since the frequency band in which the gains of the first amplifier circuit and the second amplifier circuit are uniform and the blocking frequency band of the broadband blocking inductance are substantially the same, the gate bias line passes under the broadband blocking inductor. Even if the wiring is performed as described above, a stable amplifying operation in which the high-frequency signal is influenced by the signal line can be realized.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の広帯域増幅回路の回路図である。FIG. 1 is a circuit diagram of a wideband amplifier circuit of the present invention.

【図2】本発明の広帯域増幅回路の利得周波数特性と広
帯域阻止インダクタの阻止周波数特性を示す特性図であ
る。
FIG. 2 is a characteristic diagram showing a gain frequency characteristic of a wideband amplifier circuit of the present invention and a blocking frequency characteristic of a wideband blocking inductor.

【図3】従来の広帯域増幅回路の回路図である。FIG. 3 is a circuit diagram of a conventional wide band amplifier circuit.

【符号の説明】[Explanation of symbols]

20 入力トランス 21 入力端子 22 出力トランス 23 出力端子 25 第1の増幅回路 26 第2の増幅回路 27a、27b 第1段目MESFET 28a、28b 第2段目MESFET 29a、29b 第3段目MESFET 30 ゲートバイアス線 32a、32b 広帯域阻止インダクタンス 20 input transformer 21 Input terminal 22 output transformer 23 output terminals 25 First amplifier circuit 26 Second amplifier circuit 27a, 27b 1st stage MESFET 28a, 28b Second stage MESFET 29a, 29b Third stage MESFET 30 gate bias line 32a, 32b Broadband blocking inductance

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 高周波信号が加えられる入力トランス
と、 前記高周波信号を取り出す出力トランスと、 前記入力トランスと出力トランス間にプッシュプル接続
され複数段のMESFETを有する第1の増幅回路と第
2の増幅回路とよりなり、 単層基板に前記複数段のMESFET、広帯域阻止イン
ダクタ及びチップ部品を取り付け、前記MESFETの
ゲートバイアス線を広帯域阻止インダクタの下を通過さ
せることを特徴とする広帯域増幅回路。
1. An input transformer to which a high-frequency signal is applied, an output transformer for extracting the high-frequency signal, a first amplifier circuit having a plurality of stages of MESFETs connected by push-pull between the input transformer and the output transformer, and a second amplifier circuit. A broadband amplifier circuit comprising an amplifier circuit, wherein a plurality of stages of MESFETs, a broadband blocking inductor and chip parts are mounted on a single layer substrate, and a gate bias line of the MESFET is passed under the broadband blocking inductor.
【請求項2】 高周波信号が加えられる入力トランス
と、 前記高周波信号を取り出す出力トランスと、 前記入力トランスと出力トランス間にプッシュプル接続
され複数段のMESFETを有する第1の増幅回路と第
2の増幅回路とよりなり、 前記第1の増幅回路と第2の増幅回路はゲート電極に高
周波入力信号が加えられソース電極を抵抗で結合し仮想
的に接地した上下1対の第1段目MESFETと、 ゲート電極が共通のゲートバイアス線でバイアス源に接
続され広帯域阻止インダクタを介して第1段目MESF
ETに夫々接続された上下1対の第2段目MESFET
とを備え、 単層基板に前記複数段のMESFET、広帯域阻止イン
ダクタおよびチップ部品を取り付け、前記第2段目ME
SFETのゲートバイアス線を第1段目MESFETと
第2段目MESFETを接続する広帯域阻止インダクタ
の下を通過させることを特徴とする広帯域増幅回路。
2. An input transformer to which a high frequency signal is applied, an output transformer for taking out the high frequency signal, a first amplifier circuit having a plurality of stages of MESFETs connected by push-pull between the input transformer and the output transformer, and a second transformer. The first and second amplifying circuits are composed of a pair of upper and lower first stage MESFETs in which a high-frequency input signal is applied to the gate electrode and the source electrode is coupled by a resistor and is virtually grounded. , The gate electrode is connected to the bias source by the common gate bias line, and the first stage MESF is connected via the broadband blocking inductor.
A pair of upper and lower second stage MESFETs connected to ET respectively
And a plurality of stages of MESFETs, a broadband blocking inductor and a chip component are attached to a single layer substrate, and the second stage ME is provided.
A wide band amplifier circuit, wherein a gate bias line of an SFET is passed under a wide band blocking inductor connecting a first stage MESFET and a second stage MESFET.
【請求項3】 単層基板はアルミ単板又はアルミナ或い
は窒化アルミであることを特徴とする請求項1または請
求項2記載の広帯域増幅回路。
3. The broadband amplifier circuit according to claim 1, wherein the single-layer substrate is a single aluminum plate, alumina, or aluminum nitride.
【請求項4】 前記第1の増幅回路と第2の増幅回路の
利得が一様な周波数帯域と広帯域阻止インダクタの阻止
周波数帯域が略同一であることを特徴とする請求項1ま
たは請求項2記載の広帯域増幅回路。
4. The frequency band in which the gains of the first amplifier circuit and the second amplifier circuit are uniform and the stop frequency band of the wideband stop inductor is substantially the same. The broadband amplifier circuit described.
JP2001188969A 2001-06-22 2001-06-22 Wide band amplification circuit Pending JP2003008363A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001188969A JP2003008363A (en) 2001-06-22 2001-06-22 Wide band amplification circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001188969A JP2003008363A (en) 2001-06-22 2001-06-22 Wide band amplification circuit

Publications (1)

Publication Number Publication Date
JP2003008363A true JP2003008363A (en) 2003-01-10

Family

ID=19027963

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001188969A Pending JP2003008363A (en) 2001-06-22 2001-06-22 Wide band amplification circuit

Country Status (1)

Country Link
JP (1) JP2003008363A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5528626B2 (en) * 2011-06-27 2014-06-25 三菱電機株式会社 Feed forward amplifier, feedback amplifier and broadband amplifier

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5528626B2 (en) * 2011-06-27 2014-06-25 三菱電機株式会社 Feed forward amplifier, feedback amplifier and broadband amplifier

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