JP2003008361A - Phase compensation amplification circuit, switched capacitor circuit using the same, and variable resistance amplifier circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable optimum phase compensation in the case of gain change and prevent distortion of output after amplification and oscillation. SOLUTION: This phase compensation amplification circuit is provided with a differential amplification stage 100 for differential amplification of first and second input signals which are complementary, and first and second output stages 101 and 102 which amplify first and second output signals, respectively, and perform phase compensation. The first and second output stages 101 and 102 have a first and a second phase compensation circuits 104 and 105, respectively, between output ends and input ends. The first and second phase compensation circuits are so constituted that the amount of phase compensation can be changed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase compensation amplifier circuit. Further, the present invention is configured using a phase compensation amplifier circuit, a sampling capacitor and a feedback capacitor, and a switched capacitor circuit capable of changing the gain of the phase compensation amplifier circuit by changing the ratio of the sampling capacitor and the feedback capacitor. It is about. Further, the present invention is configured by using a phase compensation amplifier circuit, a sampling (input) resistor and a feedback resistor, and a variable resistance amplifier circuit capable of changing the gain by changing the ratio of the sampling resistor and the feedback resistor. It is about.

[0002]

2. Description of the Related Art Recently, as an amplifier for changing the gain,
Phase compensation amplifier circuits have come to be used. In the conventional phase compensation amplifier circuit, a circuit as shown in FIG. 7 is used.

As shown in FIG. 7, this phase compensation amplifier circuit is a differential amplifier stage 20 for differentially amplifying complementary first and second input signals (input analog signals) Vin1 and Vin2.
0, and first and second output stages 201 and 202 for amplifying the complementary first and second output signals of the differential amplifying stage 200 and performing phase compensation, respectively.
Each of the first and second output stages 201 and 202 has a phase compensation circuit (feedback circuit for increasing the phase margin) 203 and 204 formed of a series circuit of a resistor and a capacitor between the output end and the input end. is doing.

The differential amplifier stage 200 includes a transistor Q25.
~ Q33. Transistors Q27, Q2
In No. 8, the drain is connected to the power supply terminal 211 (power supply voltage VDD), and the gates are connected to the signal input terminals 205 and 206 to which the first and second input signals (complementary input analog signals) Vin1 and Vin2 are applied, respectively. Has been done. The gates of the transistors Q25 and Q26 are respectively connected to the sources of the transistors Q27 and Q28,
The sources are connected together. Transistors Q32, Q
In the transistor 33, the drains of the transistors Q25 and Q26 are respectively connected, the sources are connected to the power supply terminal 211, and the gates are supplied with the bias voltage BIASP from the bias voltage terminal 209. Transistors Q29, Q
In the transistor 31, the drains are connected to the gates of the transistors Q25 and Q26, the sources are grounded, and the bias voltage BIASN is applied to the gates from the bias voltage terminal 210. The transistor Q30 is the transistor Q2
5, the source of Q26 is connected to the drain, the source is grounded, and the bias voltage BIASN is applied to the gate from the bias voltage terminal 210.

The output stage 201 includes transistors Q34 and Q34.
35 and a phase compensation circuit 203. In the transistor Q34, the gate is connected to the drain of the transistor Q25, the source is connected to the power supply terminal 211, and the drain is connected to the second signal output terminal 208 that outputs the second output signal Vout2. The transistor Q35 is
The drain is connected to the drain of the transistor Q34,
The source is grounded, and the bias voltage BIASN is applied to the gate from the bias voltage terminal 210. The phase compensation circuit 203 includes a phase compensation resistor RC3 and a capacitor Cc connected between the gate and drain of the transistor Q34.
It consists of 9 series circuits.

The output stage 202 includes transistors Q36 and Q.
37 and a phase compensation circuit 204. The gate of the transistor Q36 is connected to the drain of the transistor Q26, the source is connected to the power supply terminal 211, and the drain is connected to the first signal output terminal 207 that outputs the first output signal Vout1. Transistor Q37 is
The drain is connected to the drain of the transistor Q36,
The source is grounded, and the bias voltage BIASN is applied to the gate from the bias voltage terminal 210. The phase compensation circuit 204 includes a phase compensation resistor RC4 and a capacitance Cc connected between the gate and drain of the transistor Q36.
It consists of 10 series circuits.

Next, FIG. 8 shows a switched capacitor circuit constructed by using the phase compensation amplifier circuit shown in FIG. In FIG. 8, 1 is the phase compensation amplifier circuit shown in FIG. Cs is a sampling capacity, and the same capacity is provided at two locations. Cf is a feedback capacity, and the same capacity is provided in two places.
S1 to S9 are switches that switch the connection state of the sampling capacitance Cs and the feedback capacitance Cf at two locations. φ1 and φ2 are clocks for turning on and off the switches S1 to S9. Switches S1, S2
S4, S5, S8 and S9 are turned on / off by a clock φ1, and switches S3, S6 and S7 are turned on / off by a clock φ2. VDD is a power supply voltage applied to the power supply voltage terminal 2, VREF1 and VREF2 are reference voltages applied to the reference voltage terminals 3 and 4, respectively, and VCM.
Is a common feedback voltage applied to the common feedback voltage terminal 5, Vin11 and Vin21 are normal input and inverted input applied to the pair of input terminals 6 and 7, and Vout11 and Vout21 are positive terminals appearing at the pair of output terminals 8 and 9. The inverted output and the inverted output are shown.

Common feedback voltage terminal 5 described above
Is the normal output V which is the output of the phase compensation amplifier circuit 1 of FIG.
It is connected to a circuit that detects a common voltage of the out11 and the inverted output Vout21. This circuit is configured by division by resistors or capacitors controlled by clocks φ1 and φ2.

In the switched capacitor circuit shown in FIG. 8, the gain of the phase compensation amplifier circuit 1 can be set by the ratio of the sampling capacitance Cs and the feedback capacitance Cf,
The input signal is amplified in the phase compensation amplifier circuit 1 with the gain.

The phase compensation amplifier circuit shown in FIG. 7 can be applied to a resistance variable amplifier circuit as shown in FIG. Figure 5
In the figure, 1 is a phase compensation amplifier circuit. Rs is a sampling (input) resistance, which has the same resistance value provided at two locations. Rf is a feedback resistance,
The same resistance value is provided in two places. S22 ~
S25 is a switch for switching the connection state of the sampling resistor Rs and the feedback resistor Rf at two locations. φ3 is a clock for turning on / off the switches S22 to S25. Switches S22, S23, S
24 and S25 perform on / off operation of amplification with clock φ3. Vin12 and Vin22 are a pair of input terminals 11 and 1
2 shows the forward input and the inverted input given to Vou,
t12 and Vout22 indicate a normal output and an inverted output appearing at the pair of output terminals 13 and 14, respectively.

[0011]

In the switched capacitor circuit, the gain can be set as follows: Gain = Cs / Cf by the ratio of the sampling capacitance Cs and the feedback capacitance Cf. At this time, if gain control is performed from the outside using a serial binary code, the gain can be set for each binary code. 3 (a) and 3 (b)
2 schematically shows an example of a specific configuration of the sampling capacitance Cs and the feedback capacitance Cf that form the switched capacitor circuit. In FIG. 3, C is a unit capacity. S10 to S13 are switches controlled by the binary code SW4. S14 to S17 are switches controlled by the binary code SW5. S18, S1
Reference numeral 9 is a switch controlled by the binary code SW6. S20 and S21 are switches controlled by the binary code SW7.

When the sampling capacitance Cs and the unit capacitance C of the feedback capacitance Cf in FIGS. 3A and 3B are the same, a serial binary code SW4 from the outside is used.
Switches S10 to S13 controlled by the switch, switches S14 to S17 controlled by the binary code SW5, and switches S18 and S19 controlled by the binary code SW6.
And the switch S2 controlled by the binary code SW7
With 0 and S21, the gain can be changed from 0 dB to 12 dB in 6 dB steps. Switch S
The on / off operations of 10 to S21 will be described in detail in the embodiments described later.

As described above, when the gain is varied in 6 dB steps, in the conventional phase compensation amplifier circuit shown in FIG. 7, the phase margin varies greatly depending on the set gain, which causes distortion and oscillation of the output after amplification, and linearity up to a high gain. There is a problem that various characteristics cannot be obtained.

Further, in the variable resistance type amplifier circuit shown in FIG. 5, the gain can be set by gain = Rf / Rs by the ratio of the sampling (input) resistance Rs and the feedback resistance Rf.

In this variable resistance type amplifier circuit as well, when the conventional phase compensation amplifier circuit is used as in the switched capacitor circuit, the phase margins at the time of low gain and at the time of high gain are largely different, and the linear characteristic up to the high gain is obtained. There is a problem that you cannot get it.

Therefore, an object of the present invention is to perform optimum phase compensation when the gain is variable and to prevent distortion and oscillation of the output after amplification and a switched capacitor circuit using the same. And a variable resistance type amplifier circuit.

[0017]

SUMMARY OF THE INVENTION A phase compensation amplifier circuit of the present invention comprises a differential amplifier stage for differentially amplifying complementary first and second input signals, and a complementary first and second differential amplifier stage. Second
And a first and second output stage for respectively amplifying the output signals of the above and performing phase compensation, and the first and second output stages include first and second phase compensation between the output end and the input end. Each circuit is provided, and the first and second phase compensation circuits are configured so that the phase compensation amount can be changed.

According to this structure, since the phase compensation amounts of the first and second phase compensation circuits are changeable,
It is possible to optimally set the phase compensation amounts of the first and second phase compensation circuits for each set gain, and it is possible to perform the optimal phase compensation for each set gain. as a result,
The phase margin of the output after amplification can be optimized, the output can be stabilized, and linear characteristics up to high gain can be obtained. As a result, in the phase compensation amplifier circuit capable of variable gain, it is possible to stably maintain the phase margin of the output and linearly amplify up to a high gain without causing distortion or oscillation of the output.

In the above configuration, the first phase compensation circuit includes, for example, a series circuit of a first resistor and a first capacitor for phase compensation, and a second capacitor and a first switch for phase compensation. It comprises a series circuit and at least one first capacitance switch circuit connected in parallel with the first capacitance. The second phase compensation circuit includes, for example, a series circuit of a second resistor and a third capacitor for phase compensation and a series circuit of a fourth capacitor and a second switch for phase compensation. At least one second connected in parallel with the capacity of
And a capacitance switch circuit.

In the differential amplifier stage, for example, the drain is connected to the power supply terminal and the gates are connected to the first and second signal input terminals to which the first and second input signals are applied, respectively. Drains of the first and second transistors, and third and fourth transistors whose gates are respectively connected to the sources of the first and second transistors and whose sources are commonly connected, and drains of the third and fourth transistors Are connected to each other, the source is connected to the power supply terminal, the gates are supplied with the first bias voltage, and the drains are connected to the gates of the fifth and sixth transistors and the third and fourth transistors, respectively, and the source is Seventh and eighth transistors which are grounded and have a second bias voltage applied to their gates, and third and fourth transistors The drain is connected to the source,
The ninth transistor has a source grounded and a gate to which a second bias voltage is applied.

In the first output stage, for example, the drain of the third transistor is connected to the gate, the source is connected to the power supply terminal, and the drain is the second signal output terminal for outputting the second output signal. A tenth transistor connected to the node, a drain connected to the tenth transistor, a drain connected to the tenth transistor, a source grounded, and a gate to which a second bias voltage is applied; and a gate of the tenth transistor. A series circuit of a first resistor and a first capacitor for phase compensation connected between the drain and the drain, and a second capacitor for phase compensation and a series circuit of a first switch A first phase compensation circuit including at least one first capacitance switch circuit connected to the first capacitance switch circuit and a series circuit of the first resistor and the first capacitance and the first capacitance switch circuit. Constructed.

In the second output stage, for example, the drain is connected to the drain of the fourth transistor, the source is connected to the power supply terminal, and the drain is the first signal output terminal for outputting the first output signal. And a drain connected to the drain of the twelfth transistor, a source of the twelfth transistor is grounded, a gate is supplied with a second bias voltage, and a gate of the twelfth transistor. A series circuit of a second resistor and a third capacitor for phase compensation connected between the drain and a drain, and a series circuit of a fourth capacitor and a second switch for phase compensation, and a parallel circuit to the third capacitor. A second phase compensation circuit including at least one second capacitance switch circuit connected to the second capacitance switch circuit and a series circuit of the second resistor and the third capacitance, and the second capacitance switch circuit. Constructed.

The common bias stage applies the first bias voltage to the fifth and sixth transistors of the differential amplifier stage. The common feedback stage includes a fourteenth transistor having a source connected to a power supply terminal and a gate and a drain commonly connected, a fifteenth transistor having a source connected to the power supply terminal and a gate and a drain commonly connected, and A drain of the fourteenth transistor is connected to the drain and a drain of the fifteenth transistor is connected to the sixteenth transistor whose gate is connected to the common feedback voltage terminal;
A seventeenth transistor having a gate connected to the reference voltage terminal, a source commonly connected to the sixteenth transistor, a drain connected to the sources of the sixteenth and seventeenth transistors, a source grounded, and a second gate connected to the gate.
An eighteenth transistor to which a bias voltage of
It consists of a common feedback stabilizing capacitor having one end connected to the gate of the sixteenth transistor and the other end grounded. Then, from the drain of the 16th transistor to the 5th
And the first bias voltage is applied to the gate of the sixth transistor.

Further, the switched capacitor circuit of the present invention includes a differential amplifier stage for differentially amplifying complementary first and second input signals, and complementary first and second outputs of the differential amplifier stage. First and second output stages for amplifying signals and performing phase compensation, respectively, and the first and second output stages include first and second phase compensation circuits between an output end and an input end. A phase compensation amplifier circuit having the respective first and second phase compensation circuits configured so that the amount of phase compensation can be changed;
A sampling capacitor connected to the phase compensation amplifier circuit, a feedback capacitor connected to the phase compensation amplifier circuit, and a switch group for switching the connection state of the sampling capacitor and the feedback capacitor to the phase compensation amplifier circuit according to the clock are provided. .

According to this configuration, the phase compensation amounts of the first and second phase compensation circuits are changeable, so that
It is possible to optimally set the amount of phase compensation of the first and second phase compensation circuits for each gain set by the ratio of the sampling capacitance and the feedback capacitance, and it is possible to perform optimal phase compensation for each set gain. . As a result, the phase margin of the output after amplification can be optimized, the output can be stabilized, and linear characteristics up to high gain can be obtained. As a result, in the switched capacitor circuit that can change the gain, the output phase margin is kept stable,
High gain can be linearly amplified without causing output distortion or oscillation.

In the above configuration, the ratio of the sampling capacitance and the feedback capacitance is switched according to the binary code for gain setting, and the phase compensation amounts of the first and second phase compensation circuits are adjusted according to the binary code. Alternatively, the switching may be performed in conjunction with the ratio of the feedback capacity. With this, the phase compensation amount can be automatically switched when the gain is switched.

At this time, the first phase compensating circuit is, for example, a series circuit of a first resistor and a first capacitor for phase compensation, and a series circuit of a second capacitor and a first switch for phase compensation. And at least one first capacitance switch circuit connected in parallel with the first capacitance. Also,
The second phase compensating circuit includes, for example, a series circuit of a second resistor and a third capacitor for phase compensation, and a series circuit of a fourth capacitor for phase compensation and a second switch, and a third capacitor. And at least one second capacitance switch circuit connected in parallel. Then, the first and second switches are turned on and off according to the binary code.

The variable resistance type amplifier circuit of the present invention is
A differential amplification stage that differentially amplifies complementary first and second input signals, and first and second differential amplification stages that respectively amplify the complementary first and second output signals of the differential amplification stage and perform phase compensation. And two output stages, the first and second output stages have first and second phase compensation circuits respectively between the output end and the input end, and the first and second phase compensation circuits are provided. A phase compensation amplifier circuit configured to change the amount of phase compensation, a sampling resistor connected to the phase compensation amplifier circuit, a feedback resistor connected to the phase compensation amplifier circuit, and a sampling resistor and a feedback resistor for the phase compensation amplifier circuit. And a switch group for switching the connection state according to the clock.

According to this configuration, since the phase compensation amounts of the first and second phase compensation circuits are changeable,
The phase compensation amounts of the first and second phase compensation circuits can be optimally set for each gain set by the ratio of the sampling resistance and the feedback resistance, and the optimum phase compensation can be performed for each set gain. . As a result, the phase margin of the output after amplification can be optimized, the output can be stabilized, and linear characteristics up to high gain can be obtained. As a result, in the variable resistance type amplifier circuit capable of variable gain, it is possible to stably maintain the phase margin of the output and linearly amplify up to a high gain without causing distortion or oscillation of the output.

In the above configuration, the ratio of the sampling resistance and the feedback resistance is switched according to the binary code for gain setting, and the phase compensation amounts of the first and second phase compensation circuits are adjusted according to the binary code. Alternatively, the switching may be performed in conjunction with the ratio of the feedback resistance. With this, the phase compensation amount can be automatically switched when the gain is switched.

At this time, the first phase compensating circuit is, for example, a series circuit of a first resistor and a first capacitor for phase compensation, and a second circuit and a first switch for phase compensation. And at least one first capacitance switch circuit connected in parallel with the first capacitance. Also,
The second phase compensating circuit includes, for example, a series circuit of a second resistor and a third capacitor for phase compensation, and a series circuit of a fourth capacitor for phase compensation and a second switch, and a third capacitor. And at least one second capacitance switch circuit connected in parallel. Then, the first and second switches are turned on and off according to the binary code.

[0032]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described with reference to the drawings.

(First Embodiment) FIG. 1 shows a circuit diagram of an embodiment of a phase compensation amplifier circuit according to the present invention. The present embodiment is an example of a circuit when outputting a signal complementary to the common reference voltage VREF1. When the gain can be controlled by an external binary code (for example, a switched capacitor circuit), this phase compensation amplification circuit performs optimum phase compensation for each gain set by the binary code to be controlled, and thereby the output distortion It is possible to prevent oscillation and output a linear amplified output signal up to a high gain.

As shown in FIG. 1, this phase compensation amplification circuit includes a differential amplification stage 100 for differentially amplifying complementary first and second input signals, and a complementary first amplification stage 100 of the differential amplification stage 100.
And the first and second output stages 101, 1 for amplifying and outputting the respective second and second output signals and performing phase compensation
02 and a predetermined bias voltage (first
Common feedback stage 10 for providing a bias voltage of
3 and 3. First and second output stages 101,1
02 has first and second phase compensating circuits 104 and 105 between the output end and the input end, respectively.
The phase compensation circuits 104 and 105 are configured such that the amount of phase compensation can be changed.

The common feedback stage 103 described above is
The differential outputs Vout1 and Vout2 output from the first and second signal output terminals 121 and 122 are provided to output with reference to a reference voltage VREF1 given from the outside.

The common feedback stage 103 compares the output of the differential amplification stage 100 with the common feedback voltage VCM in order to match the output with the reference voltage VREF1. If the reference voltage VREF1 and the common feedback voltage VCM do not match, the bias (gate) voltage of the transistor Q14 is set so that the source potential of the transistor Q14 (current source) in FIG. 1 becomes the same as the source potential of the transistor Q15. Fluctuate. This bias voltage is fed back to the bias voltages of the transistors Q5 and Q6 which are the current sources of the differential amplifier 100, and when the differential input signals Vin1 and Vin2 are the same, the common voltage (reference voltage) of the differential output signals Vout1 and Vout2 is the same. It becomes the same as the reference voltage VREF1. As described above, the common feedback voltage VCM is obtained from the circuit that receives the differential output signals Vout1 and Vout2 as input and detects the common voltage of the differential output signals Vout1 and Vout2.

The first phase compensation circuit 104 includes a series circuit of a first resistor RC1 and a first capacitor Cc1 for phase compensation, and second capacitors Cc3, Cc5, Cc7 and a first transistor for phase compensation. (Switch) Q19, Q20,
It is composed of a series circuit of Q21 and is composed of at least one, for example, three first capacity switch circuits connected in parallel with the first capacity Cc1.

The second phase compensation circuit 105 includes a series circuit of a second resistor RC2 and a third capacitor Cc2 for phase compensation, and fourth capacitors Cc4, Cc6, Cc8 for phase compensation and a second transistor. (Switch) Q22, Q23,
It is composed of a series circuit of Q24 and at least one, for example, three second capacitance switch circuits connected in parallel with the third capacitance Cc2.

The differential amplifier stage 100 is composed of first to ninth transistors Q1 to Q9. The drains of the first and second transistors Q1 and Q2 are connected to the power supply terminal 123 (power supply voltage VDD), and the first and second input signals (differential input signals) Vin1 and Vin2 are applied thereto, respectively. Gates are connected to the second signal input terminals 117 and 118, respectively. The gates of the third and fourth transistors Q3 and Q4 are connected to the sources of the first and second transistors Q1 and Q2, respectively, and the sources are commonly connected. The fifth and sixth transistors Q5 and Q6 are connected to the third and fourth transistors Q3 and Q3, respectively.
The drain of Q4 is connected to the drain, the source is connected to the power supply terminal 123, and the gate is supplied with the first bias voltage from the common feedback stage 103.
The drains of the seventh and eighth transistors Q7 and Q8 are respectively connected to the gates of the third and fourth transistors Q3 and Q4, the sources are grounded, and the gates receive the second bias voltage BIAS from the bias voltage terminal 124. Given. The ninth transistor Q9 has third and fourth transistors.
The drains of the transistors Q3 and Q4 are connected to the source, the source is grounded, and the gate is connected to the bias voltage terminal 12
The second bias voltage BIAS is given from 4.

The first output stage 101 includes the tenth and first
It is composed of one transistor Q10 and Q11 and the first phase compensation circuit 104. Tenth transistor Q
The gate of the transistor 10 is connected to the drain of the third transistor Q3, the source is connected to the power supply terminal 123, and the drain is connected to the second signal output terminal 122 that outputs the second output signal Vout2. The eleventh transistor Q11 has a drain connected to the drain of the tenth transistor Q10, a source grounded, and a gate supplied with the second bias voltage BIAS from the bias voltage terminal 124.

The first phase compensation circuit 104 includes a first resistor RC1 for phase compensation and a first capacitance Cc connected between the gate and drain of the tenth transistor Q10.
1 series circuit and the second capacitors Cc3 and Cc for phase compensation
5, Cc7 and transistor (first switch) Q1
A first capacitor Cc composed of a series circuit of 9, Q20 and Q21
11 and at least one, for example, three first capacitance switch circuits connected in parallel. Transistor Q1
The gates of 9, Q20, and Q21 are switch terminals SW1,
They are connected to SW2 and SW3, respectively.

The second output stage 102 includes a twelfth and first
3 and a second phase compensation circuit 105. The twelfth transistor Q12 has a gate connected to the drain of the fourth transistor Q4, a source connected to the power supply terminal 123, and a drain connected to the first signal output terminal 121 for outputting the first output signal Vout1. ing. The thirteenth transistor Q13 has a first
The drain of the second transistor Q12 is connected to the drain, the source is grounded, and the gate is connected to the bias voltage terminal 12
The second bias voltage BIAS is given from 4. Second
Of the twelfth transistor Q12
A series circuit of a second resistor RC2 and a third capacitor Cc2 for phase compensation connected between the gate and drain of
Fourth capacitors Cc4, Cc6, Cc8 for phase compensation and transistors (second switches) Q22, Q23, Q2
4 series circuits and at least one second capacitance switch circuit connected in parallel with the third capacitance Cc2. The gates of the transistors Q22, Q23, Q24 are
The switch signals SW1, SW2 and SW3 are connected to switch terminals 125, 125 and 127, respectively.

The common feedback stage 103 has a fourteenth
To 18th transistors Q14 to Q18 and a common feedback stabilizing capacitor C1. In the fourteenth transistor, the source is connected to the power supply terminal 123, and the gate and drain are commonly connected. The fifteenth transistor Q15 has a source connected to the power supply terminal 123, and a gate and a drain commonly connected. First
The transistor Q16 of the sixth transistor is the fourteenth transistor Q1.
The drain is connected to the drain of the common feedback voltage terminal 120 (common feedback voltage VC
The gate is connected to M). The seventeenth transistor Q17 has a drain connected to the drain of the fifteenth transistor Q15 and a gate connected to the reference voltage terminal 119 (reference voltage VREF1).
The transistor Q16 and the source are commonly connected.
The eighteenth transistor Q18 has drains connected to the sources of the sixteenth and seventeenth transistors Q16 and Q17, the sources grounded, and the gate connected to the bias voltage terminal 1
A second bias voltage BIAS is applied from 24. The common feedback capacitor C1 has one end connected to the gate of the sixteenth transistor Q16 and the other end grounded. Then, from the drain of the sixteenth transistor Q16 of the common feedback stage 103, the differential amplification stage 100
The first bias voltage is applied to the gates of the fifth and sixth transistors Q5 and Q6.

According to the phase compensation amplifier circuit of this embodiment, by controlling the switch signals SW1, SW2, SW3 supplied to the switch terminals 125, 126, 127, the first and second phase compensation circuits 104, 105. Since the phase compensation amount can be changed, it is possible to optimally set the phase compensation amounts of the first and second phase compensation circuits 104 and 105 for each set gain, and for each set gain. Optimal phase compensation can be performed. As a result, even if the gain is changed, the phase margin of the output after amplification can be optimized, the output can be stabilized, and linear characteristics up to a high gain can be obtained. As a result, for example, when used in a switched capacitor circuit capable of variable gain, it is possible to stably maintain the phase margin of the output and linearly amplify up to a high gain without causing distortion or oscillation of the output.

FIG. 2 shows a circuit diagram of an embodiment of a switched capacitor circuit constructed by using the phase compensation amplifier circuit shown in FIG. In FIG. 2, reference numeral 1 is a phase compensation amplifier circuit. Cs is a sampling capacity, and the same capacity is provided at two locations. Cf is a feedback capacity, and the same capacity is provided in two places.
S1 to S9 are switches that switch the connection state of the sampling capacitance Cs and the feedback capacitance Cf at two locations. φ1 and φ2 are clocks for turning on and off the switches S1 to S9. Switches S1, S2
S4, S5, S8 and S9 are turned on / off by a clock φ1, and switches S3, S6 and S7 are turned on / off by a clock φ2. VDD is a power supply voltage applied to the power supply terminal 2, VREF1 and VREF2 are reference voltages applied to the reference voltage terminals 3 and 4, VCM is a common feedback voltage applied to the common feedback voltage terminal 5, and Vin11 and Vin21 are a pair of input terminals 6. , And 7 are the normal input and the inverted input (differential input), and Vout11 and Vout21 are the normal output and the inverted output (differential output) appearing at the pair of output terminals 8 and 9. SW1 to SW3 are switch elements 10
The switch signal given to (only one is shown in the figure) is shown.

The operation of the circuit shown in FIG. 2 will be described below. Figure 2
In the switched capacitor circuit of, when the switches S1, S2, S4, S5, S8 and S9 are turned on by the clock φ1, the normal input Vin to the sampling capacitor Cs
11. The charge input from the inverting input Vin21 is accumulated, and the clock φ2 is turned on after the clock φ1 is turned off, and the charge accumulated in the sampling capacitor Cs is
It is divided by the feedback capacitance Cf, and the gain of the amplifier is Cs / Cf.

FIG. 3A shows a specific example of the sampling capacitor Cs in FIG. Switches in which the unit capacitance C is connected in parallel and switches S10 and S1 for turning on / off the unit capacitance C by binary codes SW4 and SW5 from the outside.
1, S12, S13, S14, S15, S16, S17
Composed of and.

FIG. 3B shows a specific example of the feedback capacitance Cf in FIG. Switches S18 and S1 for turning on / off the unit capacitance C by a portion in which the unit capacitance C is connected in parallel and external binary codes SW6 and SW7.
9, S20, S21.

In FIG. 4, a non-inverting input Vin11 and an inverting input Vin are input to the switched capacitor circuit during operation.
21, switches S1 to S9 of the switched capacitor circuit
Clocks φ1 and φ2 for turning on and off, forward output Vo
It shows a timing diagram of ut11 and inverted output Vout21. In the figure, Vin is an input amplitude and Vout is an output amplitude.

The normal output Vout1 and the inverted output Vout2 shown in FIG. 4 are the binary code S shown in FIG.
W4, SW5 and the binary code SW shown in FIG. 3 (b)
6 and SW7, the gain of the output signal is expressed by the ratio of the sampling capacitance Cs and the feedback capacitance Cf: gain = Cs / Cf.

According to the binary code at this time, in this embodiment, for example, when the binary code SW4 is on, the binary code SW5 is off, and the binary code SW6 and the binary code SW7 are on, the gain is 0 dB. When the binary code SW4 and the binary code SW5 are on and the binary code SW6 and the binary code SW7 are on, the gain is 6 dB. Further, when the binary code SW4 and the binary code SW5 are on, the binary code SW6 is on, and the binary code SW7 is off, the gain is 12 dB. One of the binary code SW4 and the binary code SW5 is ON and the other is OF.
F, binary code SW6 and binary code SW
The gain is 6 dB even when one of 7 is on and the other is off.

Therefore, in this embodiment, the gain can be changed from 0 dB to 12 dB in 6 dB steps. When the gain is changed, the output has a maximum gain difference of 12 dB, and a large difference in phase margin occurs between 0 dB and 12 dB. In the conventional phase compensation amplifier circuit as shown in FIG. 7, when the gain is 12 dB, Output causes distortion and oscillation of the output more than when the gain is 0 dB, and linear characteristics cannot be obtained.

However, using the phase compensation amplifier circuit shown in FIG. 1, the switch signal SW supplied to the switch terminals 125 to 127 shown in FIG. 1 in synchronization with the serial binary code.
By controlling 1, SW2 and SW3, the optimum phase compensation capacitance is obtained for each gain, and the output is changed from 0 dB to 12 dB.
Even if it is changed to, output distortion or oscillation does not occur, and linear characteristics up to high gain can be obtained.

A more detailed description will be given. The gain is the switched capacitor circuit of FIG. 2, the Cs capacitance of FIG.
From the Cf capacity of (b), as described above, Cs and Cf
The ratio of can be set by a binary code. The output stages 100 and 101 input on / off signals from switch terminals 125 to 127 as switch signals SW1, SW2 and SW3 controlled by an external serial binary code for setting a gain, and the transistor Q1
0, Q11, Q12, Q13, Q14, Q15 on /
The capacitors Cc3, Cc4, Cc5, Cc6, Cc7, Cc8 for turning off and connected to each transistor for phase compensation
By switching the connection of, the optimum phase compensation is performed for each set gain, and the phase margin of the output after amplification is optimized to stabilize the output and obtain linear characteristics up to high gain. Try to solve.

According to the switched capacitor circuit of this embodiment, the phases of the first and second phase compensation circuits 104 and 105 are controlled by controlling the switch signals SW1, SW2 and SW3 supplied to the switch terminals 125 to 127. Since the compensation amount is changeable, the first and second phase compensation circuits 104, 1 are provided for each gain set by the ratio of the sampling capacitance Cs and the feedback capacitance Cf.
It is possible to optimally set the phase compensation amount of 05, and optimal phase compensation can be performed for each set gain. As a result, even if the gain is changed, the phase margin of the output after amplification can be optimized, the output can be stabilized, and linear characteristics up to a high gain can be obtained. by this,
In a switched-capacitor circuit capable of variable gain, the output phase margin can be kept stable, and high gain can be linearly amplified without causing distortion or oscillation of the output.
In addition, the phase compensation amount can be switched automatically in association with the gain switching.

(Second Embodiment) FIG. 5 shows an embodiment in which the phase compensation amplifier circuit of the present invention is applied to a resistance variable amplifier circuit. In FIG. 5, reference numeral 1 is a phase compensation amplifier circuit. Rs is a sampling (input) resistance, which has the same resistance value provided at two locations. Rf is a feedback resistor, and two resistors having the same resistance value are provided. S22 to S25 are switches that switch the connection state of the sampling resistor Rs and the feedback resistor Rf at two locations. φ3 is a switch S22-S2
This is a clock for turning on and off the signal 5. The switches S22, S23, S24, and S25 perform amplification on / off operation at the clock φ3. Vin12 and Vin22 indicate a normal input and an inverted input given to the pair of input terminals 11 and 12, and Vout12 and Vout22 indicate a normal output and an inverted output appearing on the pair of output terminals 13 and 14.

In this embodiment, when the clock φ3 is turned off after being turned on, the input signals input from the non-inverting input Vin12 and the inverting input Vin22 are amplified by the sampling resistor Rs and the feedback resistor Rf. , The output gain is gain = Rf / Rs, and the normal output Vout12 and the inverted output Vout22
Is output to. At this time, the phase compensation amplifier circuit shown in FIG. 1 can be applied as the complementary output amplifier. That is, when the gain is changed by changing the ratio of the sampling resistance Rs and the feedback resistance Rf, by changing the voltage applied to the switch terminals 125 to 127 as the switch signals SW1 to SW3, as in the above embodiment, Change the phase compensation amount.

According to the resistance variable amplifier circuit of this embodiment, by controlling the switch signals SW1, SW2, SW3 supplied to the switch terminals 125 to 127, the first and second phase compensation circuits 104 and 105 are controlled. Since the phase compensation amount can be changed, the sampling resistor R
It is possible to optimally set the phase compensation amounts of the first and second phase compensation circuits 104 and 105 for each gain set by the ratio of s and the feedback resistance Rf, and perform optimal phase compensation for each set gain. be able to. As a result, even if the gain is changed, the phase margin of the output after amplification can be optimized, the output can be stabilized, and linear characteristics up to a high gain can be obtained. As a result, in the variable resistance type amplifier circuit capable of variable gain, it is possible to stably maintain the phase margin of the output and linearly amplify up to a high gain without causing distortion or oscillation of the output.

(Third Embodiment) FIG. 6 shows an embodiment in which the phase compensation amplifier circuit of the present invention is applied to another resistance variable amplifier circuit. This embodiment differs from the embodiment shown in FIG. 5 in that two resistors R1 and switches S30 and S3 are provided.
1 is added. The resistor R1 is selectively connected in parallel to the sampling resistor Rs and the feedback resistor Rf, and its connection is switched by the switch S30,
It is designed to be performed in S31. And switch S3
The gain is switched by switching the connection between 0 and S31. The above gain switching can be controlled by a binary code.

In this embodiment, the gain when the resistor R1 is connected to the sampling resistor Rs side by the binary code is: gain = Rf / (Rs // R1), and the resistor R1 is connected to the feedback resistor Rf side. The gain at this time is gain = (Rf // R1) / Rs. The symbol Rs // R1 means a parallel combined resistance of the resistors Rs and R1, and Rf // R1 is the resistance Rf and R1.
Means the parallel combined resistance of.

At this time, if the conventional phase compensation amplifier circuit is used, there is a phase margin between the gain when the resistor R1 is connected to the sampling resistor Rs side and the gain when the resistor R1 is connected to the feedback resistor Rf side. Differences occur, and output distortion and oscillation occur. When the phase compensation amplifier circuit of this embodiment is used, optimum phase compensation can be performed even when the gain is changed, and output distortion and oscillation can be prevented. In addition, the phase compensation amount can be switched automatically in association with the gain switching.

[0062]

According to the phase compensation amplifier circuit of the present invention, since the phase compensation amounts of the first and second phase compensation circuits are changeable, the first and second phase compensation amplifiers are set for each set gain.
The phase compensation amount of the phase compensation circuit can be optimally set, and the optimal phase compensation can be performed for each set gain. As a result, the phase margin of the output after amplification can be optimized, the output can be stabilized, and linear characteristics up to high gain can be obtained. As a result, when the gain is variable, for example, when it is used in a switched capacitor circuit, the output phase margin can be stably maintained, and linear amplification up to a high gain can be performed without causing distortion or oscillation of the output.

Further, according to the switched capacitor circuit of the present invention, since the phase compensation amounts of the first and second phase compensation circuits are changeable, the gain set by the ratio of the sampling capacitance and the feedback capacitance is set. Every 1st
Also, the phase compensation amount of the second phase compensation circuit can be optimally set, and optimal phase compensation can be performed for each set gain. As a result, the phase margin of the output after amplification can be optimized, the output can be stabilized, and linear characteristics up to high gain can be obtained. As a result, in the switched capacitor circuit that can change the gain,
The output phase margin can be kept stable, and high gain can be linearly amplified without distortion or oscillation of the output.

Further, according to the variable resistance type amplifier circuit of the present invention, since the phase compensation amounts of the first and second phase compensation circuits can be changed, it is set by the ratio of the sampling resistance and the feedback resistance. The phase compensation amounts of the first and second phase compensation circuits can be optimally set for each gain, and the optimal phase compensation can be performed for each set gain. As a result, the phase margin of the output after amplification can be optimized, the output can be stabilized, and linear characteristics up to high gain can be obtained. As a result, in the variable resistance type amplifier circuit capable of variable gain, it is possible to stably maintain the phase margin of the output and linearly amplify up to a high gain without causing distortion or oscillation of the output.

Further, according to the present invention, when the gain of, for example, a switched capacitor circuit using the phase compensation amplifier circuit can be controlled by an external binary code, for each gain set by the binary code to be controlled,
By performing the optimum phase compensation, it is possible to prevent output distortion and oscillation and to output a linear amplified output signal up to a high gain.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a phase compensation amplifier circuit of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a switched capacitor circuit according to an embodiment of the present invention.

FIG. 3A is a circuit diagram showing a specific example of sampling capacitance of a switched capacitor circuit, and FIG. 3B is a circuit diagram showing a specific example of feedback capacitance of a switched capacitor circuit.

FIG. 4 is a timing diagram showing an input signal, an input clock signal, and an output signal showing the operation of the embodiment of the phase compensation amplifier circuit of the present invention.

FIG. 5 is a circuit diagram showing a configuration of an embodiment of a variable resistance type amplifier circuit of the present invention.

FIG. 6 is a circuit diagram showing a configuration of another embodiment of the variable resistance type amplifier circuit of the present invention.

FIG. 7 is a circuit diagram showing a conventional example of a phase compensation amplifier circuit.

FIG. 8 is a circuit diagram showing a configuration of a conventional switched capacitor circuit.

[Explanation of symbols]

Q1 to Q37 transistors Rc1, Rc4 resistance Cc1 to Cc10 capacity C1 Common feedback stabilizing capacity 1 Phase compensation amplifier circuit 2 power supply terminals 3,4 Reference voltage terminal 5 Common feedback voltage terminal 6,7 input terminals 8, 9 output terminals 10 switch terminals 11,12 input terminals 13, 14 output terminals 100 differential amplification stage 101 First output stage 102 Second output stage 103 Common feedback stage 104, 105 Phase compensation circuit 117, 118 signal input terminals 119 Reference voltage terminal 121, 122 signal output terminals 120 common feedback voltage terminal 123 Power terminal 124 Bias voltage terminal 125-127 switch terminals Cs sampling capacity Cf feedback capacity φ1, φ2, φ3 clock SW1 to SW3 switch signals SW4 to SW7 binary code C unit capacity S1 to S9 switches S10 to S17 switches S18-S21 switch S22-S29 switch S30, S31 switch Rs sampling resistor Rf feedback resistance R1 resistance

   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 5J066 AA01 AA12 CA21 CA54 FA19                       HA09 HA17 HA25 HA29 HA38                       HA39 MA11 MA19 ND01 ND14                       ND22 ND23 PD02 TA01 TA06                 5J090 AA01 AA12 CA21 CA54 FA19                       GN01 GN06 HA09 HA17 HA25                       HA29 HA38 HA39 MA11 MA19                       TA01 TA06

Claims (10)

[Claims] 1. A differential amplifier stage that differentially amplifies complementary first and second input signals, and amplifies the complementary first and second output signals of the differential amplifier stage and performs phase compensation. And a first and second output stage for performing the first and second output stages, the first and second output stages having first and second phase compensating circuits between an output end and an input end, respectively. A phase compensation amplifier circuit, wherein the second phase compensation circuit is configured so that the amount of phase compensation can be changed. 2. The first phase compensation circuit is a first phase compensation circuit.
At least one first capacitance switch circuit connected in parallel with the first capacitance, which is composed of a series circuit of a resistor and a first capacitance, and a series circuit of a second capacitance for phase compensation and a first switch. And the second phase compensation circuit includes a series circuit of a second resistor and a third capacitance for phase compensation,
The phase compensation amplifier circuit according to claim 1, comprising a series circuit of a fourth capacitor for phase compensation and a second switch, and at least one second capacitor switch circuit connected in parallel with the third capacitor. . 3. The differential amplifier stage has first and second drains connected to a power supply terminal and gates connected to first and second signal input terminals to which first and second input signals are applied, respectively. A second transistor and third and fourth transistors whose gates are connected to the sources of the first and second transistors, respectively, and sources are commonly connected, and drains of the third and fourth transistors. And a source connected to a power supply terminal and a gate to which a first bias voltage is applied, and fifth and sixth transistors, and the third and fourth transistors.
Drains of the transistors are connected to the respective gates, the sources are grounded, and the second bias voltage is applied to the gates of the seventh and eighth transistors, and the third transistor.
And a drain of the third transistor, the drain of which is connected to the source of the fourth transistor, the source of which is grounded and the gate of which is applied the second bias voltage. A gate connected to the source, a source connected to the power supply terminal, a drain connected to the second signal output terminal for outputting the second output signal, and a drain connected to the drain of the tenth transistor. A first gate connected to the source, the source grounded, and the gate supplied with the second bias voltage;
A first transistor, a series circuit of a first resistor and a first capacitor for phase compensation connected between the gate and drain of the tenth transistor, and a second capacitor and a first capacitor for phase compensation. Consisting of a series circuit of switches
At least one first capacitance switch circuit connected in parallel with the capacitance of the first capacitance switch circuit and the first resistance and the first capacitance series circuit and the first capacitance switch circuit.
And a gate connected to the drain of the fourth transistor, a source connected to the power supply terminal, and a drain that outputs the first output signal. A twelfth transistor connected to the output terminal; a thirteenth transistor having a drain connected to the drain of the twelfth transistor, a source grounded, and a gate to which the second bias voltage is applied; Second phase compensator connected between the gate and drain of the second transistor
At least one second capacitance switch circuit connected in parallel with the third capacitance, which is composed of a series circuit of a resistor and a third capacitance, and a series circuit of a fourth capacitance for phase compensation and a second switch. 2. The phase compensation amplifier circuit according to claim 1, wherein the second phase compensation circuit is constituted by a series circuit of the second resistor and the third capacitor and the second capacitance switch circuit. 4. A fourteenth transistor whose source is connected to a power supply terminal and whose gate and drain are commonly connected, and a fifteenth transistor whose source is connected to a power supply terminal and whose gate and drain are commonly connected, First
The first of which the drain is connected to the drain of the transistor 4 and the gate is connected to the common feedback voltage terminal
A sixth transistor, a drain connected to the drain of the fifteenth transistor, a gate connected to the reference voltage terminal, a seventeenth transistor in which the sixteenth transistor and the source are commonly connected, and the sixteenth transistor and the sixteenth transistor. The drain of the seventeenth transistor is connected to the source, the source is grounded, the gate of the eighteenth transistor is supplied with the second bias voltage, and the gate of the sixteenth transistor is connected at one end to the other end and grounded. And a common feedback stabilizing capacitor, and a first to a gate of the fifth and sixth transistors from the drain of the sixteenth transistor.
4. The phase compensation amplifier circuit according to claim 3, wherein said bias voltage is applied. 5. A differential amplifier stage that differentially amplifies complementary first and second input signals, and amplifies the complementary first and second output signals of the differential amplifier stage and performs phase compensation. And a first and second output stage for performing the first and second output stages, the first and second output stages having first and second phase compensating circuits between an output end and an input end, respectively. A phase compensation amplification circuit in which the amount of phase compensation is changeable in the second phase compensation circuit, a sampling capacitance connected to the phase compensation amplification circuit, a feedback capacitance connected to the phase compensation amplification circuit, and the phase A switched capacitor circuit comprising: a switch group that switches a connection state of the sampling capacitor and the feedback capacitor to a compensation amplifier circuit according to a clock. 6. The ratio of the sampling capacity and the feedback capacity is switched according to a binary code for gain setting, and the first capacity is controlled according to the binary code.
6. The switched capacitor circuit according to claim 5, wherein the phase compensation amount of the second phase compensation circuit is switched in conjunction with the ratio of the sampling capacitance and the feedback capacitance. 7. The first phase compensation circuit is a first phase compensation circuit.
At least one first capacitance switch circuit connected in parallel with the first capacitance, which is composed of a series circuit of a resistor and a first capacitance, and a series circuit of a second capacitance for phase compensation and a first switch. And the second phase compensation circuit includes a series circuit of a second resistor and a third capacitance for phase compensation,
It is composed of a series circuit of a fourth capacitor for phase compensation and a second switch, and is composed of at least one second capacitor switch circuit connected in parallel with the third capacitor, and is composed of the first circuit according to a binary code. 7. The switched capacitor circuit according to claim 6, wherein the second switch is turned on and off. 8. A differential amplifier stage that differentially amplifies complementary first and second input signals, and amplifies the complementary first and second output signals of the differential amplifier stage and performs phase compensation. And a first and second output stage for performing the first and second output stages, the first and second output stages having first and second phase compensating circuits between an output end and an input end, respectively. A phase compensation amplifier circuit in which the amount of phase compensation is changeable in the second phase compensation circuit, a sampling resistor connected to the phase compensation amplifier circuit, a feedback resistor connected to the phase compensation amplifier circuit, and the phase A variable resistance amplifier circuit comprising: a switch group that switches connection states of the sampling resistor and the feedback resistor to a compensation amplifier circuit according to a clock. 9. A ratio of a sampling resistance and a feedback resistance is switched according to a binary code for gain setting, and a first code is selected according to the binary code.
9. The variable resistance type amplifier circuit according to claim 8, wherein the phase compensation amount of the second phase compensation circuit is switched in association with the ratio of the sampling resistor and the feedback resistor. 10. The first phase compensation circuit comprises a series circuit of a first resistor and a first capacitor for phase compensation and a series circuit of a second capacitor and a first switch for phase compensation. At least one first connected in parallel with one capacitance
The second phase compensation circuit includes a series circuit of a second resistor and a third capacitance for phase compensation, and a series circuit of a fourth capacitance and a second switch for phase compensation. 10. The variable resistance type according to claim 9, further comprising: at least one second capacitance switch circuit connected in parallel with the third capacitance, wherein the first and second switches are interrupted according to a binary code. Amplifier circuit.