JP2003007067A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain stable operation with low power consumption and low voltage by generating no through current in read, unnecessitating electric power consumed in pre-charge, and performing small amplitude transmission and recycle of electric changes. SOLUTION: In a memory cell, a first load transistor P1 and a second load transistor P2 are connected to a first drive transistor N1 and a second drice transistor N2 in a flip-flop state. A first switch N3 controlled by a word line WL and a second switch N14 activated only in the case of write-in are connected in series to a first storage node V1, and a second switch N14 is connected in series between the first storage node V1 and the first drive transistor N1. When read, a current detecting impedance which varies by a signal potential of the first storage node is injected to a selected bit line pair BL,/BL.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor memory device such as a static random access memory (hereinafter referred to as SRAM) which operates at low voltage and low power consumption.

[0002]

2. Description of the Related Art In recent years, semiconductor integrated circuit devices such as SRAMs, which are driven at low voltage and operate at high speed, have been strongly desired with the increase in density and capacity of semiconductor integrated circuit devices.

A conventional semiconductor integrated circuit device will be described below with reference to the drawings.

FIG. 31 is a diagram showing a memory cell of a conventional SRAM. In FIG. 31, P1 is a first load transistor of one inverter, P2 is a second load transistor of the other inverter, N1 is a first drive transistor that drives one inverter, and N2 drives the other inverter. A second drive transistor, V1 is a first storage node that holds a signal potential of a memory cell, and V2 is a second storage node that holds a potential in a complementary relationship with the first storage node V1.
Storage node, WL is a word line for activating a memory cell in a specified row direction among memory cells arranged in an array, and BL is a memory cell arranged in an array. Is a bit line for controlling a write operation and a read operation with respect to a memory cell in the column (= column) direction designated by, and / BL is a bit line BL during a write operation.
The potential becomes complementary to the bit line BL during the read operation.
A bit complementary line which has the same potential as that of the bit line BL and which serves as a reference potential of the bit line BL, Vcc is a first power source for operating the memory cell, and Vss is a second potential which is a reference potential for operating the memory cell.
, N3 is a first switch that enables a write operation and a read operation to the first storage node V1 by the bit line BL only when the word line WL is activated,
N4 is a second switch, I, which enables the write operation and the read operation to the second storage node V2 by the bit complementary line / BL only when the word line WL is activated.
r is a read current generated when the signal potential of the first storage node V1 is read by the bit line BL, and Id is the first
Is a through current flowing from the first power supply Vcc to the second power supply Vss when the second drive transistor is activated when the signal potential of the storage node V1 is read. The first load transistor P1 and the second load transistor P2 paired therewith, the first drive transistor N1 and the second drive transistor N2 paired therewith are flip-flop connected, and the first storage node V1 and Two storage nodes V2
The potentials of and are always reversed and held. Vcc is 3V
And Vss is set to 0V.

The operation of the memory cell configured as described above will be described below. The write operation will be described. First, the word line WL is selected, the potential rises, and the first switch N3 and the second switch N4 are turned on. next,
A state in which the potential of the first power source Vcc is held is represented by "1", and a state in which the potential of the second power source Vss is held is represented by "0", so that "1" is stored in the first storage node V1. Second
If "0" is written in the storage node V2 of, the bit line BL is applied to the potential of the first power supply Vcc, and the bit complementary line / BL is applied to the potential of the second power supply Vss. At this time, the potential of the first storage node V1 is the first switch N3.
Which is the potential of the bit line BL applied through the first
Gradually approaches the potential of the power source Vcc. At the same time, the potential of the gate electrode of the second drive transistor N2, which is at the same potential as the first storage node V1, gradually rises, and when it exceeds the threshold voltage, the second drive transistor N2 is activated and the second drive transistor N2 is activated.
Storage node V2 gradually approaches the potential of the second power supply Vss.

Further, the potential of the second storage node V2 is the second
Approaching the power supply Vss of the first driving transistor N1 and falling below the threshold voltage of the first driving transistor N1.
Is turned off, and the potential of the first storage node V1 finally becomes the potential of the first power supply Vcc and is held.

On the contrary, when "0" is written in the first storage node V1 and "1" is written in the second storage node V2, the bit line BL is applied to the potential of the second power supply Vss, and the bit complementary line is applied. / BL is applied to the potential of the first power supply Vcc. next,
Contrary to the above, the potential of the second storage node V2 is held at the potential Vcc of the bit complementary line / BL.

Next, the read operation will be described. First, the word line WL is selected, the potential is raised, the first switch and the second switch are turned on, and the bit complementary line /
BL and bit line BL are selected and precharged together near the first power supply Vcc to raise the potential.

Next, it is assumed that "0" is held in the first storage node V1 and "1" is held in the second storage node V2.
Since the potential of the second storage node V2 of the first drive transistor N1 is activated high, the read current Ir flows from the bit line BL to the second power supply Vss through the first switch N3, and the bit line BL Is lower than the initial potential of the first power supply Vcc.

On the other hand, the second drive transistor N2 has a first
Since the storage node V1 of
No read current flows through the bit complementary line / BL. Therefore, the potential of the bit complementary line / BL is the initial first power supply Vcc.
It is not different from the potential of. The held data is read by detecting the potential difference between the bit line BL and the bit complementary line / BL at this time.

On the contrary, when "1" is held in the first storage node V1 and "0" is held in the second storage node V2,
Since a read current flows through the bit complementary line / BL and the potential of the bit complementary line / BL falls below the potential of the initial first power supply Vcc, a potential difference opposite to the above is found when comparing the potential with the bit line BL. Occurs and the reverse data is read.

[0012]

However, as described below, the conventional SRAM memory cell has two problems.

First, there is a problem that a through current Id is generated between the first power source Vcc and the second power source Vss during the read operation. For example, assume that "0" is held in the first storage node V1 and "1" is held in the second storage node. As described above, the word line is activated, and the bit line BL and the second bit line BL which are precharged near the first power source Vcc are activated.
Storage node V1 holding the potential of the power supply Vss of
When they are connected to each other, the potential is pulled to the potential Vcc of the bit line BL having a significantly large capacitance, and the potential of the first storage node V1 is greatly increased. Therefore, the first storage node V1
Since the potential of the gate electrode of the second drive transistor N2 connected to the threshold voltage exceeds the threshold voltage, the second drive transistor N2 that has been turned off is activated.
A through current Id flows. This through current Id has been a cause of increasing the power consumption of the memory cell.

Further, the flow of the through current Id causes the first power supply V held by the second storage node V2.
Since the potential of cc drops, the potential of the gate electrode of the first drive transistor N1 connected to the second storage node V2 also drops, so that the potential of the bit line BL rapidly drops and the necessary read current Ir becomes smaller. Therefore, the value of the read current Ir becomes close to the value of the noise current, and the read operation becomes unstable. This problem has become a major factor in hindering low-voltage driving because the noise margin cannot be secured as the first power supply voltage Vcc is set lower.

Secondly, after the read operation is completed, the potential difference generated between the bit complementary line / BL and the bit line BL connected to all the memory cells in the same row connected to the word line WL is restored. Pre-charge is required. Especially SRAM and ROM (= read only memory)
However, since the number of memory cells connected in parallel is large, there is a problem that the power consumption required for precharging becomes large.

The present invention solves the above conventional problems all at once, and in an SRAM or ROM having a large number of parallel bits,
Low power consumption is achieved by eliminating the power consumption for precharging, generating no shoot-through current in the memory cell, and performing small-amplitude transmission and reusing charges.
Moreover, it is an object of the present invention to enable a high speed operation at a low voltage.

[0017]

In order to achieve the above object, the present invention eliminates the power consumed for precharging by setting the bit line pair to the ground potential, so that the memory cell selected in the read operation can be provided. A current for impedance detection is injected to the memory cell, and a storage node holding a potential opposite to the potential of the source electrode of the drive transistor of the memory cell is cut off from the bit line to prevent a through current. In addition, in the write operation, the potential of the source line of the memory cell is set higher than the ground potential according to the write data.

Specifically, the first semiconductor integrated circuit device according to the present invention includes a memory cell array in which memory cells for storing data are arranged in a matrix and a memory cell arrayed in a row direction of the memory cell array. A row decoder that selects an address and a column circuit that selects a memory cell arranged in a column direction of the memory cell array by a column address are provided. The column circuit reads the row address and the column when reading data from the memory cell. It has a detection current injection means for injecting a current for detecting a data signal potential into a memory cell selected by an address.

According to the first semiconductor integrated circuit device, the detection current injection means injects a current for detecting the signal potential of the data into the selected memory cell when reading the data from the memory cell. By detecting the impedance of the memory cell, the data of the memory cell selected according to the value of the impedance can be determined.

Further, since the charges of the signal potential do not flow out from the memory cells activated in the read period and arranged in the row direction, it is not necessary to precharge the memory cells.

In the first semiconductor integrated circuit device, the detection current injection means is a sense amplifier for injecting a current for detecting impedance into the selected memory cell during a data read period for reading data from the memory cell. Preferably there is.

As described above, since the detection current injection means is the sense amplifier for injecting the current for detecting the impedance into the selected memory cell, the signal potential of the selected memory cell is surely obtained as the impedance difference. Can be detected. Therefore, the read operation can be performed at high speed and reliably.

In the first semiconductor integrated circuit device, when the detection current injection means is a sense amplifier, the sense amplifier is injected into the selected memory cell after reading the data from the selected memory cell. It is preferable to discard the current.

As described above, the sense amplifier discards the current for detecting the impedance injected into the selected memory cell after reading the data from the memory cell, and thus reads the potential of the selected memory cell. Since the previous state can be restored, the next read operation can be guaranteed.

In the first semiconductor integrated circuit device, when the detection current injection means is a sense amplifier, the sense amplifier is an inverter including a transistor pair of a first conductivity type and a transistor pair of a second conductivity type. A circuit is flip-flop connected, and a source electrode pair of the first conductivity type transistor pair is an input pair to which data of the memory cell whose address is specified is input,
The common contact of the source electrode pair of the second conductivity type transistor pair is connected to the power supply via the second conductivity type first transistor controlled by a predetermined activation signal, and the output pair of the inverter circuit is The first conductivity type first transistor and the first conductivity type second transistor controlled by the activation signal are respectively connected to the power source, and the second conductivity type is connected during the data read period. It is preferable that the first transistor and the first and second conductivity type first and second transistors are not activated at the same time.

As described above, since the first transistor of the second conductivity type and the first and second transistors of the first conductivity type are not activated at the same time, the activation signal of the sense amplifier is turned on. Causes a potential difference that detects the difference in impedance characteristics of the input pair, and during the period when the activation signal is off, the flip-flop circuit is activated to amplify the detected potential difference and to inject the injected charge. Can be discarded.

In the first semiconductor integrated circuit device, the memory cell array has a first control line and a second control line for controlling the memory cells arranged in the column direction, and the column circuit is A first potential is applied to the first control line and the second control line when reading data from the memory cell, and the first control line is applied to the first control line when writing data to the memory cell. It is preferable to have a bit line control circuit that applies the second potential or the second potential and the third potential to the second control line.

As described above, the memory cell array includes the first control line and the second control line for controlling the memory cells arranged in the column direction.
Control line, and applies the first potential to the first control line and the second control line when reading data from the memory cell, the first control line and the second control line The control line can be at ground potential. In addition, a bit line control circuit which applies a first potential or a second potential to the first control line and a third potential to the second control line when writing data to the memory cell Since it has, the low data or the high data can be applied to the first control line, and the control potential for controlling the writing can be applied to the second control line. The potential can be written surely.

In the first semiconductor integrated circuit device, when the column circuit has a bit line control circuit, the memory cell is a first load transistor connected to a first power supply, and the first load transistor is a first load transistor. Second paired with the load transistor of
Load transistor, a first drive transistor connected to a second power source, and a second drive transistor paired with the first drive transistor are flip-flop connected, and connected to the first load transistor. A first storage node that holds a signal potential and a second storage node that is connected to the second load transistor and holds a signal potential complementary to the first storage node;
Connected in series between the first storage line and the first control line, is controlled by a third control line, and one source / drain electrode is connected to the first control line. Controlled by the switch transistor and the second control line, one source / drain electrode is connected to the first storage node, and the other source / drain electrode is the other source / drain of the first switch transistor. A second switch transistor connected to the electrode, wherein the second switch transistor is preferably connected in series between the first storage node and the first drive transistor.

As described above, since the second switch transistor is connected in series between the first storage node and the first drive transistor, the first storage node is cut off from the first control line. Therefore, the precharge potential can be set to the ground potential, and the potential of the first storage node does not rise even if the first control line is activated during the read period. As a result, a through current does not flow in the memory cell, so that low voltage driving is possible.

Furthermore, in this case, the threshold voltage of the second switch transistor is lower than the threshold voltage of any of the first drive transistor, the second drive transistor and the first switch transistor. Is preferably set as follows.

As described above, since the threshold voltage of the second switch transistor activated by the second control line during the write operation is set to be low, the first voltage applied to the second control line is set. Since the potential higher than the potential of 3 is unnecessary, the power consumption can be further reduced.

Further, in this case, the size of the second load transistor is the same as that of the first load transistor and the second load transistor.
It is preferable that the driving transistor is set to be smaller than any size of the driving transistor.

As described above, since the size of the second load transistor controlled by the potential of the first storage node is set to be small, the operating speed of the second load transistor is increased, so that the second load transistor operates in the write operation. The high data “1” can be written into the storage node of 1 quickly, and the access time can be shortened.

Further, in this case, the memory cell is connected in parallel with the second drive transistor between the second storage node and the second power supply, and is connected to the first switch transistor. It is preferable to further include a third switch transistor which is controlled by a potential at a connection point with the second switch transistor.

With this configuration, the third switch transistor controlled by the first control line is connected between the second storage node and the second power supply at the ground potential, so that the third switch is connected. Since the transistor will start operating before the second drive transistor controlled by the first storage node, the second storage node will quickly approach the reference potential, and the access time will be shortened. You can

Further, in this case, it is preferable that the first power source is stepped down by a step-down circuit.

In this way, the potential applied to the memory cell becomes lower than the potential of the first power supply, which is the normal power supply potential, so that the power consumption of the memory cell can be reduced. Further, since the potential of the source line is relatively increased, the ability of the drive transistor to latch the signal potential is reduced, so that the writing operation is accelerated.

In this case, it is preferable that the step-down circuit is a memory cell in which the conductivity types of all the transistors forming the memory cell are inverted.

In this way, since the memory cells whose conductivity type is inverted and the memory cells which are not inverted are connected in series, the potential of the first power supply, which is the normal power supply potential, is applied. , Two memory cells connected in series can be stably driven. Moreover, since two memory cells connected in series can be driven by the potential of the first power supply which is a normal power supply potential, the power consumption of each memory cell can be reduced.

In this case, the number of memory cells connected to the third control line becomes larger than the number of memory cells connected to the first control line and the second control line. It is preferable.

With this arrangement, the number of memory cells connected to the third control line increases and the number of memory cells connected to the first and second control line pairs decreases, so that the third control line is connected. Since the number of lines is reduced, the row address can be decoded faster, and the access time can be shortened, which enables high-speed operation. In the first semiconductor integrated circuit device, when the column circuit has a bit line control circuit, the memory cell includes a first load transistor connected to a first power supply, and the first load transistor. A second load transistor paired with the first drive transistor connected to the second power source, and a second drive transistor paired with the first drive transistor are flip-flop connected, Storage node connected to the second load transistor and holding a signal potential, and a second storage node connected to the second load transistor and holding a signal potential complementary to the first storage node. Is connected in series between the second storage node and the first control line, is controlled by the third control line, and one source / drain electrode is the first control line. A first switch transistor being connected to the control line, is controlled by said second control line, one source /
A second drain electrode connected to the second storage node and the other source / drain electrode connected to the other source / drain electrode of the first switch transistor;
Switch transistor, and a third switch transistor connected in series between the first switch transistor and the second power supply and controlled by the first storage node. preferable.

Thus, controlled by the second control line, one source / drain electrode is connected to the second storage node and the other source / drain electrode is the other source / drain electrode of the first switch transistor. And a third switch transistor connected in series between the first switch transistor and the second power supply and controlled by the first storage node. Therefore, the first storage node is cut off from the first control line, so that the precharge potential can be set to the ground potential and the first control line is activated even when the first control line is activated at the time of reading. The potential of the storage node does not rise. As a result, a through current does not flow in the memory cell, so that low voltage driving is possible. Further, since the switch transistors are not connected in series in the inverter, the noise margin can be increased accordingly.

In this case, it is preferable that the size of the first load transistor is set smaller than the size of the second load transistor.

As described above, since the size of the first load transistor controlled by the potential of the second storage node is set to be small, the operation speed of the first load transistor is increased, so that the write operation is performed. At the second
The high data "1" can be written into the storage node of 1 quickly, and the access time can be shortened.

Further, in this case, the memory cell is connected in parallel with the first drive transistor between the first storage node and the second power supply, and is connected to the first switch transistor. It is preferable to further include a fourth switch transistor that is controlled by the potential of the connection point with the second switch transistor.

In this way, the fourth switch transistor activated by the first control line and controlled by the potential at the connection point of the first and second switch transistors is connected to the first storage node and the ground potential. The fourth switch transistor is connected to the second power source
Since the operation starts before the first drive transistor controlled by the first storage node, the first storage node quickly approaches the reference potential, and the access time can be shortened.

Further, in this case, it is preferable that the first power source is stepped down by a step-down circuit.

In this way, the potential applied to the memory cell becomes lower than the potential of the first power supply which is the normal power supply potential, so that the power consumption of the memory cell can be reduced. Further, since the potential of the source line is relatively increased, the ability of the drive transistor to latch the signal potential is reduced, so that the writing operation is accelerated.

In this case, it is preferable that the step-down circuit is a memory cell in which the conductivity types of all the transistors forming the memory cell are inverted.

In this way, the memory cells whose conductivity types are inverted and the memory cells which are not inverted are connected in series, so that the potential of the first power supply, which is a normal power supply potential, is applied. , Two memory cells connected in series can be stably driven. Further, since two memory cells connected in series can be driven by the potential of the first power supply which is a normal power supply potential, the power consumption of each memory cell can be reduced.

In this case, the number of memory cells connected to the third control line may be larger than the number of memory cells connected to the first control line and the second control line. preferable.

In this way, the number of memory cells connected to the third control line increases and the number of memory cells connected to the second and third control line pairs decreases, so that the third control line Since the number of lines is reduced, the row address can be decoded faster. As a result, the access time can be shortened, and high-speed operation is possible.

A second semiconductor integrated circuit device according to the present invention is intended for a semiconductor integrated circuit device provided with a memory cell array in which memory cells are arranged in rows and columns, wherein the memory cells have gate electrodes and drain electrodes. And a cross-coupled transistor pair including a first transistor and a second transistor, at the time of writing data to the memory cell, at least a gate of a transistor in the on-state of the transistor pair. A source potential changing means for changing the potential of the source electrode of the transistor is provided so that the absolute value of the difference between the sources becomes small.

According to the second semiconductor integrated circuit device, when writing data to the memory cell, the absolute value of the difference between the gate-source voltage of at least the transistor in the on-state of the transistor pair becomes small. Since the source potential changing means for changing the potential of the source electrode of the transistor is provided in the transistor, at least the transistor in the on-state of the transistor pair is in the off-state than the other transistors, so that the signal potential latch Ability decreases.

In the second semiconductor integrated circuit device, it is preferable that the transistor pair share a source electrode. By doing so, the potential of the source electrode can be easily and surely changed.

In the second semiconductor integrated circuit device, it is preferable that the source electrode of the transistor pair is separated. By doing so, the latching capability of the signal potential can be reduced according to the write data.

In this case, the source potential changing means is
It is preferable that the potential of the source electrode of the transistor is changed so that the absolute value of the difference between the gate-source voltage of the transistor on the side of the transistor in the off state becomes larger.

As described above, the source potential changing means changes the potential of the source electrode of the transistor so that the absolute value of the difference between the gate-source voltage of the transistor on the side in which the transistor pair is in the off state becomes large. To let
Since at least the transistor in the off state of the transistor pair is in the on state than the other transistors, the ability to latch the signal potential is reduced. As a result, the balance of the signal potentials of the storage node pair is quickly lost, so that the write operation can be performed at high speed.

Further, in this case, the first transistor in the memory cell is a first drive transistor whose drain electrode is connected to the first storage node,
The second transistor is a second drive transistor whose drain electrode is connected to a second storage node that is complementary to the first storage node, and the memory cell is
A first load transistor having a gate electrode and a source electrode cross-coupled with each other, one source / drain electrode connected to a first power supply, and the other source / drain electrode connected to the first storage node; , One source / drain electrode is connected to the first power supply and the other source / drain electrode
A second drain electrode connected to the second storage node;
Load source transistor, the source potential changing means is configured to, when the signal potential opposite to the source / drain electrode of the first driving transistor is written to the first storage node, supply the third power source. A ground line control potential and a potential of the second power source to the fourth power source, and write the same signal potential as the source / drain electrode of the first drive transistor to the first memory node. In this case, the ground line control circuit preferably applies the potential of the second power source to the third power source and applies the ground line control potential to the fourth power source.

In this way, the source potential changing means is the ground line control circuit, and when writing the signal potential opposite to the source / drain electrode of the first drive transistor to the first storage node, the third potential is applied to the third storage node. When the ground line control potential is applied to the second power supply and the potential of the second power supply is applied to the fourth power supply, and the same signal potential as the source / drain electrode of the first drive transistor is written to the first storage node Since the potential of the second power source is applied to the third power source and the ground line control potential is applied to the fourth power source, the ability to latch the signal potential of the first or second storage node is surely lowered. Can be made.

In the second semiconductor integrated circuit device, the memory cell array has a first control line and a second control line for controlling the memory cells arranged in the column direction, and data is read from the memory cells. At this time, a first potential is applied to the first control line and the second control line, and when writing data in the memory cell, the first potential or the second potential is applied to the first control line. It is preferable to include a bit line control circuit that applies a potential and that applies a third potential to the second control line.

As described above, the memory cell array includes the first control line and the second control line for controlling the memory cells arranged in the column direction.
Control line, and applies the first potential to the first control line and the second control line when reading data from the memory cell, the first control line and the second control line The control line can be at ground potential. In addition, a bit line control circuit which applies a first potential or a second potential to the first control line and a third potential to the second control line when writing data to the memory cell Since it has, the low data or the high data can be applied to the first control line, and the control potential for controlling the writing can be applied to the second control line. The potential can be written surely.

When the second semiconductor integrated circuit device includes a bit line control circuit, the memory cell has the first
Connected in series between the first storage line and the first control line, is controlled by a third control line, and one source / drain electrode is connected to the first control line. Controlled by the switch transistor and the second control line, one source / drain electrode is connected to the first storage node, and the other source / drain electrode is the other source / drain of the first switch transistor. A second switch transistor connected to the electrode, wherein the second switch transistor is preferably connected in series between the first storage node and the first drive transistor.

As described above, since the second switch transistor is connected in series between the first storage node and the first drive transistor, the first storage node is cut off from the first control line. Therefore, the precharge potential can be set to the ground potential, and the potential of the first storage node does not rise even if the first control line is activated during the read period. As a result, a through current does not flow in the memory cell, so that low voltage driving is possible.

In this case, it is preferable that the memory cells adjacent to each other are commonly connected to the third power source and the fourth power source.

As described above, since the memory cells adjacent to each other share the third power supply line and the fourth power supply line, it is possible to reduce the number of these power supply lines. Area is not sacrificed by these power lines.

In this case, the threshold voltage of the second switch transistor may be lower than the threshold voltage of any of the first drive transistor, the second drive transistor and the first switch transistor. Is preferably set to.

As described above, since the threshold voltage of the second switch transistor activated by the second control line is set to be low during the write operation, the second
Since the potential higher than the third potential applied to the control line is unnecessary, the power consumption can be further reduced.

In this case, it is preferable that the size of the second load transistor is set to be smaller than the size of either the first load transistor or the second drive transistor.

As described above, since the size of the second load transistor controlled by the potential of the first storage node is set small, the operating speed of the second load transistor is increased, so that the second load transistor operates in the write operation. The high data “1” can be written into the storage node of 1 quickly, and the access time can be shortened.

Further, in this case, the second control line is arranged in parallel with the third control line, and the power supply line connected to the fourth power supply and the first control line are separated from each other. It is preferable to form a bit line pair of the memory cell for decoding a column address.

With this arrangement, the second control line, which is a control line for writing, is arranged in parallel with the third control line, so that more memory cells are arranged in the column direction than in the row direction. In the case of a memory cell array in which the second control line is connected, the number of memory cells connected to the second control line is reduced, so that the capacity of the second control line is reduced and the power consumption during the write operation is reduced. can do.

Further, since the memory cell to be written is limited to the memory cell where the first control line and the second control line intersect, erroneous writing can be prevented.

In this case, it is preferable that the second control line be shared by a plurality of memory cells in the same column.

As described above, since the second control line is shared by a plurality of memory cells in the same column, the number of second control lines is reduced, so that the element area on the semiconductor substrate is the second. Not sacrificed by the control line.

Further, in this case, the memory cell is connected between the second storage node and the fourth power source in parallel with the second drive transistor, and is connected to the first switch transistor. It is preferable to further include a third switch transistor which is controlled by a potential at a connection point with the second switch transistor.

With this configuration, the third switch transistor controlled by the first control line is connected between the second storage node and the second power supply at the ground potential, so that the third switch is connected. Since the transistor starts operating before the second drive transistor controlled by the first storage node, the second storage node quickly approaches the reference potential, and the access time can be shortened.

Further, in this case, it is preferable that the first power source is stepped down by a step-down circuit.

In this way, the potential applied to the memory cell becomes lower than the potential of the first power supply, which is the normal power supply potential, so that the power consumption of the memory cell can be reduced. Further, since the potential of the source line is relatively increased, the ability of the drive transistor to latch the signal potential is reduced, so that the writing operation is accelerated.

In this case, it is preferable that the step-down circuit is a memory cell in which the conductivity types of all the transistors forming the memory cell are inverted.

In this way, since the memory cells whose conductivity types are inverted and the memory cells which are not inverted are connected in series, the normal power source potential and the potential of the first power source are applied. , Two memory cells connected in series can be stably driven. Further, since two memory cells connected in series can be driven by the potential of the first power supply which is a normal power supply potential, the power consumption of each memory cell can be reduced.

In this case, the number of memory cells connected to the third control line is the same as that of the first control line and the second control line.
It is preferable that the number is larger than the number of memory cells connected to the control line.

In this way, the number of memory cells connected to the third control line increases and the number of memory cells connected to the first and second control line pairs decreases, so that the third control line Since the number of lines is reduced, the row address can be decoded faster. As a result, the access time can be shortened, and high-speed operation is possible.

In the case where the second semiconductor integrated circuit device includes a bit line control circuit, the memory cell has the second line.
Connected in series between the first storage line and the first control line, controlled by the third control line, and one source / drain electrode connected to the first control line. One switch transistor and one of the source / drain electrodes are controlled by the second control line.
A second switch transistor connected to the storage node of the first switch transistor and the other source / drain electrode connected to the other source / drain electrode of the first switch transistor, the first switch transistor, and the third power supply. And a third switch transistor which is connected in series between and and is controlled by the first storage node.

As described above, controlled by the second control line, one source / drain electrode is connected to the second storage node and the other source / drain electrode is the other source / drain electrode of the first switch transistor. And a third switch transistor connected in series between the first switch transistor and the second power supply and controlled by the first storage node. Therefore, the first storage node is cut off from the first control line, so that the precharge potential can be set to the ground potential and the first control line is activated even when the first control line is activated at the time of reading. The potential of the storage node does not rise. As a result, a through current does not flow in the memory cell, so that low voltage driving is possible. Furthermore, since the switch transistors are not connected in series in the inverter, the noise margin can be increased accordingly.

In this case, it is preferable that the memory cells adjacent to each other are commonly connected to the third power source and the fourth power source.

As described above, since the memory cells adjacent to each other share the third power supply line and the fourth power supply line, the number of these power supply lines is reduced, so that the elements on the semiconductor substrate are reduced. Area is not sacrificed by these power lines.

Further, in this case, it is preferable that the size of the first load transistor is set to be smaller than the size of the second load transistor.

As described above, since the size of the first load transistor controlled by the potential of the second storage node is set to be small, the operating speed of the first load transistor is increased, so that the first load transistor operates in the write operation. The high data "1" can be written into the second storage node quickly, and the access time can be shortened.

Further, in this case, the second control line is arranged in parallel with the third control line, and the power supply line connected to the fourth power supply and the first control line are separated from each other. It is preferable to form a bit line pair of the memory cell for decoding a column address.

As described above, since the second control line, which is a control line for writing, is arranged in parallel with the third control line, more memory cells are arranged in the column direction than in the row direction. In case of connected memory cell array,
Since the number of memory cells connected to the second control line is reduced, the capacity of the second control line is reduced and the power consumption during the write operation can be reduced.

Further, since the memory cell to be written is limited to the memory cell where the second control line and the first control line intersect, erroneous writing can be prevented.

In this case, it is preferable that the second control line is shared by the memory cells in the same column.

As described above, since the second control line is shared by a plurality of memory cells in the same column, the number of second control lines is reduced, so that the element area on the semiconductor substrate is the second. Not sacrificed by the control line.

Further, in this case, the memory cell is connected in parallel with the first drive transistor between the first storage node and the third power supply, and is connected to the first switch transistor. It is preferable to further include a fourth switch transistor that is controlled by the potential of the connection point with the second switch transistor.

In this way, the fourth switch transistor activated by the first control line and controlled by the potential at the connection point of the first and second switch transistors is connected to the first storage node and the ground potential. The fourth switch transistor is connected to the second power source
Since the operation starts before the first drive transistor controlled by the storage node of No. 1, the first storage node quickly approaches the reference potential, and the access time can be shortened.

Further, in this case, it is preferable that the first power source is stepped down by a step-down circuit.

In this way, the potential applied to the memory cell becomes lower than the potential of the first power supply, which is the normal power supply potential, so that the power consumption of the memory cell can be reduced. Further, since the potential of the source line is relatively increased, the ability of the drive transistor to latch the signal potential is reduced, so that the writing operation is accelerated.

In this case, it is preferable that in the step-down circuit, the conductivity types of all the transistors forming the memory cell are inverted.

In this way, since the memory cells whose conductivity type is inverted and the memory cells which are not inverted are connected in series, the potential of the first power supply, which is the normal power supply potential, is applied. , Two memory cells connected in series can be stably driven. Moreover, since two memory cells connected in series can be driven by the potential of the first power supply which is a normal power supply potential, the power consumption of each memory cell can be reduced.

In this case, the number of memory cells connected to the third control line is the same as that of the first control line and the second control line.
It is preferable that the number is larger than the number of memory cells connected to the control line.

In this way, the number of memory cells connected to the third control line increases and the number of memory cells connected to the first and second control line pairs decreases, so that the third control line Since the number of lines is reduced, the row address can be decoded faster. As a result, the access time can be shortened, and high-speed operation is possible.

In the second semiconductor integrated circuit device, the memory cell array controls the first control line and the second control line for controlling the memory cells arranged in the column direction and the memory cells arranged in the row direction. A third control line, in the memory cell, the first transistor is a first drive transistor whose drain electrode is connected to a first storage node, and the second transistor is a drain. An electrode is a second drive transistor connected to a second storage node which is in a complementary relationship with the first storage node, and the memory cell has a gate electrode and a source electrode which are cross-coupled to each other. A first load transistor having a source / drain electrode connected to a first power supply and the other source / drain electrode connected to the first storage node; A second load transistor having a source / drain electrode connected to a first power supply and the other source / drain electrode connected to the second storage node, the first storage node and the second load transistor being connected to the second storage node. A first switch transistor connected in series with the first control line, controlled by the third control line, and having one source / drain electrode connected to the first control line; A second switch transistor controlled by the second storage node and having one source / drain electrode connected to the other source / drain electrode of the first switch transistor; the second storage node; A third switch transistor connected in series with a second control line and controlled by the first storage node; and controlled by the first control line, A fourth switch transistor having a source / drain electrode connected to one source / drain electrode of the third switch transistor and the other source / drain electrode connected to the second control line; The second switch transistor is connected in series between the first storage node and the first drive transistor, and the third switch transistor is connected between the second storage node and the second drive transistor. It is preferable that they are connected in series.

As described above, since the source / drain electrode of one of the source / drain electrodes is controlled by the second storage node and is connected to the source / drain electrode of the first switch transistor, Since the first storage node is cut off from the first control line, the precharge potential can be set to the ground potential, and even if the first control line is activated during the read period, the potential of the first storage node Will not rise. As a result, a through current does not flow in the memory cell at the time of reading, so that low voltage driving is possible.

In this case, the memory cell arrays are connected in series with each other, and include a first memory cell and a second memory cell in which the conductivity type of each corresponding transistor in the first memory cell is inverted. It is preferable that the first memory cell and the second memory cell are applied to a potential approximately half the potential of the first power supply.

In this way, the memory cells whose conductivity types are inverted and the memory cells which are not inverted are connected in series, so that the potential of the first power supply, which is the normal power supply potential, is applied. Since two memory cells connected in series can be stably driven, the power consumption of each memory cell can be reduced.

Further, since the reference potential is set to almost half of the normal power supply potential, when the reference potential which becomes low data is written in the first storage node, the first conductivity type memory cell has the first potential. The ground potential lower than the reference potential is applied to the first control line, and the power supply potential higher than the reference potential is applied to the first control line in the second conductivity type memory cell. The latching ability of the node is reduced, the write operation is completed quickly, and the access time can be shortened.

In this case, the absolute value of the threshold voltage of any of the first and fourth switch transistors and the first and second drive transistors is the same as that of the first and second load transistors. Further, it is preferable that the threshold voltage is set to be smaller than the absolute value of the threshold voltage of the second and third switch transistors. Thus, the absolute values of the threshold voltages of the first and fourth switch transistors and the first and second drive transistors are the same as those of the first and second load transistors and the second and third load transistors. Since the absolute value of each threshold voltage of the switch transistor is set to be smaller, the operations of the first drive transistor and the first switch transistor, and the second drive transistor and the fourth switch transistor operate at high speed. At the same time, it is possible to suppress the standby current generated during the period in which neither the read operation nor the write operation is performed, so that it is possible to further increase the speed and reduce the power consumption.

Further, in this case, the first, second and third control lines in the memory cell are read-only control lines, and the memory cell array is the write-only fourth line in the memory cell in the column direction. Control line and fifth control line, a write-only sixth control line in the memory cell in the row direction, and the sixth control line, and one of the source / drain electrodes is controlled by the first memory. A fifth switch transistor connected to the node and having the other source / drain electrode connected to the fourth control line, and one source / drain electrode controlled by the sixth control line, and the second switch transistor having the second control transistor connected to the fourth control line. A sixth switch transistor connected to the storage node and having the other source / drain electrode connected to the fifth control line, and the first and fourth switch transistors.
The absolute value of the threshold voltage of any one of the switch transistor, the first and second drive transistors, and the fifth and sixth switch transistors,
It is preferable that the absolute values of the threshold voltages of the second load transistor and the second load transistor and the second and third switch transistors are smaller than the absolute values. As described above, the first, second, and third control lines are used as read-only control lines, and further, the write-only fourth control line and the fifth control line in the memory cells in the column direction are connected to the memory cell array. A sixth control line dedicated to writing in the memory cells in the row direction, a fifth switch transistor connected to the first storage node, and a sixth switch transistor connected to the second storage node. Is newly provided, the read operation and the write operation can be simultaneously performed. Further, the absolute values of the threshold voltages of the first and fourth switch transistors, the first and second drive transistors, and the fifth and sixth switch transistors are the same as those of the first and second load transistors. Since the threshold voltages of the second and third switch transistors are set to be smaller than their absolute values, the first drive transistor and the first switch transistor, the second drive transistor, and the The operation of the switch transistor of No. 4 becomes high speed, the operation of the fifth and sixth switch transistors becomes high at the time of writing, and the standby current generated during the period in which neither read operation nor write operation is performed can be suppressed. As a result, higher speed and lower power consumption can be achieved.

[0111]

BEST MODE FOR CARRYING OUT THE INVENTION The basic idea of a read operation and a write operation in a semiconductor integrated circuit device according to the present invention will be described with reference to the drawings.

First, the basic idea of the read operation will be described.

FIG. 32 schematically shows the current flow at the time of reading in the conventional SRAM device. Figure 32
The first conventional SRAM shown in (a) supplies charges to all bit lines of the memory cell array from the precharge power supply regardless of selection / non-selection during the precharge period shown in the timing chart of FIG. 32 (b). After that, the charges are discarded from all the bit lines of the memory cell array even in the read period, and only the charges of the bit lines selected by the selection switch based on the column address input from the outside are amplified through the amplifier. . Therefore, the first
The conventional SRAM has a very low efficiency because only part of the precharge current consumption is used.

Further, the second conventional type S shown in FIG.
The RAM device supplies current only to the bit line selected by the first selection switch based on the column address in the memory cell array, and reduces the amount of supplied current to improve efficiency.

FIG. 23 schematically shows a current flow at the time of reading in the SRAM semiconductor integrated circuit device according to the present invention. As shown in the timing chart of FIG. 23B, the activation signal XSA of the sense amplifier, which will be described later, is turned on during the read period, and as shown in FIG.
A current is injected into the selected memory cell from the sense amplifier side to such an extent that the difference in impedance between the bit line pair can be detected. As a result, as shown in FIG. 23B, for example, one bit line of the selected bit line pair is grounded and the other bit line (=
If the bit complementary line) is not grounded, the potential of the bit complementary line rises. After this minute potential difference is read by the sense amplifier, the activation signal XSA of the sense amplifier is turned off. Therefore, it is an inverted signal of the activation signal XSA of the sense amplifier and is selected by the equalization signal EQ of the sense amplifier described later. The injected charges are discarded by forcibly grounding the bit line pair.

As a result, a sufficient current is supplied to the selected memory cell with a current enough to detect the impedance difference of the bit line pair from the sense amplifier side, that is, with a potential difference of about the threshold voltage of the transistors forming the memory cell. Since the signal potential is determined by the difference between the supplied and detected impedances, the read operation can be performed at high speed.

Further, since the power supply circuit and the electric power required for the precharge are unnecessary, the power consumption can be reduced.

Although the unselected bit lines are grounded, it goes without saying that the memory cell according to the present invention has a structure in which the signal potential held in the storage node is not destroyed.

Next, the basic idea of the write operation will be described.

FIG. 33 schematically shows the write operation in the conventional SRAM. In FIG. 33, SRA
Only the first drive transistor N1 and the second drive transistor N2, whose source lines of the inverter pair of the memory cells in M are connected to the ground potential Vss serving as a power source for holding low data, are extracted and shown as cross-coupled transistors. A node that holds data is a first storage node V1 and a second storage node V2.

First, the signal potential 0 is applied to the first storage node V1.
When writing V low data, as shown in FIG. 33, the signal potential of the first storage node V1 before writing is 2
If the data is high data of V, as a method of breaking the balance of the signal potentials of the first and second storage nodes V1 and V2, the charge of the signal potential is extracted from the first storage node V1 through the first switch transistor N3. It is possible. The gate-source voltage Vgs (N1) of the first driving transistor N1 before writing is 0V, and the gate-source voltage Vgs (N1) of the second driving transistor N2 is 0V.
2) is 2V. Therefore, the first drive transistor N
1 is in the off state, and the second drive transistor N2 is in the on state. When the writing operation starts, the potential of the first storage node V1 starts to gradually decrease, so that the second drive transistor N2 whose gate electrode is connected to the first storage node V1 gradually turns off.

To complete such reverse writing,
Gates of the first and second drive transistors N1 and N2
Since the potential difference between the source voltage Vgs is 2 V, the gate-source voltage Vgs (N
1) is 2V, the gate of the second drive transistor N2
The source-to-source voltage Vgs (N2) needs to be 0V.

FIG. 24 schematically shows the potential of the source line of the cross-coupled transistor at the time of writing in the SRAM semiconductor integrated circuit device according to the present invention. Figure 24
As shown in FIG. 33A, consider the case where row data is written to the first storage node V1 for a memory cell having the same configuration as that of FIG. As shown in FIG. 24 (a),
Assuming that the signal potential of the first storage node V1 before writing is high data of 2V, the potential Vm of the common source line of the cross-coupled transistor at the time of writing low data.
Is set to 1 V and set higher than the ground potential Vss.

As a result, the first drive transistor N1
Of the gate-source voltage Vgs (N1) of the second drive transistor N2 becomes 0V, and the gate-source voltage Vgs of the second drive transistor N2 becomes Vgs.
(N2) becomes 1V.

In order to complete this reverse writing, since the potential difference between the gate-source voltage Vgs of the first and second drive transistors N1 and N2 is 1 V, the gate-source voltage of the first drive transistor N1 is Vgs (N1) is 1
V needs only to have a potential difference of 1 V so that the gate-source voltage Vgs (N2) of the second drive transistor N2 becomes 0 V, and the latching capability of the first drive transistor N1 is reduced. Since the potentials of the storage node V1 and the second storage node V2 are out of balance, the write operation is completed faster than in the conventional case.

The source lines of the cross-coupled transistors in the memory cell shown in FIG. 24B are separated from each other, and the cross-coupled transistors are weakened in the latching capability of each storage node according to the write data. The potential of the first storage node V1 and the second storage node V2 is quickly lost by applying the potential of the source line of the.

Consider, for example, the case of writing raw data to the first storage node V1. As shown in FIG. 24B, the signal potential of the first storage node V1 before writing is 2
Assuming that the data is high data of V, the potential Vm1 of the first source line of the cross-coupled transistor is set to 0V of the ground potential and the potential Vm2 of the second source line of the cross-coupled transistor when writing the low data.
Are respectively applied to 1V.

Thus, the first drive transistor N1
Between the gate-source voltage Vgs (N1) of the second driving transistor N2 becomes 1V, and the gate-source voltage Vgs of the second driving transistor N2 becomes Vgs.
(N2) also becomes 1V.

In the case of the common source line shown in FIG. 24A, the first drive transistor N desired to be turned on from off.
The gate-source voltage Vgs (N1) before writing 1 is 0 V, but in the case of the separated source line shown in FIG. 24 (b), the gate-source voltage before writing of the first drive transistor N1 is 1 Since the voltage Vgs (N1) is 1 V, the first drive transistor N1 turns on faster, so that the first storage node V1 and the second storage node V1
The balance of the potential with 2 will be lost quickly. As a result, the writing operation can be performed at a higher speed.

Hereinafter, specific embodiments of the present invention will be sequentially described with reference to the drawings. First, an overall view of the semiconductor integrated circuit device according to the present invention and respective control devices in the periphery will be described,
Each embodiment will be described.

FIG. 25 is an overall configuration diagram of a semiconductor integrated circuit device according to the present invention. In the semiconductor integrated circuit device shown in FIG. 25, there are n memory cells to be SRAMs in the row direction (n is a positive integer. The same applies hereinafter) and m memory cells in the column direction (m
Is a positive integer. same as below. ) Are arranged in a matrix of n rows and m columns (n × m) in total, and a row decoder that selects a word line WL (m) by a designated row address and a bit line pair BL by a designated column address Add.
(N), / BL (n) are selected to perform a read operation and a write operation, or a third power source Vs1 (n) and a fourth power source Vs applied to an independent ground line of a memory cell.
A column circuit for selecting s2 (n), an input / output data control circuit for controlling write data Din, read data Dout, and read reference data / Dout for the column circuit, and a read request / for the column circuit. WE
Alternatively, the read / write switching control circuit for instructing the write request WE and the clock control circuit for controlling the read period by the sense amplifier activation signal XSA and the bit line equalize signal EQ are supplied to the column circuit.

In the memory cell array, the row direction means the direction in which the row address is constant and the column address changes, and the column direction means the direction in which the column address is constant and the row address changes. .

FIG. 26 is a block diagram showing a column circuit according to an embodiment of the present invention. The column circuit shown in FIG. 26 includes a bit line selection circuit DSW1 which decodes a bit line pair BL (n), / BL (n) to write data by a designated column address Add, and a designated column address. Third power supply Vs1 by Add
(N) and the fourth power supply Vs2 (n) are selected by decoding to select the ground line selection circuit DSW2, and the bit line pair B by the column address Add designated during the read operation.
L (n), / BL (n) are decoded and common data line RD
(K) and the common data reference line / RD (k) (k is a positive integer. The same applies to the following.) The selection circuit DSW3 in the preceding stage of the sense amplifier that transmits to the sense amplifier, and the selection circuit DSW1 for the bit line during the write operation. For bit line pair B
Previous bit line pair p in which L (n) and / BL (n) are multiplexed
Bit line control circuit A1 or A2 for controlling the potentials of BL (k) and / pBL (k), and a selection circuit DS for the ground line
Third power supply Vs1 (n) and fourth power supply Vs2 with respect to W2
First front ground line pVs1 in which (n) is multiplexed
(K) and the ground line control circuit B for controlling the potentials of the second front ground line pVs2 (k), and the common data line pair RD (k), / selected by the selection circuit DSW3 in the preceding stage of the sense amplifier during the read operation. This is a configuration including a sense amplifier that detects a current difference of RD (k), converts the detected current difference into a potential difference, and amplifies the potential difference.

FIG. 27A is a circuit diagram showing a bit line selection circuit according to an embodiment of the present invention. FIG. 27 (a)
The bit line selection circuit DSW1 shown in FIG. 2 includes a column decoder that decodes the input column address Add and a previous bit line pair pBL input from the bit line control circuit A1.
(K), / pBL (k) and a column switch for selecting the bit line pair BL (n), / BL (n) by the output of the column decoder.

FIG. 27B is a circuit diagram showing a ground line selection circuit according to an embodiment of the present invention. FIG. 27
The ground line selection circuit DSW2 shown in (b) includes a column decoder for decoding the input column address Add, a first front ground line pVs1 (k) and a second front ground line input from the ground line control circuit B. It is composed of a ground line pVs2 (k) and a column switch which selects the third power supply Vs1 (n) or the fourth power supply Vs2 (n) by the output of the column decoder.

FIG. 28 is a circuit diagram showing the selection circuit in the preceding stage of the sense amplifier according to the embodiment of the present invention. FIG. 28
The selection circuit DSW3 in the preceding stage of the sense amplifier shown in FIG.
A column decoder for decoding the input column address Add, and a plurality of connected bit line pairs BL (n),
Select a bit line pair BL (n), / BL (n) designated by the output of the column decoder from / BL (n),
The third column switch outputs to the common data line pair RD (k) and / RD (k).

Although the sense amplifier shown in the present application is of the input / output separation type, the bit line selection circuit DSW1 shown in FIG. 27A and the selection circuit DSW3 in the preceding stage of the sense amplifier shown in FIG. It is not necessary to provide both,
If the sense amplifier is an input / output through type, it can be shared.

The first embodiment of the present invention will be described below with reference to the drawings.

FIG. 1A is a circuit diagram showing a memory cell according to the first embodiment of the present invention. In FIG. 1A, P1 is a first load transistor of one of the inverters connected to the first power supply Vcc, and P2 is a second load transistor connected to the first power supply Vcc and forming a pair with the first load transistor P2. Second inverter load transistor, N1 is a first drive transistor for driving one inverter, N2
Is a second drive transistor that drives the other inverter paired with the first drive transistor, V1 is a first storage node that holds the signal potential of the memory cell, and V2 is a complementary potential of the first storage node V1. The second storage node BL for holding the memory cell BL is the first high data potential Vu1 as the second potential during the write operation with respect to the memory cell in the specified column direction among the memory cells arranged in an array.
Is applied to the ground potential Vx1 as the first potential during the read operation, and / BL is the second high potential which is the third potential as the write control line during the write operation. A second potential applied to the data potential Vu2, which serves as a reference for the bit line BL during the read operation and is applied to the ground potential Vx1 as the first potential.
Complementary bit line as a control line, WL is a word line as a third control line for activating a memory cell in a specified row direction among memory cells arranged in an array, and Vcc is a memory cell Is a normal power source for operating the memory cell, Vss is a second power source which is a ground potential of a reference potential for operating the memory cell, and N3 is a first power source by the bit line BL only when the word line WL is activated. Storage node V
The first switch N14 that enables the write operation and the read operation with respect to 1 is the first storage node V1 only when the bit complementary line / BL is activated during the write operation.
A second switch, V, which enables a write operation to
3 is the first drive transistor N1 and the first switch N3
Is the first connection point with.

The first drive transistor N1 and the second drive transistor N2 form a pair, the first load transistor P1 and the second load transistor P2 form a pair, and these transistor groups are flip-flop connected. There is.

The first storage node V1 is connected to the first load transistor P1 and is also connected to the second power supply Vss via the second switch N14 and the first drive transistor N1.

The second storage node V2 is connected to the second load transistor P2, and the second drive transistor N2 is connected.
It is connected to the second power source Vss via 2.

The operation of the memory cell configured as described above will be described below with reference to the drawings. FIG. 29 is a timing chart during operation of the memory cell according to the first embodiment of the present invention. In FIG. 29, CLK is a system clock for controlling the entire semiconductor integrated circuit device, RE is a read request and an inverted signal of the write request WE, pDout is the output of the sense amplifier, and / pDout is the reference output of the sense amplifier. The signal names mentioned above are omitted.

Consider a case where a read operation or a write operation is performed in synchronization with clock CLK. The read request / WE and the write request WE are signals that determine whether the read period or the write period is in progress. When the read request / WE is "1" at the rising edge of the clock CLK, the clock cycle is a read period, and when the write request WE is "1", the clock cycle is a write period. FIG. 29
As shown in, the first half clock cycle is the read period and the second half clock cycle is the write period.

First, the operation of the memory cell in the read period will be described.

First, the first storage node V1 holds "0", that is, the potential Vss of the second power supply, and the second storage node V2 holds "1", that is, the potential Vcc of the first power supply. Suppose The rising edge of the clock CLK identifies the read period, and the row address and the column address are latched.

Then, the activation signal XSA of the sense amplifier and the equalization signal EQ of the bit line are reset, and the word line WL (1) selected by the latched address.
Stands up. Also, the bit line pair BL (1), / BL
(1) is precharged to the ground potential Vx1. Figure 2
As shown in 1 (a), the bit line control circuit A1 (= precharge control circuit) is controlled by the write request WE, and the write request WE is "0" during the read period, so that the ground potential Vx1 is generated. However, the potential of Vx1 does not necessarily have to be the ground potential, and may be any potential as low as the second switch N14 shown in FIG. 1A does not operate sufficiently.

Next, when the word line WL (1) shown in FIG. 29 rises and the first switch N3 shown in FIG. 1 (a) is turned on, the first drive transistor N1 and the first switch N3 are turned on. The connection point V3 of 1 is connected to the bit line BL.

Next, the potential of the second storage node V2 is the first
Power supply Vcc, the first drive transistor is operating sufficiently, and the bit line BL is connected to the second power supply Vss with low impedance. On the other hand, bit complementary line / BL
Is only connected to the gate electrode of the second switch N14, and is therefore connected to the second power supply Vss with an impedance higher than that of the bit line BL. Therefore, the difference in electrical characteristics between the pair of bit lines BL and / BL depends only on the data held in the first storage node V1, and appears as a difference in impedance characteristics, which enables a high-speed and stable read operation. Become.

Next, the impedance difference between the bit line pair BL, / BL is sent to the sense amplifier shown in FIG. 22 (a) through the selection circuit DSW3 in the preceding stage of the sense amplifier shown in FIG. 28 (a). The difference in impedance characteristics is detected as a difference in current, the detected current difference is converted into a potential difference and amplified, and then read data D is obtained.
The data is sent as out and / Dout to the input / output data control circuit shown in FIG. 25, and the read operation is completed.

The feature of this embodiment is that the signal potential of the held data is not read out as a direct potential difference between the bit line pair BL, / BL as in the conventional case, and the bit line pair BL, / BL is not read.
Since both BLs are applied to the potential of the second power source Vss, which is the ground potential, the power used for precharging can be made unnecessary.

Further, the minimum voltage to be secured as the read current for impedance detection is the bit line pair BL, /
Since it becomes better within the range that can be detected as the difference in the impedance characteristics of BL, the voltage becomes the voltage at which the first drive transistor N1 and the second drive transistor N2 operate, that is, the threshold voltage of the transistor, so that low voltage operation becomes possible . The configuration and operation of the sense amplifier according to the present invention will be described later.

Since the first storage node V1 is cut off from the bit line by the second switch N14, the potential of the storage node V1 does not rise at the time of reading. The through current does not flow to the second power supply Vss through the driving transistor. Therefore, stable read operation is possible and unnecessary power is not consumed.

Next, the operation of the memory cell in the writing period will be described.

First, "1" is stored in the first storage node V1.
It is assumed that “0” is written in the second storage node V2.
In the latter half of the clock cycle, the rising edge of the clock CLK is recognized as the writing period, and the row address and the column address are latched.

Next, the word line WL (2) selected by the latched address rises, and the write request WE is made in the bit line control circuit A1 shown in FIG.
Is "1", the first high data potential Vu1 is generated on the previous bit line pBL (k), and the previous bit complementary line / pBL
A second high data potential Vu2 is generated at (k).

As a result, the potential of the bit complementary line / BL (1) is applied to the second high data potential Vu2. The second high data potential Vu2 is a voltage necessary for operating the second switch N14 sufficiently and is preferably as high as possible. For example, it may be the potential of the first power supply Vcc or its boosted potential Vpp.

Next, since voltage is applied to both the word line WL (2) and the bit complementary line / BL (1), both the first switch N3 and the second switch N14 are turned on.

Next, the bit line BL (1) and the first storage node V1 are connected to the first switch N3 and the second switch N.
Since they are connected through 14, the potential of the first storage node V1 gradually approaches the first high data potential Vu1. At the same time, since the gate electrode of the first load transistor P1 is connected to the second storage node V2, the first load transistor P1 is activated when the potential of the gate electrode exceeds its threshold voltage. , The first storage node V1 is connected to the first power supply Vcc.

Since the gate electrode of the second drive transistor N2 is connected to the first storage node V1,
When the potential exceeds the threshold voltage, the second drive transistor N2 is activated and the second storage node V2 is connected to the second power supply Vss. At the same time, since the gate electrode of the second load transistor P2 is connected to the first storage node V1, the second load transistor P2 stops when the potential of the gate electrode exceeds its threshold voltage and becomes high. , The second storage node V2 is cut off from the first power supply Vcc, its potential approaches the second power supply Vss, and the write operation is completed. The first high data potential Vu1 is the second high data potential Vu2 in order to shorten the writing time.
Similarly, the higher it is, the better, and the potential Vcc of the first power source or the boosted potential Vpp thereof is used.

The first modification of the first embodiment of the present invention will be described below.

In the first modification, the threshold voltage of the second switch N14 is the threshold voltage of the first driving transistor N1, the threshold voltage of the second driving transistor N2, and the first switch N3. The threshold voltage is set to be lower than any of the threshold voltages.

The feature of this modification is that the second switch N
By setting the threshold voltage of the MOS transistor to be 14 lower than that of the other transistors, the bit complementary line / BL does not need to be boosted to the potential Vpp higher than the first power source Vcc during the write operation. It is possible to realize a memory cell that operates at a low voltage.

The reason why the threshold voltage of the second switch N14 can be set low is that the threshold voltage of the second switch N14 is low, so that a through current is generated in the second switch N14. In this case, the first drive transistor N1 connected in series cuts off the through current.

A second modification of the first embodiment of the present invention will be described below.

The second modification is the second load transistor P2.
Is set to be smaller than the first load transistor P1 and the second drive transistor N2.

In the conventional memory cell design, increasing the noise margin during the read operation and increasing the write speed during the write operation are in the opposite relationship, so that access corresponding to the first switch N3 is performed. The current driving capability ratio between the transistor and the second driving transistor N2 and the current driving capability ratio between the access transistor and the second load transistor P2 have to be sufficiently taken into consideration in order to secure a noise margin.

A feature of this modification is that the first storage node V1 and the second storage node V2 have a bit line pair BL, / B.
Since each of them is cut off from L, a very large noise margin is ensured during the read operation, and the noise margin does not easily become small. Therefore, the balance of the flip-flop circuit is disturbed and the second load transistor P2 Can be made smaller, and as a result, the write operation can be speeded up.

A third modification of the first embodiment of the present invention will be described below with reference to the drawings.

FIG. 1B shows the third embodiment of the present invention.
FIG. 11 is a circuit diagram illustrating a memory cell according to a modification. Figure 1
Only the components newly added to the memory cell shown in FIG. 1B with respect to the memory cell shown in FIG. In FIG. 1B, N15 is connected in parallel with the second driving transistor N2 between the second storage node V2 and the second power supply Vss in order to increase the writing speed in the writing operation, and the bit line BL Is a third switch controlled by the first switch N3.

The write operation of the memory cell configured as described above will be described below. Generally, in the write operation, it takes more time to rewrite a storage node from “0” to “1” than to rewrite from “1” to “0”. This is because even if a voltage is applied to the storage node, the drive transistor does not operate until the applied voltage exceeds the threshold voltage of the drive transistor.

Only characteristic points as compared with the first embodiment will be described. Consider a case where "1" is written in the first storage node and "0" is written in the second storage node. First, since a voltage of about the first power supply Vcc is applied to the word line WL and a second high data potential Vu2 is applied to the bit complementary line / BL, the first switch N3 and the second switch N14 are applied.
Turn on together.

Next, the bit line BL and the first storage node V
Since 1 and 1 are connected through the first switch N3 and the second switch N14, the potential of the first storage node V1 gradually approaches the first high data potential Vu1. Also, the first
Since the potential of the connection point V3 of the second storage node V2 is higher than that of the first storage node V1, the third switch N15 starts to operate before the second drive transistor N2 operates. The potential rapidly approaches the potential of the second power supply Vss, the first drive transistor N1 rapidly stops operating, and the first load transistor P1 rapidly becomes a low impedance, which is the same as in the first embodiment. The write operation can be performed faster than in the case.

Although the number of transistors per memory cell is increased by one, since the symmetry is improved,
There is no disadvantage when designing a layout on a semiconductor substrate.

A fourth modification of the first embodiment of the present invention will be described below with reference to the drawings.

FIG. 2A shows a fourth embodiment of the first embodiment of the present invention.
The electric potential of the power supply of the memory cell which concerns on a modification is shown. In FIG. 2 (a), Vm is the potential of the sixth power source Vm which is higher than the potential of the second power source Vss by lowering the potential of the first power source Vcc by the step-down circuit. The word line WL and the bit complementary line / BL during the write operation are applied to the potential of the first power supply Vcc, and the memory cell according to the first embodiment is the sixth
In this configuration, the potential of the power source Vm is applied.

A feature of this modification is that the flip-flop-connected transistor group has a potential of the sixth power source Vm lower than the potential of the first power source Vcc even during the read operation. Is applied to the potential of the second power supply Vss and is applied to the bit complementary line / BL at the same potential as the potential of the first power supply Vcc similar to that of the first embodiment during the write operation, so that stable operation is performed. can do.

Further, since the potential of the sixth power source Vm intermediate between the first power source Vcc and the second power source Vss is applied to the common source line of the memory cell, the signal potential latching ability is lowered. Therefore, the write operation becomes faster.

A fifth modification of the first embodiment of the present invention will be described below with reference to the drawings.

FIG. 2B shows the fifth embodiment of the present invention.
The electric potential of the power supply of the memory cell which concerns on a modification is shown. In FIG. 2B, the step-down circuit shown in FIG. 2A is replaced with the memory cell according to the first embodiment.

FIG. 3 is a circuit diagram showing a memory cell according to a fifth modification of the first embodiment of the present invention. The memory cell in FIG. 3A corresponds to the memory cell 2 shown in FIG. 2B, and the memory cell configuration corresponds to each transistor of the memory cell according to the first embodiment shown in FIG. 1A. The conductivity type is set to the opposite conductivity type of the transistor. Figure 3
The memory cell in (b) corresponds to the memory cell 1 shown in FIG. 2 (b), and the configuration of the memory cell is similar to that of the memory cell according to the first embodiment shown in FIG. 1 (a).

As a feature of this modification, the memory cell 1 is
Flip-flop connected transistor groups N1, N
2, even if the potential for driving P1 and P2 is the potential of the sixth power source Vm, which is about half the potential of the first power source Vcc, the word line WLn is the first power source during the read operation. The bit line pair BLn, / BLn is second to the potential of Vcc.
Is applied to the potential of the power source Vss, and the word line WLn and the bit complementary line / BLn are applied to the same potential as the potential of the first power source Vcc, which is the same as that of the first embodiment, during the write operation, and therefore stable. Can act.

Further, the memory cell 2 includes the sixth power source Vm in which the potential at which the flip-flop connected transistor groups P1, P2, N1 and N2 are driven is approximately one half of the potential of the first power source Vcc. Even if the potential is, the word line WLp becomes the potential of the second power source Vss during the read operation.
The bit line pair BLp, / BLp is applied to a potential similar to the potential of the first power supply Vcc, and the word line WLp and the bit complementary line / BLp are the second power supply opposite to that of the first embodiment during the write operation. Since it is applied to the potential of Vss, stable operation can be performed.

Further, the memory cell 1 and the memory cell 2
Since the potential of the sixth power source Vm is applied to the common source line, the ability to latch the signal potential is reduced.
Write operation becomes faster.

A sixth modification of the first embodiment of the present invention will be described below with reference to the drawings.

FIG. 4 is a schematic diagram showing a memory cell array according to a sixth modification of the first embodiment of the present invention.

FIG. 5 is a timing chart for reading data from the memory cell array according to the sixth modification of the first embodiment of the present invention. In FIG. 5, dT1 represents the time difference of rising of the word line WL (m) between this embodiment and the conventional example, and dT2 represents the time difference of read data output between this embodiment and the conventional example.

In FIG. 4A, the memory cells according to the first embodiment shown in FIG. 1A are arranged in an array of 4 rows × 16 columns, and WL (m) is a word line and BL (m). n)
Is a bit line, and / BL (n) is a bit complementary line that serves as a write control line during writing. In FIG. 4 (b),
The row system shows a gate array which decodes the conventional word line WL (m) when the memory cells are arranged in 8 rows × 8 columns, and the column system also shows the conventional bit line pair B.
A gate array for decoding L (n) and / BL (n) is shown. In FIG. 4C, the row system shows a gate array that decodes the word line WL (m) of the sixth modification when the memory cells are arranged in 4 rows × 16 columns, and the column system is the same. Bit line pair BL of this embodiment
A gate array for decoding (n) and / BL (n) is shown.

Conventionally, in the SRAMs arranged in an array, since the address non-multiplex in which the row address and the column address are not distinguished is adopted, the previous address is decoded by the word line WL (m) or the bit line BL. It can be assigned to either of the decoding of (n). When the word line WL (m) is activated, a through current flows through all the memory cells connected to the activated word line WL (m) and the bit line pair BL (n), /
Since a potential difference occurs in BL (n), the bit line BL
Since power is unnecessarily consumed when equalizing (n), there is a tendency to increase the number of word lines WL (m) as much as possible to reduce the number of memory cells connected to one word line WL (m). there were. However, if the number of word lines WL (m) is increased, it takes time to decode the row address, which causes a problem that the access time from address input to data output is extended.

As shown in FIGS. 4 (b) and 4 (c),
The decoding system is different between the conventional example and the sixth modified example, and the row system according to the present modified example for decoding a row address has a smaller number of stages in the gate array than the conventional case, so the decoding time is shortened, and the column system according to the present modified example. Since the number of stages of the gate array is larger than that of the conventional case, the decoding time will be extended.

However, as shown in FIG. 5, the access time from address input to data output is shorter in the sixth modification than in the conventional example. Because the rise time of the decoded word line WL (m) is fast,
The potential of the data signal appears on the bit line BL (n) earlier, and the decoding of the word line WL (m) ends even if it takes time to decode the bit line BL (n). After that, if the decoding of the bit line BL (n) is completed by the time the potential of the data signal appears on the bit line BL (n), the extra time taken by the conventional method is offset. is there.

As a feature of this modification, since the storage node of the memory cell connected to the activated word line WL (m) is cut off from the bit line BL (n), the through current does not flow, and the Since memory cells that do not consume power are used for charging, the power consumption per memory cell is small. As a result, the number of memory cells that can be connected per word line is increased, so that the number of word lines WL (m) can be reduced, so that the row address can be decoded faster, and thus the access time can be shortened. can do.

The second embodiment of the present invention will be described below with reference to the drawings.

FIG. 6A is a circuit diagram showing a memory cell according to the second embodiment of the present invention. In FIG. 6A, only the difference in configuration from the memory cell according to the first embodiment shown in FIG. 1A will be described. N24 is activated by the bit complementary line / BL during the write operation,
Second switch connected in series between the switch N3 and the second storage node V2, N25 being the first switch.
Is connected in series between the switch N3 and the second power supply Vss, which is a common ground line of the memory cell, and is activated by the first storage node during the read operation to control the impedance of the bit line pair BL, / BL. Is a third switch for performing.

The operation of the memory cell configured as described above will be described below only for the differences from the first embodiment.

First, the operation of the memory cell in the read period will be described. The first storage node V1 holds "0", that is, the potential Vss of the second power supply, and the second storage node V1.
It is assumed that 2 holds "1", that is, the potential Vcc of the first power supply.

First, the word line WL rises and the first switch N3 is turned on.

Next, the potential of the first storage node V1 is set to the second
Of the third switch N2 because it is the ground potential of the power source Vss of
5 is turned off, and there is no difference in the impedance characteristics between the bit line BL and the bit complementary line / BL that is the reference thereof.

On the contrary, the first storage node V1 holds "1", that is, the potential of the first power supply Vcc, and the second storage node V2 holds "0", that is, the ground potential of the second power supply Vss. When held, the third switch N25 is turned on, which causes a difference in impedance characteristics between the bit line BL and the bit complementary line / BL.

Therefore, as in the first embodiment, the difference in electrical characteristics between the bit line pair BL, / BL depends only on the data held in the first storage node V1 and appears as a difference in impedance characteristics. A stable read operation becomes possible.

Next, the operation of the memory cell in the writing period will be described. It is assumed that "1" is written in the first storage node V1 and "0" is written in the second storage node V2.

First, since a voltage of about the first power supply Vcc is applied to the word line WL and the second high data potential Vu2 is applied to the bit complementary line / BL, the first switch N
Both 3 and the second switch N24 are turned on.

Next, the bit line BL and the second storage node V
2 is connected through the first switch N3, the potential of the second storage node V2 gradually approaches the ground potential Vx1 applied to the bit line BL. Further, since the gate electrode of the first drive transistor N1 is connected to the second storage node V2, the operation of the first drive transistor N1 is stopped when the voltage drops to the threshold voltage thereof, and the first load transistor Since the gate electrode of P1 is connected to the second storage node V2, the first load transistor P1
1 starts operating when the voltage drops below its threshold voltage, so that the potential of the first storage node V1 changes to the first power supply Vcc.
And the write operation is completed. The storage node to be written is the first storage node V1 in the memory cell of the first embodiment, and the second storage node V2 in the present embodiment as described above.

The feature of this embodiment is that the number of transistors connected from the first storage node V1 and the second storage node V2 to the second power supply is one, and the symmetry is good. Further, since the second switch N24 activated by the bit complementary line / BL is not connected in series in the inverter, the noise margin becomes larger than that in the first embodiment.

The memory cell of the present embodiment and the memory cell of the first embodiment are selectively used according to the present embodiment in which the second switch N24 is not connected in series in the inverter when the noise margin is prioritized. Using memory cells,
In the case where the degree of integration is prioritized, the memory cell of the first embodiment composed of six transistors may be used.

The first modification of the second embodiment of the present invention will be described below.

The first modification is the first load transistor P.
The size of 1 is set to be smaller than that of the second load transistor P2.

In the write operation, it takes the longest time to rewrite “0” of the first storage node to “1”. It is because the first storage node V1 is cut off from the bit line BL, and the second storage node V2 is
Is written indirectly by setting "0" to "0", so that it takes time for the first drive transistor N1 to stop sufficiently and for the first load transistor P1 to operate sufficiently. Since the MOS transistor does not operate unless the threshold voltage is exceeded, the operating time can be shortened by reducing the size of the first load transistor P1 to reduce the capacitance.

A feature of this modification is that the first storage node V1 and the second storage node V2 have a bit line pair BL, / B.
Since it is cut off from L, a very large noise margin is ensured at the time of read operation, and it does not easily become small. Therefore, the balance of the flip-flop circuit is disturbed and the size of the first load transistor P1 is made small. The writing operation can be facilitated and the writing operation can be speeded up.

A second modification of the second embodiment of the present invention will be described below with reference to the drawings.

FIG. 6B shows a second embodiment of the second embodiment of the present invention.
FIG. 11 is a circuit diagram illustrating a memory cell according to a modification. Figure 6
Only the components newly added to the memory cell shown in FIG. 6B with respect to the memory cell shown in FIG. 6A will be described. In FIG. 6B, N26 is a first drive transistor N1 between the first storage node V1 and the second power supply Vss in order to increase the write speed to the second storage node V2 during the write operation. A fourth switch connected in parallel and controlled by the bit line BL.

The write operation of the memory cell configured as described above will be described below. "0" in the first storage node
And write "1" to the second storage node. Explaining only the characteristic points in comparison with the second embodiment, first, a voltage of about the first power supply Vcc is applied to the word line WL and the second high data potential Vu2 is applied to the bit complementary line / BL. Is applied, the first switch N3 and the second switch N14 are both turned on.

Next, the bit line BL and the second storage node V
2 is connected through the first switch N3 and the second switch N24, the potential of the second storage node V2 gradually approaches the first high data potential Vu1. Also, the fourth
Since the potential of the gate electrode of the switch N26 of the second switch N26 is higher than that of the second storage node V2, the operation of the fourth switch N26 is started before the operation of the first drive transistor N1. The potential of the storage node V1 rapidly approaches the potential of the second power supply Vss. Therefore, the second drive transistor N2 rapidly stops operating, and the second load transistor P2 rapidly becomes low impedance,
The write operation can be performed faster than in the embodiment.

A third modification of the second embodiment of the present invention will be described below with reference to the drawings.

FIG. 2A shows the third embodiment of the second embodiment of the present invention.
The electric potential of the power supply of the memory cell which concerns on a modification is shown. In this embodiment, the memory cell 1 of the fourth modification of the first embodiment is replaced with the memory cell of the second embodiment.

A feature of the present modification is that the flip-flop connected transistor group has a potential of the sixth power source Vm lower than the potential of the first power source Vcc even during the read operation. Is applied to the potential of the second power source Vss and is applied to the bit complementary line / BL at the same potential as the potential of the first power source Vcc similar to that of the second embodiment during the write operation, so that stable operation is achieved. it can.

Since the potential of the sixth power source Vm intermediate between the first power source Vcc and the second power source Vss is applied to the common source line of the memory cell, the signal potential latching ability is lowered. Therefore, the write operation becomes faster.

A fourth modification of the second embodiment of the present invention will be described below with reference to the drawings.

FIG. 2B shows a fourth embodiment of the second embodiment of the present invention.
The electric potential of the power supply of the memory cell which concerns on a modification is shown. 2B, the step-down circuit shown in FIG. 2A is replaced with the memory cell according to the second embodiment.

FIG. 7 is a circuit diagram showing a memory cell according to a fourth modification of the second embodiment of the present invention. The memory cell in FIG. 7A corresponds to the memory cell 2 shown in FIG. 2B, and the configuration of the memory cell corresponds to each transistor of the memory cell according to the second embodiment shown in FIG. 6A. The conductivity type is set to the opposite conductivity type of the transistor. Figure 7
The memory cell in (b) corresponds to the memory cell 1 shown in FIG. 2 (b), and the configuration of the memory cell is similar to that of the memory cell according to the first embodiment shown in FIG. 6 (a).

As a feature of this modification, as in the fifth modification of the first embodiment, in the memory cell 1, the load transistors P1 and P2 and the drive transistors N1 and N2 connected in a flip-flop are operated at a low voltage. , Word line W
Since Ln and the bit line pair BLn, / BLn are controlled by the same non-stepped down potential as in the second embodiment, stable operation can be performed.

Similarly, in the memory cell 2, the load transistors N1 and N2 and the drive transistors P1 and P2, which are flip-flop connected, operate at a low voltage, and the word line WLp and the bit line pair BLp, / BLp are the second embodiment. Since it is controlled by the same potential that is not stepped down as in the form, stable operation can be performed.

Further, the memory cell 1 and the memory cell 2
Since the potential of the sixth power source Vm is applied to the common source line, the ability to latch the signal potential is reduced.
Write operation becomes faster.

A fifth modification of the second embodiment of the present invention will be described below with reference to the drawings.

FIG. 4 is a schematic diagram showing a memory cell array according to a fifth modification of the second embodiment of the present invention.

FIG. 5 is a timing chart for reading data from the memory cell array according to the fifth modification of the second embodiment of the present invention.

The memory cell in FIG. 4A is the same as that in FIG.
The memory cells of the second embodiment shown in (a) are arranged in an array of 4 rows × 16 columns, where WL is a word line, BL is a bit line, and / BL is a bit complementary line which becomes a write control line at the time of writing. Is. The description of FIGS. 4B, 4C, and 5 is the same as that of the sixth modified example of the first embodiment, and therefore will be omitted.

As a feature of this modification, as in the sixth modification of the first embodiment, a memory cell connected to an activated word line has a storage node cut off from a bit line, and therefore a through current is generated. Since the memory cells that do not flow and consume no power for precharging are used, the power consumption per memory cell is reduced, and the number of word lines can be reduced, resulting in a shorter access time. can do.

Hereinafter, a third embodiment of the present invention will be described with reference to the drawings.

FIG. 8A is a circuit diagram showing a memory cell according to the third embodiment of the present invention. In FIG. 8A, only the difference in configuration from the memory cell according to the first embodiment shown in FIG. 1A will be described. Vs1 is the third one to which the ground line of the first drive transistor N1 is connected. Power supply,
Vs2 is a fourth power supply to which the ground line of the second drive transistor N2 is connected.

FIG. 9 is a circuit diagram showing a ground line control circuit according to the third embodiment of the present invention. In FIG.
WE is a write request notified by the read / write switching control circuit shown in FIG. 25, Din is write data notified by the input / output data control circuit shown in FIG. 25, p
Vs1 (k) is sent to the ground line selection circuit DSW2 shown in FIG.
Of the multiplexed first front ground line, pVs2 (k), for application to the power supply Vs1 of the memory cell is also sent to the ground line selection circuit DSW2 and applied to the fourth power supply Vs2 of the memory cell. Second front ground line, Vu3
Is the ground line control potential applied to the first front ground line pVs1 (k) and the second front ground line pVs2 (k), and Vss is the first front ground line pVs1 (k) and the second front ground line pVs1 (k).
The second power source, which is the ground potential applied to the front ground line pVs2 (k) of PB1, opens and closes the ground line control potential Vu3 to the first front ground line pVs1 (k) according to the complementary value of the write request WE. The first P-type switch PB2 is connected to the first front ground line pV according to the write data Din.
s1 (k) is a second P-type switch for opening / closing the ground line control potential Vu3, and NB1 is a second P-type switch for opening / closing the potential of the second power supply Vss on the first front ground line pVs1 (k) according to the write data Din. A first N-type switch, NB2 is a second N-type switch for opening and closing the potential of the second power supply Vss to the first front ground line pVs1 (k) in response to the write request WE, N
B3 is a third N-type switch that opens and closes the potential of the second power supply Vss to the first front ground line pVs1 (k) according to the complementary value of the write request WE, and PB3 is according to the complementary value of the write request WE. A third P-type switch for opening and closing the ground line control potential Vu3 on the second front ground line pVs2 (k),
PB4 supplies the ground line control potential Vu3 to the second front ground line pVs2 (k) according to the complementary value of the write data Din.
NB4 is a fourth P-type switch for opening / closing the second front ground line pVs2 according to the complementary value of the write data Din.
A fourth N-type switch that opens and closes the potential of the second power supply Vss at (k), and NB5 opens and closes the potential of the second power supply Vss at the second front ground line pVs2 (k) in response to the write request WE. The fifth N-type switch, NB6, is a sixth N-type switch that opens and closes the potential of the second power supply Vss to the second front ground line pVs2 (k) according to the complementary value of the write request WE.

The operation of the ground line control circuit B configured as described above will be described below.

In this embodiment, the write request WE
Is positive logic.

First, when the write request WE is "1",
That is, the operation of the ground line control circuit B in the writing period will be described.

When the write data Din is "1", the first
The first P-type switch PB1, the first N-type switch NB1, and the second N-type line on the front ground line pVs1 (k) of
Since the type switch NB2 is closed and the other switches are opened, the first front ground line pVs1 (k) is applied to the potential of the second power supply Vss, and the third front ground line pVs2 (k) is Since the P-type switch PB3, the fourth P-type switch PB4, and the fourth N-type switch NB4 are closed and the other switches are opened, the second front ground line pVs2 (k) is applied to the ground line control potential Vu3. .

When the write data Din is "0", the first
Of the first P-type switch PB1, the second P-type switch PB2, and the second N on the front ground line pVs1 (k) of
Since the type switch NB2 is closed and the other switches are opened, the first front ground line pVs1 (k) is applied to the ground line control potential Vu3 and the second front ground line pVs2 (k) is applied.
, The third P-type switch PB3, the fourth N-type switch NB4, and the fifth N-type switch NB5 are closed and the other switches are opened, so that the second front ground line pVs2
(K) is applied to the potential of the second power supply Vss.

Next, when the write request WE is "0",
That is, the operation of the ground line control circuit B in the read period will be described.

When the write data Din is "1", the first
Of the first ground line pVs1 (k), the first N-type switch NB1 and the third N-type switch NB3 are closed and the other switches are opened.
(K) is applied to the potential of the second power supply Vss, and the fourth P-type switch PB4 and the sixth N-type switch NB6 are closed and the other switches are opened in the second front ground line pVs2 (k). Therefore, the previous bit complementary line / pBL (k) is the second
Is applied to the potential of the power source Vss.

When the write data Din is "0", the first
Of the first ground line pVs1 (k), the second P-type switch PB2 and the third N-type switch NB3 are closed and the other switches are opened.
(K) is applied to the potential of the second power supply Vss, and the fourth N-type switch NB4 and the sixth N-type switch NB6 are closed and the other switches are opened in the second front ground line pVs2 (k). Therefore, the second front ground line pVs2 (k) is applied to the potential of the second power supply Vss.

A feature of this embodiment is that during the writing period, the potential of the second power source Vss or the ground line control potential Vu3 applied to the third power source Vs1 or the fourth power source Vs2 is changed according to the write data Din. A second voltage generated and applied to the third power supply Vs1 or the fourth power supply Vs2 during the read period.
The electric potential of the power source Vss is also generated.

The operation of the memory cell configured as described above will be described below with reference to the drawings.

FIG. 30 is a timing chart during operation of the memory cell according to the third embodiment of the present invention. Since each signal is the same as that in FIG. 29, the description is omitted.

As shown in FIG. 30, in the read operation, the timing chart of the read period is the same as the timing chart of the read period shown in FIG. 29, and since the operation is the same, the description thereof will be omitted.

Also in the write operation, only the difference from the first embodiment will be described. First, it is assumed that "1" is written in the first storage node V1 and "0" is written in the second storage node V2.

Next, the word line WL (2) selected by the latched address rises, and in the ground line control circuit B shown in FIG. 9, the write request WE is "1" and the AT data Din is "1". 0 ", the ground line control potential Vu3 is generated on the first front ground line pVs1 (k), and the second front ground line pVs2 is generated.
The potential of the second power supply Vss is generated at (k).

Next, the potential of the bit complementary line / BL (1) is applied to the second high data potential Vu2 and the third power supply Vs1 (1) is applied to the ground line control potential Vu3, and the fourth Power source Vs2 (1) is applied to the potential of the second power source Vss.

Next, a voltage of about the first power supply Vcc is applied to the word line WL (2), and the bit complementary line / BL (1) is applied.
Since the second high data potential Vu2 is applied to the
The first switch N3 and the second switch N shown in (a)
Both 14 are turned on.

Next, the bit line BL and the first storage node V
Since 1 and 1 are connected through the first switch N3 and the second switch N14, the potential of the first storage node V1 gradually approaches the first high data potential Vu1, and conversely, of the second storage node V2. The potential gradually approaches the potential of the second power supply Vss.

A feature of this embodiment is that the second switch N14 is always in operation during the write operation period, and the first load transistor P1 and the first drive transistor N1 are also at the potential of the first storage node V1. In the transitional period until “1” becomes “1”, the through current flows from the first power supply Vcc to the third power supply Vs1 because it is in operation. However, a third power supply V connected to the first storage node
By setting the potential of s1 higher than the potential of the second power supply Vss which is the ground potential, the first drive transistor N1
Since the on-state resistance is increased, the through current flowing through the first drive transistor N1 is suppressed, and the write operation is completed quickly.

Further, since the third power supply is applied higher than the second power supply Vss, the ability to latch the signal potential of the second storage node is lowered, so that the first drive transistor N
It turns off earlier than when 1 is the second power supply Vss. As a result, the balance of the signal potential is quickly lost, and the write operation is further accelerated.

The ground line control potential Vu3 is expressed by the equation 1
It is set to be equal to or higher than 00 mV and equal to or lower than a potential difference between the potential of the first power supply Vcc and the threshold voltage Vt of the first drive transistor N1.

A first modification of the third embodiment of the present invention will be described below with reference to the drawings.

FIG. 8B shows the first embodiment of the third embodiment of the present invention.
It is a circuit diagram showing a part of memory cell array concerning a modification. In FIG. 8B, the memory cells 31, 32, and 33 are the memory cells according to the third embodiment shown in FIG. 8A, which are connected to the same word line WL.
1st fourth power supply Vs2 (n-1) and 3rd memory cell 32
Connected to the power supply Vs1 (n) of
Power supply Vs2 (n) of the memory cell 33 and the third power supply Vs1 of the memory cell 33
(N + 1) is connected.

In the memory cell having the above structure, when writing to memory cell 32, the adjacent memory cells are bit complementary lines / BL serving as write control lines.
Since (n-1) and / BL (n + 1) are not selected, the second switch N1 of the adjacent memory cells 31 and 33 is
4 is off. Therefore, the third power source Vs1 and the fourth power source
Potential difference from the power source Vs2, that is, the ground line control potential Vu3 is several hundred mV or more, and the potential of the first power source Vcc and the threshold voltage Vt of the first drive transistor N1 or the second drive transistor N2. It can be set below the potential of the difference.

A feature of this modification is that the third power supply Vs1 and the fourth power supply Vs2 of the memory cells adjacent to each other can be shared so that the number of divided ground lines does not increase. Does not sacrifice the circuit element forming region.

The second modification of the third embodiment of the present invention will be described below.

In the second modification, as in the first modification of the first embodiment, the threshold voltage of the second switch N14 is equal to the threshold voltage of the first drive transistor N1 and the second drive. The threshold voltage of the transistor N2 and the first switch N
The configuration is such that it is set to be lower than the threshold voltage of 3.

A feature of this modification is that, as in the first modification of the first embodiment, a MOS serving as the second switch N14 is formed.
By setting the threshold voltage of the type transistor to be lower than that of other transistors, the bit complementary line / BL does not need to be boosted to the potential Vpp higher than the potential of the first power source Vcc during the write operation. Therefore, a memory cell that operates with a low voltage can be realized.

The third modification of the third embodiment of the present invention will be described below.

In the third modification, the size of the second load transistor P2 is smaller than that of the first load transistor P1 and the second drive transistor N2, as in the second modification of the first embodiment. The configuration is set to.

As a feature of this modification, as in the second modification of the first embodiment, the first storage node V1 and the second storage node V2 are cut off from the bit line pair BL, / BL, respectively. Therefore, a very large noise margin is ensured at the time of read operation, and since it does not easily become small, the balance of the flip-flop circuit is disturbed,
The size of the second load transistor P2 can be reduced, and the write operation becomes faster.

A fourth modification of the third embodiment of the present invention will be described below with reference to the drawings.

FIG. 10 is a circuit diagram showing a memory cell according to a fourth modification of the third embodiment of the present invention. In FIG. 10, only the difference in configuration from the memory cell according to the third embodiment shown in FIG. 8A will be described. / BL is the bit line BL applied to the potential of the fourth power supply Vs2 during the write operation.
And WT is a write control line as a second control line applied to the second high data potential Vu2 during the write operation.

Second power supply Vss applied to fourth power supply Vs2
And the ground line control potential Vu3 are generated by the ground line control circuit B shown in FIG. 9, and the second high data potential Vu2 is generated by the bit line control circuit A2 shown in FIG.

The read operation and write operation of the fourth modified example are similar to those of the third embodiment, and will be omitted.

A feature of this modification is that, in the case of a write operation in the case where more memory cells are connected in the column direction than in the row direction, the potential of the second power supply Vss changes to the second high data potential. Since the wiring of the write control line WT whose potential changes greatly to Vu2 is arranged in parallel with the word line WL, the number of memory cells connected to the write control line WT is reduced, so that the load capacitance of the write control line WT is reduced. Since the power consumption is reduced, the power consumption of the memory cell is reduced and the write operation becomes faster.

Further, when the potential of the third power supply Vs1 which is the potential of the ground line of the first drive transistor N1 is controlled by the ground line control circuit B shown in FIG. 9 and the write operation is performed, the write control is performed. Since the line WT is selected from the row direction, the bit line BL to which the write data signal is applied is arranged in the column direction, and the write control line WT to which the write control voltage is applied is arranged in the row direction. Since the memory cell to be written is limited to the selected memory cell where the bit line BL and the write control line WT cross each other, so-called erroneous writing in which data is written to the unselected memory cell is prevented. be able to.

A fifth modification of the third embodiment of the present invention will be described below with reference to the drawings.

FIG. 11 is a schematic diagram showing a memory cell array according to a fifth modification of the third embodiment of the present invention. Figure 1
In FIG. 1, when the memory cells according to the fourth modified example of the third embodiment shown in FIG. 10 are arranged in an array, one write control line WT is arranged for four word lines WL. It is a composition. The potential of the write control line WT is generated by the bit line control circuit A2 shown in FIG. 21B, as in the fourth modification of the third embodiment.

As shown in FIG. 11, assuming that there is a selected column for every four columns, four write control lines WT are provided for the 16 word lines, so that four write control lines WT are provided.
Since the write control line WT of the book is connected to the memory cells of different column addresses, only the selected cell is selected at the same time by the word line WL serving as the word line and the write control line WT serving as the write control line. Become a memory cell. Therefore, the third power source Vs1 and the fourth power source Vs
Even if the potential of s2 changes during the write operation, erroneous write to the unselected memory cells can be prevented.

A feature of this modification is that the write control line WT is not provided for each row address that is the same as that of the word line WL, but only one write control line WT is provided for four word lines WL. Since the number of lines WT can be reduced, the write control line WT does not sacrifice the circuit element formation region on the semiconductor substrate.

A sixth modification of the third embodiment of the present invention will be described below with reference to the drawings.

FIG. 12 is a circuit diagram showing a memory cell according to a sixth modification of the third embodiment of the present invention. Figure 8 (a)
Only the components newly added to the memory cell shown in FIG. 12 with respect to the memory cell shown in FIG. In FIG. 12, N35 is a second storage node V for increasing the write speed to the first storage node V1 during the write operation.
Second drive transistor N between the second power supply Vs2 and the fourth power supply Vs2
The third switch is connected in parallel with 2 and is controlled by the bit line BL via the first switch N3.

The write operation of the memory cell configured as described above will be described below.

Only characteristic points as compared with the third embodiment will be described. Consider a case where "1" is written in the first storage node and "0" is written in the second storage node. First, since a voltage of about the first power supply Vcc is applied to the word line WL and a second high data potential Vu2 is applied to the bit complementary line / BL, the first switch N3 and the second switch N14 are applied.
Turn on together.

Next, the bit line BL and the first storage node V
1 is connected through the first switch N3 and the second switch N14, the potential of the first storage node V1 is the first high data potential generated by the bit line control circuit A1 shown in FIG. It gradually approaches Vu1. Since the potential of the first connection point V3 is higher than that of the first storage node V1, the third switch N35 starts its operation before the second drive transistor N2 operates. The potential of the second storage node V2 rapidly approaches the potential of the second power supply Vss, the first drive transistor N1 rapidly stops operating, and the first load transistor P1 rapidly becomes low impedance, The write operation can be performed faster than in the third embodiment.

Although the number of transistors per memory cell is increased by one, the symmetry is improved, so that there is no disadvantage in designing the layout on the semiconductor substrate.

A seventh modification of the third embodiment of the present invention will be described below with reference to the drawings.

FIG. 2A shows the seventh embodiment of the present invention.
The electric potential of the power supply of the memory cell which concerns on a modification is shown. The seventh modification has a configuration including the memory cell of the third embodiment in place of the memory cell 1 of the fourth modification of the first embodiment.

A feature of this modification is that the flip-flop-connected transistor group has a potential of the sixth power source Vm lower than the potential of the first power source Vcc even during the read operation. Is applied to the potential of the second power supply Vss and is applied to the bit complementary line / BL at the same potential as the potential of the first power supply Vcc similar to that of the third embodiment during the write operation, so that stable operation is achieved. it can.

Further, since the potential of the sixth power source Vm intermediate between the first power source Vcc and the second power source Vss is applied to the common source line of the memory cell, the signal potential latching capability is lowered. Therefore, the write operation becomes faster.

An eighth modification of the third embodiment of the present invention will be described below with reference to the drawings.

FIG. 2B shows the eighth embodiment of the third embodiment of the present invention.
The electric potential of the power supply of the memory cell which concerns on a modification is shown. 2B, the step-down circuit shown in FIG. 2A is replaced with the memory cell according to the third embodiment.

FIG. 13 is a circuit diagram showing a memory cell according to an eighth modification of the third embodiment of the present invention. FIG.
The memory cell in (a) corresponds to the memory cell 2 shown in FIG. 2 (b), and the configuration of the memory cell is the same as that of each transistor in the memory cell according to the third embodiment shown in FIG. 8 (a). It is set to the opposite conductivity type to the conductivity type. The memory cell in FIG. 13B corresponds to the memory cell 1 shown in FIG. 2B, and the configuration of the memory cell is shown in FIG.
This is similar to the memory cell according to the first embodiment shown in (a).

As a feature of this modification, as in the fifth modification of the first embodiment, in the memory cell 1, the load transistors P1 and P2 and the drive transistors N1 and N2 connected in the flip-flop are operated at a low voltage. , Word line W
Since Ln and the bit line pair BL, / BLn are controlled by the same non-stepped down potential as in the third embodiment, stable operation can be performed.

In the memory cell 2, the load transistors N1 and N2 and the drive transistors P1 and P2 connected in a flip-flop operate at a low voltage, and the word line W
Since Lp and the pair of bit lines BLp and / BLp are controlled by the potential which is not stepped down as in the third embodiment, stable operation can be performed.

Further, the memory cell 1 and the memory cell 2
Since the potential of the sixth power source Vm is applied to the common source line, the ability to latch the signal potential is reduced.
Write operation becomes faster.

The ninth modification of the third embodiment of the present invention will be described below with reference to the drawings.

FIG. 4 is a schematic diagram showing a memory cell array according to a ninth modification of the third embodiment of the present invention.

FIG. 5 is a timing chart for reading data from the memory cell array according to the ninth modification of the third embodiment of the present invention.

In FIG. 4A, the memory cell is shown in FIG.
The memory cells of the third embodiment shown in (a) are arranged in an array of 4 rows × 16 columns, and WL is a word line, BL is a bit line, and / BL is a bit complementary line which becomes a write control line at the time of writing. Is. The description of FIG. 4B, FIG. 4C, and FIG. 5 is the same as that of the sixth modified example of the first embodiment, and therefore will be omitted.

As a feature of this modification, as in the sixth modification of the first embodiment, a memory cell connected to an activated word line has a storage node cut off from a bit line, and therefore a through current is generated. Since the memory cell that does not flow and consumes no power for precharging is used, the power consumption per memory cell is small, so that the number of word lines WL can be reduced, and as a result, the access time is shortened. can do.

The fourth embodiment of the present invention will be described below with reference to the drawings.

FIG. 14A is a circuit diagram showing a memory cell according to the fourth embodiment of the present invention. In FIG. 14A, only the difference in configuration from the memory cell according to the second embodiment shown in FIG. 6A will be described. Vs1 is the third one to which the ground line of the first drive transistor N1 is connected. A power source, Vs2, is a fourth power source to which the ground line of the second drive transistor N2 is connected.

FIG. 9 is a circuit diagram showing a ground line control circuit according to the fourth embodiment of the present invention. Since the ground line control circuit B shown in FIG. 9 is used in common with the third embodiment, description thereof will be omitted.

The operation of the memory cell and the ground line control circuit configured as described above will be described below with reference to the drawings.

FIG. 30 is a timing chart during the operation of the memory cell according to the fourth embodiment of the present invention.

As shown in FIG. 30, in the read operation, the timing chart of the read period is the same as the timing chart of the read period shown in FIG. 29, and the operation is also the same, so the description thereof will be omitted.

Also in the write operation, only the difference from the second embodiment will be described. First, it is assumed that "0" is written in the first storage node V1 and "1" is written in the second storage node V2.

Next, the word line WL (2) selected by the latched address rises, and in the ground line control circuit B shown in FIG. 9, the write request WE is "1" and the write data Din is "0". , The first front ground line pVs1 (k) is applied to the ground line control potential Vu3, and the second front ground line pVs1 (k) is applied.
s2 (k) is applied to the potential of the second power supply Vss.

Next, the potential of the bit complementary line / BL (1) is applied to the second high data potential Vu2, the third power source Vs1 (1) is applied to the ground line control potential Vu3, and the fourth Power source Vs2 (1) is applied to the potential of the second power source Vss.

Next, a voltage of about the first power supply Vcc is applied to the word line WL (2), and the bit complementary line / BL (1) is applied.
Since the second high data potential Vu2 is applied to the first
Both the switch N3 and the second switch N24 are turned on.

As a result, since the bit line BL and the second storage node V2 are connected through the first switch N3, the potential of the second storage node V2 gradually increases to the ground potential Vx1.
Approach. Further, since the gate electrode of the first drive transistor N1 is connected to the second data holding node V2, the operation of the first drive transistor N1 stops when the voltage drops to the threshold voltage, and the first load Since the gate electrode of the transistor P1 is connected to the second storage node V2, the first load transistor P1 starts operating when its threshold voltage is exceeded.
The potential of 1 gradually approaches the first power supply Vcc and the write operation is completed. The storage node to be written is the first storage node V1 in the memory cell of the third embodiment, but is the same second storage node V2 as in the second embodiment in the present embodiment.

As a feature of this embodiment, during the write operation period, the first drive transistor N1 applies the ground line control potential Vu3 to the third power supply Vs1 when writing low data to the first storage node V1. By doing so, the ability to latch the signal potential of the first storage node V1 is reduced, so that it is possible to quickly write "0" to the first storage node V1.

The ground line control potential Vu3 is expressed by the equation 1
It is set to be equal to or higher than 00 mV and equal to or lower than the potential difference between the potential of the first power supply Vcc and the threshold voltage Vt of the first drive transistor.

The memory cell of this embodiment and the memory cell of the third embodiment are properly used, and when the noise margin is prioritized, the second switch N24 is not connected in series with the first drive transistor N1. When the memory cell of the present embodiment is used and the degree of integration is prioritized, the memory cell of the third embodiment including six transistors may be used.

A first modification of the fourth embodiment of the present invention will be described below with reference to the drawings.

FIG. 14B is a circuit diagram showing a part of the memory cell array according to the first modification of the fourth embodiment of the present invention. In FIG. 14B, the memory cells 41 and 42
14 and 43, the memory cells according to the fourth embodiment shown in FIG. 14A are connected to the same word line WL, and the fourth power source Vs2 (n-1) of the memory cell 41 and the memory cell 42 are connected.
Connected to the third power supply Vs1 (n) of the memory cell 42
The fourth power supply Vs2 (n) is connected to the third power supply Vs1 (n + 1) of the memory cell 43.

In the memory cell having the above-mentioned structure, as in the first modification of the third embodiment, the adjacent memory cells are the bit complementary lines / BL (n-1) and / BL (n + 1) serving as the write control lines. ) Is not selected, the second switch N24 of the adjacent memory cells 41 and 43 is off. Therefore, the potential difference between the third power source Vs1 and the fourth power source Vs2, that is, the ground line control potential Vu3, is expressed by the formula 1
It is possible to set the potential to be equal to or higher than 00 mV and equal to or lower than the potential difference between the potential of the first power supply Vcc and the threshold voltage Vt of the first drive transistor N1 or the second drive transistor N2.

A feature of this modification is that since the third power supply Vs1 and the fourth power supply Vs2 are shared by the memory cells adjacent to each other, the number of divided ground lines does not increase. The circuit element formation region of is not sacrificed by the divided ground line.

The second modification of the fourth embodiment of the present invention will be described below.

The second modification is similar to the first modification of the second embodiment in that the size of the first load transistor P1 is set smaller than that of the second load transistor P2.

As a feature of this modification, as in the first modification of the second embodiment, the first storage node V1 and the second storage node V2 are cut off from the bit line pair BL, / BL, respectively. Therefore, a very large noise margin is ensured at the time of read operation, and since it does not easily become small, the balance of the flip-flop circuit is disturbed,
The size of the first load transistor P1 can be reduced, and the write operation can be speeded up.

A third modification of the fourth embodiment of the present invention will be described below with reference to the drawings.

FIG. 15A is a circuit diagram showing a memory cell according to a third modification of the fourth embodiment of the present invention. Figure 15
In FIG. 14A, only the difference in configuration from the memory cell according to the fourth embodiment shown in FIG. 14A will be described. / BL, which is a complementary line to the bit line BL, is applied to the fourth power supply Vs2, WT is the second high data potential Vu2 during the write operation
The write control line is applied to the.

Second power supply Vss applied to fourth power supply Vs2
And the ground line control potential Vu3 are generated by the ground line control circuit B shown in FIG. 9, and the second high data potential Vu2 is the bit line control circuit A2 shown in FIG.
Is generated by.

The read operation and write operation of the third modified example are similar to those of the fourth embodiment, and will be omitted.

As a characteristic of this modification, as in the case of the fourth modification of the third embodiment shown in FIG. 10, writing in the case where more memory cells are connected in the column direction than in the row direction is written. During operation, the number of memory cells connected to the write control line WT is reduced, so the load capacity of the write control line WT is reduced, so that the power consumption of the memory cell is reduced and the write operation becomes faster. Furthermore, the first
When the write operation is performed by controlling the potential of the third power supply Vs1 which is the potential of the ground line of the driving transistor N1 of FIG. 9 by the ground line control circuit B shown in FIG.
The memory cell to be written is limited to the selected memory cell where the bit line BL and the write control line WT cross each other.
Incorrect writing can be prevented.

A fourth modification of the fourth embodiment of the present invention will be described below with reference to the drawings.

FIG. 11 is a schematic diagram showing a memory cell array according to a fourth modification of the fourth embodiment of the present invention. Figure 1
1, the configuration is such that when the memory cells according to the third modified example of the fourth embodiment are arranged in an array, one write control line WT is arranged for four word lines WL. The potential of the write control line WT is generated by the bit line control circuit A2 shown in FIG.

As shown in FIG. 11, the fifth embodiment of the third embodiment
As in the modified example, since the four write control lines WT are connected to the memory cells of different column addresses,
Since only the selected cell is the only memory cell that is simultaneously selected by the word line WL and the write control line WT,
Even if the potential of the third power supply Vs1 and the potential of the fourth power supply Vs2 change during the write operation, erroneous write to the unselected memory cells can be prevented.

A feature of this modification is that the write control line WT is not provided for each row address that is the same as that of the word line WL, but only one write control line WT is provided for four word lines WL. Since the number of lines WT can be reduced, the write control line WT does not sacrifice the circuit element formation region on the semiconductor substrate.

A fifth modification of the fourth embodiment of the present invention will be described below with reference to the drawings.

FIG. 15B is a circuit diagram showing a memory cell according to a fifth modification of the fourth embodiment of the present invention. Figure 1
FIG. 15B is newly added to the memory cell shown in FIG.
Only the components added to the memory cell shown in will be described. In FIG. 15B, N46 is a first drive transistor N1 between the first storage node V1 and the third power supply Vs1 in order to increase the write speed to the second storage node V2 during the write operation. A fourth switch connected in parallel and controlled by the bit line BL via the first switch N3.

The write operation of the memory cell configured as described above will be described below.

Only characteristic points as compared with the fourth embodiment will be described. Consider a case where "0" is written in the first storage node V1 and "1" is written in the second storage node. First, since the voltage of about the first power supply Vcc is applied to the word line WL and the second high data potential Vu2 is applied to the bit complementary line / BL, the first switch N3 and the second switch N are connected.
Both 14 are turned on.

Next, the bit line BL and the second storage node V
2 is connected through the first switch N3 and the second switch N24, the potential of the second storage node V2 is the first high data generated by the bit line control circuit A1 shown in FIG. It gradually approaches the potential Vu1. Also,
Since the potential of the gate electrode of the fourth switch N46 is higher than that of the second storage node V2, the first drive transistor N4
Since the fourth switch N46 starts to operate before 1 operates, the potential of the first storage node V1 rapidly approaches the ground potential of the second power supply Vss. Therefore, the second
Drive transistor N2 rapidly stops operating, and
The load transistor P2 of 3) rapidly becomes low impedance, and the write operation can be performed faster than in the fourth embodiment.

A sixth modification of the fourth embodiment of the present invention will be described below with reference to the drawings.

FIG. 2A shows a sixth embodiment of the fourth embodiment of the present invention.
The electric potential of the power supply of the memory cell which concerns on a modification is shown. The present embodiment is configured to have the memory cell of the fourth embodiment in place of the memory cell 1 of the fourth modification of the first embodiment.

A feature of this embodiment is that the flip-flop connected group of transistors has a potential of the sixth power source Vm lower than the potential of the first power source Vcc even during the read operation. Is applied to the potential of the second power supply Vss, and the bit complementary line / BL
Further, since the potential of the first power source Vcc and the potential of the degree of identification similar to those of the fourth embodiment are applied, stable operation can be performed.

Further, since the potential of the sixth power source Vm intermediate between the first power source Vcc and the second power source Vss is applied to the common source line of the memory cell, the signal potential latching ability is lowered. Therefore, the write operation becomes faster.

A seventh modification of the fourth embodiment of the present invention will be described below with reference to the drawings.

FIG. 2B shows a seventh embodiment of the fourth embodiment of the present invention.
The electric potential of the power supply of the memory cell which concerns on a modification is shown. 2B, the step-down circuit shown in FIG. 2A is replaced with the memory cell according to the fourth embodiment.

FIG. 16 is a circuit diagram showing a memory cell according to a seventh modification of the fourth embodiment of the present invention. FIG.
The memory cell in (a) corresponds to the memory cell 2 shown in FIG. 2 (b), and the memory cell has a configuration of the transistor corresponding to each transistor of the memory cell according to the fourth embodiment shown in FIG. 14 (a). It is set to the opposite conductivity type to the conductivity type. The memory cell in FIG. 16B is the same as that in FIG.
1 corresponds to the memory cell 1 shown in FIG.
This is similar to the memory cell according to the fourth embodiment shown in FIG.

As a feature of this modification, as in the eighth modification of the third embodiment, in the memory cell 1, the load transistors P1 and P2 and the drive transistors N1 and N2 connected in a flip-flop are operated at a low voltage. , Word line W
Since Ln and the pair of bit lines BLn, / BLn are controlled by the potential which is not stepped down like the fourth embodiment, stable operation can be performed.

In the memory cell 2, the load transistors N1 and N2 and the drive transistors P1 and P2 connected in the flip-flop operate at a low voltage, and the word line W
Since Lp and the bit line pair BLp, / BLp are controlled by the same non-stepped down potential as in the fourth embodiment, stable operation can be performed.

Further, the memory cell 1 and the memory cell 2
Since the potential of the sixth power source Vm is applied to the common source line, the ability to latch the signal potential is reduced.
Write operation becomes faster.

An eighth modified example of the fourth embodiment of the present invention will be described below with reference to the drawings.

FIG. 4 is a schematic diagram showing a memory cell array according to an eighth modification of the fourth embodiment of the present invention.

FIG. 5 is a timing chart for reading data from the memory cell array according to the eighth modification of the fourth embodiment of the present invention.

In FIG. 4A, the memory cell is shown in FIG.
The memory cells of the fourth embodiment shown in (a) are arranged in an array of 4 rows × 16 columns, WL is a word line, BL is a bit line, and / BL is a bit complementary line which becomes a write control line at the time of writing. . The description of FIGS. 4B, 4C, and 5 is the same as that of the sixth modified example of the first embodiment, and will not be repeated.

As a feature of this modification, as in the sixth modification of the first embodiment, the memory cell connected to the activated word line WL penetrates because the storage node is cut off from the bit line BL. Since memory cells that do not flow current and consume no power for precharging use less power per memory cell, the number of word lines can be reduced. Can be shortened.

The fifth embodiment of the present invention will be described below with reference to the drawings.

FIG. 17A is a circuit diagram showing a memory cell according to the fifth embodiment of the present invention. In FIG. 17A, only the components different in configuration from the conventional memory cell shown in FIG. 28 will be described. N54 is controlled by the potential of the second storage node V2 and the first storage node V1 is connected to the bit line. A second switch for cutting off from BL, N55 is a third switch which is controlled by the potential of the first storage node V1 and cuts off the second storage node V2 from the complementary bit line / BL, and N56 activates the word line WL. The fourth switch that enables the write operation to the second storage node V2 by the complementary bit line / BL when it is turned on, Vsm is the fifth power supply serving as the reference potential for operating the memory cell, and V53 is the first power supply. Connection point between the first drive transistor N1 and the first switch N3, V54 is the second drive transistor N2
And the third switch N55.

The second switch N54 is connected in series between the first load transistor P1 and the first drive transistor N1, and the third switch N55 is connected to the second load transistor P2 and the second drive transistor N2. And are connected in series.

The first drive transistor N1 and the second switch N54 form a pair with the second drive transistor N2 and the third switch N55, and the first load transistor P1 and the second load transistor P2 form a pair. None, these transistor groups are flip-flop connected.

The first storage node V1 is connected to the first load transistor P1 and is also connected to the fifth power supply Vsm via the second switch N54 and the first drive transistor N1.

The second storage node V2 is connected to the second load transistor P2, and is also connected to the fifth power supply Vsm via the third switch N55 and the second drive transistor N2.

The operation of the memory cell configured as described above will be described below with reference to the drawings. FIG. 19A is a timing chart during operation of the memory cell according to the fifth embodiment of the present invention. In FIG. 19A, Vcc is the potential of the first power supply that controls the read operation and write operation of the memory cell, and Vss is the potential of the second power supply that is the ground potential that controls the read operation and the write operation of the memory cell. ,
Vsm is the potential of the fifth power supply, which is a reference potential that is approximately one half of the potential Vcc of the first power supply that controls the read operation and write operation of the memory cell, and V1 is the potential of the first storage node of the memory cell. , V2 is the potential of the second storage node of the memory cell, WLn is the potential of the word line, BLn and / BLn
Is the potential of the bit line and the bit complementary line.

First, the operation during the read period of the memory cell according to this embodiment will be described.

First, the first storage node V1 holds "1", that is, the potential of the first power supply Vcc, and the second storage node V2 holds "0", that is, the potential of the fifth power supply Vsm. Suppose Since the operation of each control circuit of the memory cell is the same as that of the first embodiment, only the memory cell will be focused and described.

First, when the potential of the word line WLn rises and the first switch N3 and the fourth switch N56 are turned on, the first connection point V53 is connected to the bit line BLn and the second connection point V54 is connected to the bit. Connected to complementary line / BLn.

Next, the potential of the second storage node V2 is the fifth
Because of the potential of the power source Vsm, the first driving transistor N1 is not operating sufficiently, and the bit line BLn is connected to the fifth power source Vsm with high impedance. On the other hand, since the bit complementary line / BLn is connected to the second connection point V54 and the second drive transistor N2 is operating sufficiently,
It is connected to the fifth power supply Vsm with an impedance lower than that of the bit line BLn. Therefore, the bit line pair BLn, / BL
The difference in the electrical characteristics between n depends only on the data held in the first storage node V1 and appears as the difference in the impedance characteristics, so that a stable read operation is possible.

A feature of this embodiment is that the first storage node V1 is cut off from the bit line by the second switch N54, so that the potential of the storage node V1 does not rise at the time of reading. No through current flows from the power supply Vcc to the fifth power supply Vsm through the second drive transistor N2. Therefore, a stable read operation is possible and unnecessary power is not consumed.

Further, unlike the conventional case, the signal potential of the held data is not read as the potential difference between the bit line pair BLn, / BLn, and both the bit line pair BLn, / BLn are applied to the ground potential. The electric power used for is unnecessary.

Furthermore, the minimum voltage to be secured as the read current for impedance detection is the bit line pair BLn,
As the difference between the impedance characteristics of / BLn can be detected, the voltage at which the first drive transistor N1 and the second drive transistor N2 operate becomes the threshold voltage of the transistor, which allows low voltage operation. .

Next, the operation of the memory cell according to this embodiment during the write period will be described.

First, "0" is stored in the first storage node V1.
It is assumed that “1” is written in the second storage node V2.

Next, as shown in the writing period of FIG. 19A, the word line WLn selected by the latched address rises and the potential of the bit complementary line / BLn is applied to the potential of the first power source Vcc. Then, the potential of the bit line BLn is applied to the potential of the second power supply Vss.

Next, the word line WLn is supplied with the first power source Vcc.
A voltage of about a certain degree is applied to turn on both the first switch N3 and the fourth switch N56.

Next, the bit complementary line / shown in FIG.
BLn and the first Vcc of the first power source are held
Since the second storage node V2 is connected through the activated third switch N55 whose gate electrode is connected to the second storage node V1, the potential of the second storage node V2 is gradually changed to the first power supply. It approaches the potential of Vcc.

The second switch N54 having the gate electrode connected to the second storage node V2 starts to operate when the potential of the gate electrode exceeds the threshold voltage, and becomes "0".
Of the storage node V1 and the bit line BLn applied to a potential lower than the potential of the fifth power supply Vsm, which is the reference potential of
19 is connected through the switch N3 and the second switch N54, and as shown in FIG.
The potential of 1 gradually exceeds the potential Vsm of the fifth power source and approaches the potential Vss of the second power source. At the same time, since the gate electrode of the first drive transistor N1 is connected to the second storage node V2, when the potential of the gate electrode exceeds the threshold voltage, the first drive transistor N1 starts to operate and
Storage node V1 is connected to the fifth power supply Vsm, and the gate electrode of the first load transistor P1 is connected to the second storage node V2, the potential of the gate electrode of the first load transistor P1 is When the voltage exceeds the threshold voltage and becomes higher, the operation is stopped, so that the first storage node V1
Is cut off from the first power supply Vcc.

The gate electrodes of the second drive transistor N2 and the third switch N55 are connected to the first storage node V1.
Since the potential is lower than the threshold voltage, the second drive transistor N2 and the third switch N55 stop operating, and the second storage node V2 is connected to the fifth power supply Vsm. And the gate electrode of the second load transistor P2 is connected to the first storage node V1, the potential of the gate electrode of the second load transistor P2 exceeds the threshold voltage and becomes low. Since the operation starts, the second storage node V2 is connected to the first power supply Vcc and the write operation is completed.

As a feature of this embodiment, when writing "0", the bit line BL is applied to the potential of the second power supply Vss lower than the potential of the fifth power supply Vsm which is the reference potential of "0". Therefore, "0" can be written at a high speed, and therefore the write operation of "1", which is the complementary value, can be speeded up.

Further, the fifth drive transistor N1 and the second drive transistor N2 forming the cross-coupled transistor are connected to the common ground line of the fifth drive transistor N1.
Since the power supply Vsm of the first power supply is approximately one half of the potential Vcc of the first power supply, the latching capability of the signal potentials of the first drive transistor N1 and the second drive transistor N2 is reduced, so that the write operation is faster. Shows a tendency to become.

A first modification of the fifth embodiment of the present invention will be described below with reference to the drawings.

FIG. 18 is a circuit diagram showing a memory cell according to a first modification of the fifth embodiment of the present invention. In FIG. 18, only the difference in configuration from the memory cell according to the fifth embodiment shown in FIG. 17A will be described. Vs1 is a third power supply to which the ground line of the first drive transistor N1 is connected, Vs2 Is a fourth power supply to which the ground line of the second drive transistor N2 is connected.

FIG. 9 is a circuit diagram of the ground line control circuit according to the first modification of the fifth embodiment of the present invention. The ground line control circuit shown in FIG. 9 is a control circuit used in common with the third and fourth embodiments, and therefore its description is omitted.

The memory cell configured as described above will be described below.

The description of the read operation is omitted because it is the same as that of the fifth embodiment, and the description of the write operation is only different from that of the fifth embodiment.

First, "0" is stored in the first storage node V1,
It is assumed that “1” is written in the second storage node V2.

Next, the word line WL selected by the latched address rises, and in the ground line control circuit B shown in FIG. 9, the write request WE is "1" and the write data Din is "1". , The potential of the second power supply Vss is generated on the first front ground line pVs1 (k), and the ground line control potential Vu3 is generated on the second front ground line pVs2 (k).

As a result, the potential of the bit complementary line / BL is applied to the potential of the first power source Vcc and the third power source Vcc.
s1 is applied to the potential of the second power source Vss, and the fourth power source Vs2 is applied.
Is applied to the ground line control potential Vu3.

Next, since a voltage about the potential of the first power source Vcc is applied to the word line WL, both the first switch N3 and the fourth switch N56 are turned on.

Next, as in the fifth embodiment, since the bit complementary line / BL and the second storage node V2 are connected through the activated third switch N55, the second storage node V2 is connected.
Of the storage node V2 gradually approaches the potential of the first power supply Vcc.

Further, the bit line BL and the storage node V1 applied to the potential of the second power source Vss which is the reference potential of "0".
Are connected through the first switch N3 and the second switch N54, and the potential of the first storage node V1 gradually approaches the potential of the second power supply Vss.

As a feature of this modification, as in the fifth embodiment, during the write operation period, the second load transistor P2, the third switch N55, and the second drive transistor N2 have the second storage node V2. Is operating during the transition period until the potential of the
A through current flows from cc to the fourth power source Vs2. However, a fourth power supply V connected to the second storage node
By setting the potential of s2 higher than that of the second power supply Vss, which is the ground potential, the on resistance of the second drive transistor N2 is increased, so that the through current flowing through the second drive transistor N2 is suppressed. Therefore, the writing operation becomes faster.

The ground line control potential Vu3 is expressed by the equation 1
It is set to be equal to or higher than 00 mV and equal to or lower than the potential difference between the potential of the first power supply Vcc and the threshold voltage Vt of the second drive transistor.

A second modification of the fifth embodiment of the present invention will be described below with reference to the drawings.

FIG. 17 is a circuit diagram showing a memory cell according to a second modification of the fifth embodiment of the present invention. FIG. 17
Since the memory cell shown in (a) is the same as that used in the fifth embodiment, its explanation is omitted. In FIG. 17B, Vsm is a fifth power supply serving as a reference potential that is a potential that is approximately one half of the potential of the first power supply Vcc that drives the memory cell, and Vss is the ground that drives the memory cell. It is a second power source which becomes a potential, and each transistor has a configuration in which the conductivity type of each transistor corresponding to the memory cell shown in FIG. 17A is inverted.

The second modified example is shown in FIGS.
It is assumed that the memory cells of (b) are connected in two stages in series, as in the fifth modification of the first embodiment.

The operation of the memory cell configured as described above will be described below with reference to the drawings. FIG. 19A shows FIG.
FIG. 19B is a timing chart at the time of operation of the memory cell according to the second modification shown in FIG. 7A, and FIG.
9 is a timing chart at the time of operation of the memory cell according to the second modified example shown in (b).

Since the read operation and write operation of the memory cell according to the second modification shown in FIG. 17A are the same as those in the fifth embodiment, description thereof will be omitted.

Since the timing chart of the memory cell shown in FIG. 19B has a negative logic, "0" is held in the first memory node V1 and "1" is held in the second memory node V2 during the read period. ”Is held,
In the writing period, "1" is written in the first storage node V1 and "0" is written in the second storage node V2.

The read operation and the write operation of the memory cell according to the second modification shown in FIG. 17B operate at the potential of the second power supply Vss, which is the ground potential, because the drive transistor is a P-type transistor. Other than the above, it is the same as the fifth embodiment.

As a feature of this modification, as in the fifth modification of the first embodiment, in the memory cell shown in FIG. 17A, a transistor group N flip-flop connected.
Nos. 1, N2, N54, N55, P1 and P2 have a driven potential which is about ½ of the potential of the first power source Vcc.
Of the power source Vsm, the word line WLn is applied to the potential of the first power source Vcc and the bit line pair BLn, / BLn is applied to the potential of the fifth power source Vsm during the read operation. . In the write operation, the word line WLn of the transistor group is applied to the same potential of the first power supply Vcc as in the first embodiment, and the bit line BLn and the bit complementary line / BLn are set to the reference potential. Half of the potential of the first power source Vcc centering on the potential Vsm of the power source
Since the voltage difference is applied in increments and decrements, the potential difference between them is applied to the potential of the first power source Vcc which is substantially the same as that in the first embodiment, so that the memory cell according to the present embodiment operates stably. You can

The memory cell shown in FIG. 17B is
Since the conductivity type of the transistor is inverted from that of the memory cell shown in FIG. 17A, all the potentials driven and controlled by the transistors are inverted, so that the memory cell shown in FIG. It can operate stably.

The third modification of the fifth embodiment of the present invention will be described below.

FIG. 17A is a circuit diagram showing a memory cell according to a third modification of the fifth embodiment of the present invention, which has the same structure as that used in the fifth embodiment.

In this modification, the operation speed is increased by adjusting the set value of the threshold voltage of the transistor of each component.

For example, if the threshold voltage of each transistor is represented by Vt (transistor name), the threshold voltage of each transistor of each memory cell is Vtp (P1) = Vtp (P2) =-0.5V, Vtn (N54) = Vtn (N55) = 0.5V, Vtn (N1) = Vtn (N2) = 0.1V, Vtn (N3) = Vtn (N56) = 0.1V.

By doing so, the first drive transistor N1 and the first switch transistor N3 which define the high-speed read operation are quickly activated, so that the high-speed read operation can be achieved.

Further, the standby current consumed in the state where neither the read operation nor the write operation is performed, the threshold voltage of the second switch transistor N54 and the third switch transistor N55 is as high as 0.5V, Even with a megabit-class storage device,
It can be kept below microamperes.

In the case of the inversion type memory cell shown in FIG. 17B, the threshold voltage of each transistor of each memory cell is Vtn (N1) = Vtn (N2) = 0.5V, Vtp (P54 ) = Vtp (P55) =-0.5V, Vtp (P1) = Vtp (P2) =-0.2V, Vtp (P3) = Vtp (P56) =-0.2V.

A fourth modification of the fifth embodiment of the present invention will be described below with reference to the drawings.

FIG. 20A is a circuit diagram showing a memory cell according to a fourth modification of the fifth embodiment of the present invention. Figure 1
Only the components newly added to the memory cell shown in FIG. 7A will be described. In FIG. 20A, BLr is a read bit line as a read-only first control line,
/ BLr is a read bit complementary line as a second read-only control line, WLr is a read word line as a third read-only control line, and BLw is a write-only first control line as a write-only first control line. Bit line, / BLw
Is a write bit complementary line as a write-only second control line, WLw is a write word line as a write-only third control line, and N81 is a write bit line activated by a write-only word line WLw. A write-only fifth switch N82 connected in series between BLw and the first storage node V1 is activated by the write-only word line WLw, and a write bit complementary line /
A sixth write-only switch connected in series between BLw and the second storage node V2.

The memory cell of this modification is a 2-port SRAM capable of simultaneously executing a read operation and a write operation.
Is.

Also in the memory cell of this modification, it is possible to speed up the operation by adjusting the set value of the threshold voltage of each transistor.

For example, the threshold voltage of each transistor of each memory cell is Vtp (P1) = Vtp (P2) =-0.5V, Vtn (N54) = Vtn (N55) = 0.5V, Vtn (N1) = Vtn (N2) = 0.1V, Vtn (N3) = Vtn (N56) = 0.1V Vtn (N81) = Vtn (N82) = 0.1V.

In the memory cell of this modification, the read-only first switch N3 and the first drive transistor N1 are connected in series, and the fourth switch N56 and the second drive transistor N2 are connected in series. And the write-only fifth switch N81 and the first storage node V
1 is connected, and the sixth switch N82 and the second storage node V2 are connected.

With this configuration and the setting of the threshold voltage,
The first storage node V1 and the first connection point V53 connected to the read bit line BLr at the time of reading are disconnected, and are connected to the second storage node V2 at the read bit complementary line / BLr at the time of the read operation. Second connection point V5
Since 4 and 4 are separated, the writing speed can be increased while increasing the static noise margin at the time of reading.

In the case of the inversion type memory cell shown in FIG. 20B, the threshold voltage of each transistor of each memory cell is Vtn (N1) = Vtn (N2) = 0.5V, Vtp (P54 ) = Vtp (P55) =-0.5V, Vtp (P1) = Vtp (P2) =-0.2V, Vtp (P3) = Vtp (P56) =-0.2V Vtp (P81) = Vtp (P82) It may be set as follows: = -0.2V.

A sixth embodiment of the present invention will be described below with reference to the drawings.

FIG. 21A is a circuit diagram showing a bit line control circuit according to the sixth embodiment of the present invention. Figure 21
25A, WE is a write request notified by the read / write switching control circuit shown in FIG. 25, Din is write data notified by the input / output data control circuit shown in FIG. 25, and pBL (k) is shown in FIG. a) The multiplexed previous bit line for applying to the bit line of the memory cell through the bit line selection circuit DSW1 shown in a), / pBL
(K) is a multiplexed previous bit complementary line for applying to the bit complementary line / BL of the memory cell through the bit line selection circuit DSW1, and Vu1 is the previous bit line pBL (k).
Is a first high data potential applied to the first bit, Vu2 is a second high data potential applied to the previous bit complementary line / pBL (k), Vu2
x1 is the previous bit line pBL (k) or the previous bit complementary line / pB
Ground potential applied to L (k), P61 is write request W
A first P-type switch that opens and closes the first high data potential Vu1 according to the complementary value of E, P62 is a second P-type switch that opens and closes the first high data potential Vu1 according to the write data Din, and N61. Is a first N-type switch that opens and closes the ground potential Vx1 according to the write data Din, N62 is a second N-type switch that opens and closes the ground potential Vx1 according to the write request WE, and N63 is a complementary value of the write request WE. A third N-type switch that opens / closes the ground potential Vx1 in response, a P63 is a third P-type switch that opens / closes the second high data potential Vu2 in accordance with the complementary value of the write request WE, and a gate electrode of P64 is grounded. The fourth P-type switch that is always closed because it is open, the N64 is the fourth N-type switch that is always open because the gate electrode is grounded, and the N65 is the ground potential V in response to the write request WE. A fifth N-type switch that opens and closes x1 is a sixth N-type switch that opens and closes the ground potential Vx1 according to the complementary value of the write request WE.

The operation of the bit line control circuit A1 having the above structure will be described below.

As shown in FIG. 29 or 30, in the present embodiment, the write request WE has a positive logic.

First, when the write request WE is "1",
That is, the operation of the bit line control circuit A1 during the writing period will be described.

When the write data Din is "1", the first P-type switch P6 on the previous bit line pBL (k) is
1, the first N-type switch N61 and the second N-type switch N62 are closed and the other switches are opened, so that the previous bit line p
BL (k) is applied to the ground potential Vx1, and the third P-type switch P63 and the fourth P-type switch P64 in the previous bit complementary line / pBL (k) are closed and the other switches are opened, so that the previous bit is opened. The complementary line / pBL (k) is applied to the second high data potential Vu2. By the ground potential Vx1 applied to the previous bit line pBL (k), "0" is written in the storage node to be written in the memory cell.

When the write data Din is "0", the first P-type switch P6 on the previous bit line pBL (k) is
Since the first and second P-type switch P62 and the second N-type switch N62 are closed and the other switches are opened, the previous bit line p
BL (k) is applied to the first high data potential Vu1, and the third P-type switch P63 and the fourth P-type switch P64 in the previous bit complementary line / pBL (k) are closed and the other switches are opened. Therefore, the previous bit complementary line / pBL (k) is applied to the second high data potential Vu2. Previous bit line p
Since the first high data potential Vu1 applied to BL (k) is applied to the potential of the first power supply Vcc or its boosted potential Vpp, "1" is applied to the storage node to be written in the memory cell. Will be written.

Next, when the write request WE is "0",
That is, the case of the read period will be described.

When the write data Din is "1", the first N-type switch N6 on the previous bit line pBL (k) is
Since the first and third N-type switches N63 are closed and the other switches are opened, the front bit line pBL (k) is applied to the ground potential Vx1 and the fourth P-type switch is applied to the front bit complementary line / pBL (k). Switch P64 and sixth N-type switch N66
Is closed and other switches are opened, so the previous bit complementary line / p
BL (k) is applied to the ground potential Vx1. Therefore, the previous bit line pBL is read by the ground potential Vx1 during the read period.
Both (k) and the previous bit complementary line / pBL (k) are at the ground potential.

When the write data Din is "0", the second P-type switch P6 on the previous bit line pBL (k) is
Since the second and third N-type switches N63 are closed and the other switches are opened, the front bit line pBL (k) is applied to the ground potential Vx1, and the fourth P-type in the front bit complementary line / pBL (k) is Switch P64 and sixth N-type switch N66
Is closed and other switches are opened, so the previous bit complementary line / p
BL (k) is applied to the ground potential Vx1.

Therefore, due to the ground potential Vx1, the previous bit line pBL (k) and the previous bit complementary line / pB are read during the read period.
Both L (k) are at the ground potential.

As a feature of this embodiment, during the write period, the ground potential Vx1 or the first high data potential Vu1 which becomes the write data to be applied to the bit line BL of the memory cell.
Is generated and serves as a write control line. Bit complementary line / BL
A second high data potential Vu2 for control applied to the bit line pair BL, / is generated during the read period.
The ground potential Vx1 applied to BL is generated.

The bit line control circuit A1 according to this embodiment is the fourth modification of the third embodiment, the fifth modification of the third embodiment, the third modification of the fourth embodiment, and the fourth modification of the fourth embodiment. Four
It is used in all the memory cells of the first to fourth embodiments except the modified example.

A first modification of the sixth embodiment of the present invention will be described below with reference to the drawings.

FIG. 21B is a circuit diagram showing a bit line control circuit according to a first modification of the sixth embodiment of the present invention. 21B, only the difference from the bit line control circuit A1 shown in FIG. 21A will be described. Figure 21 for WT
It replaces the preceding bit complementary line / pBL (k) in (a), and is a fourth modified example of the third embodiment, a fifth modified example of the third embodiment, a third modified example of the fourth embodiment, and a fourth modified example. In the memory cell according to the fourth modification of the fourth embodiment, the write control line serves as the second control line during the write operation.

Since the operation of the bit line control circuit A2 according to the first modification is similar to that of the bit line control circuit A1 according to the sixth embodiment, the description thereof will be omitted.

The seventh embodiment of the present invention will be described below with reference to the drawings.

FIG. 22A is a circuit diagram showing a sense amplifier according to the seventh embodiment of the present invention. In FIG. 22A, RD (k) is the bit line BL decoded by the column decoder from the selection circuit DSW3 in the preceding stage of the sense amplifier shown in FIG. 28A or 28B during the read operation.
Common data line for capturing data of (n), / RD (k)
Is also the bit complementary line / BL decoded by the column decoder from the selection circuit DSW3 in the preceding stage of the sense amplifier.
The common data reference line for fetching the data (n), XSA, is activated only in the first half of the read period, and the common data line R
The activation signal of the sense amplifier that serves as a trigger for detecting the impedance of D (k) and the common data reference line / RD (k), EQ is activated only in the latter half of the read period, and the difference in impedance characteristics is converted into a potential difference. , An equalizing signal of the bit line that serves as a trigger to precharge the bit line pair BL (n), / BL (n) to the ground potential, Vcc is the first power supply for operating the sense amplifier, and Vx1 is for operating the sense amplifier. , Bit line pair BL (n), / BL (n)
Ground potential for precharging, P71 is the first load transistor of one inverter, P72 is the second load transistor of the other inverter paired with the first load transistor P71, and N71 is the first load transistor of the one inverter. Drive transistor, N72 is the first drive transistor N7
The second drive transistor N73 of the other inverter paired with 1 is activated by the activation signal XSA of the sense amplifier and is activated by the first power supply Vcc and the common data reference line / RD.
The third transistor N74, which is a first transistor of the first conductivity type and is connected to (k), is activated by the activation signal XSA of the sense amplifier, and is connected to the first power supply Vcc and the common data line RD (k). A fourth transistor P75 as a second transistor of the first conductivity type for connecting the first power source Vcc, the first load transistor N71 and the second load transistor N71 is activated by a complementary signal of the activation signal XSA of the sense amplifier. The fifth transistor as the first transistor of the second conductivity type, which is connected to the common source electrode of the load transistor N72 of
, N76 is a bit line equalize signal E
A first switch that is activated by Q to apply the common data reference line / RD (k) to the ground potential Vx1, N77 is activated by the equalization signal EQ of the bit line and makes the common data line RD (k) the ground potential. Second for applying to Vx1
, PDout is the output of a sense amplifier that converts the difference in the impedance characteristics of the common data line RD (k) into a potential difference and outputs it, / pDout is the common data reference line / RD
The reference output of the sense amplifier that converts the difference in the impedance characteristics of (k) into a potential difference and outputs the potential difference, N78 is a sixth transistor that converts the output pDout of the sense amplifier to an appropriate potential, and N79 is the reference output of the sense amplifier / pDout. The seventh transistor, Dout, which converts the voltage to an appropriate potential is shown in Fig. 2.
5, read data sent to the input / output data control circuit, / Dout is read reference data also sent to the input / output data control circuit.

The selection circuit DSW3 in the preceding stage of the sense amplifier shown in FIG. 28 (b) is activated by the sense amplifier activation signal XS.
When A is activated, the potential of the common data reference line / RD (k), which is the reference potential of the common data line RD (k), is intermediate between the first power supply Vcc and the second power supply Vss. Thus, the dummy cell is provided on the common data reference line / RD (k).

The operation of the sense amplifier configured as described above will be described below. In FIG. 29, the rising direction of all signals is called high and the falling direction is called low.
In the first half of the read period of the timing chart shown in FIG. 29, first, the activation signal XSA of the sense amplifier becomes high and the equalization signal EQ of the bit line becomes low. FIG. 22 shows the circuit at this time as an equivalent circuit.
It is (b).

In FIG. 22 (b), the same reference numerals as those of the components shown in FIG. 22 (a) are attached. Common data line R
D (k) is connected to the bit line BL selected by the selection circuit DSW3 in the previous stage of the sense amplifier shown in FIG. 28A, and the common data reference line / RD (k) is selected by the selection circuit DSW3 in the previous stage of the sense amplifier. Bit complementary line / B
L is connected.

As described above, this sense amplifier injects the current for impedance detection from the sense amplifier side only to the selected bit line pair BL, / BL in the first half of the read period.

Output pair of sense amplifier pDout and / pD
The potential of out is determined by the resistance ratio between the third transistor N73 and the fourth transistor N74 and the first drive transistor N71 and the second drive transistor N72. Therefore, for example, the bit line BL selected as the common data line RD (k) is connected with a low impedance at the ground level, and the bit complementary line / BL selected as the common data reference line / RD (k) has a low impedance. Then, assuming that they are not connected, that is, in a floating state, as shown in FIG.
As shown in, even if the bit line pair BL and / BL are both applied to the ground potential, the common data line RD (k) on the low impedance side is more likely than the common data reference line / RD (k) on the high impedance side. Since a large amount of current flows, the potential of the output pDout of the sense amplifier has a large voltage drop, which is lower than the reference output / pDout of the sense amplifier. As shown in FIG. 29, the potential difference between the output pair pDout and / pDout of the sense amplifier in the first half of the reading period is very small.

Next, in the latter half of the read period shown in FIG. 29, the sense amplifier activation signal XSA goes low and the bit line equalize signal EQ goes high. FIG. 22C shows the circuit at this time as an equivalent circuit.

In FIG. 22 (c), the same reference numerals as the constituent elements shown in FIG. 22 (a) are attached. As shown in FIG. 22C, the first load transistor P71, the second load transistor P72, and the first drive transistor N7.
The flip-flop circuit constituted by the first and second drive transistors N72 is activated, and the potential of the output pair pDout and / pDout of the sense amplifier is converted into the potential of the complementary MOS level. As shown in FIG. 29, the output pair pDout and /
The potential difference of pDout is amplified.

Also, the common data line pair RD (k) and / R
By applying the ground potential Vx1 to D (k), the charges injected for impedance detection are discarded.

Only in the case of the fourth modification of the third embodiment of the present invention and the third modification of the fourth embodiment, the common data reference line / RD (k) is set to the potential of the fourth power supply Vs2. Is applied.

As a feature of this embodiment, in the first half of the read period, for the bit line pair BL, / BL selected by the column decoder of the selection circuit DSW3 in the preceding stage of the sense amplifier shown in FIG. Injecting current for impedance detection from the sense amplifier side only
Of the current between the bit line pair BL, / BL caused by the transistor N73 and the fourth transistor N74 of the sense amplifier is detected to generate a potential difference between the output pair pDout and / pDout of the sense amplifier. By amplifying with a flip-flop circuit,
The desired read data pair Dout and / Dout is generated, and the injected charges are discarded with the selected bit line pair BL, / BL as the ground level.

As described above, according to the semiconductor integrated circuit device of the present invention, the power consumption can be reduced and the bit power can be reduced by setting the precharge potential of the bit line which is an obstacle to the low power consumption to the ground potential. In order to prevent the potential loss of the storage node of the memory cell caused by setting the line to the ground potential, the bit line and the storage node are cut off by a switch transistor. As a result, it becomes possible to suppress the through current of the memory cell at the time of reading.

The signal potential can be read by injecting a current from the sense amplifier side only to the memory cell selected so that the impedance can be detected.
The power consumption can be further reduced, and the read operation can be performed at high speed.

On the other hand, since the potential of the source line of the memory cell is applied in the direction of weakening the latching ability of the signal potential of the storage node, the writing operation can be performed at high speed.

[0434]

According to the first semiconductor integrated circuit device of the present invention, by detecting the impedance value of the selected memory cell, the data of the memory cell is determined, so that a high-speed read operation is possible. .

Furthermore, since precharging is unnecessary,
Low power consumption can be achieved.

According to the second semiconductor integrated circuit device of the present invention, at least the transistor in the on-state of the transistor pair is in the off-state than the other transistors, so that the signal potential latching capability is deteriorated. Therefore, the balance of the signal potentials of the storage node pair is quickly lost, and as a result, the write operation can be performed at high speed.

[Brief description of drawings]

FIG. 1A is a circuit diagram showing a memory cell according to a first embodiment of the present invention. (B) is a circuit diagram showing a memory cell according to a third modification of the first embodiment of the present invention.

2A is a fourth modification of the first embodiment of the present invention, FIG.
It is a figure which shows the electric potential of the power supply of the memory cell which concerns on the 3rd modification of 2nd Embodiment, the 7th modification of 3rd Embodiment, and the 6th modification of 4th Embodiment. (B) is a memory cell according to a fifth modified example of the first embodiment of the present invention, a fourth modified example of the second embodiment, an eighth modified example of the third embodiment, and a seventh modified example of the fourth embodiment. It is a figure which shows the electric potential of the power supply of.

3 (a) and 3 (b) are a fifth embodiment of the present invention.
It is a circuit diagram which shows the memory cell which concerns on a modification.

FIG. 4A is a sixth modification of the first embodiment of the present invention,
It is a schematic diagram which shows the memory cell array which concerns on the 5th modification of 2nd Embodiment, the 9th modification of 3rd Embodiment, and the 8th modification of 4th Embodiment, (b) is a conventional word line and bit. FIG. 3 is a circuit diagram of a gate array for decoding lines,
(C) is a circuit diagram of a gate array for decoding word lines and bit lines according to the present invention.

FIG. 5 is a sixth modification of the first embodiment of the present invention, a fifth modification of the second embodiment, a ninth modification of the third embodiment, and a fourth modification.
It is a figure which shows the timing chart at the time of reading data from the memory cell array which concerns on the 8th modification of embodiment.

FIG. 6A is a circuit diagram showing a memory cell according to a second embodiment of the present invention. (B) is a circuit diagram showing a memory cell according to a second modification of the second embodiment of the present invention.

7 (a) and 7 (b) are a fourth embodiment of the second embodiment of the present invention.
It is a circuit diagram which shows the memory cell which concerns on a modification.

FIG. 8A is a circuit diagram showing a memory cell according to a third embodiment of the present invention. (B) is a circuit diagram showing a part of a memory cell array according to a first modification of the third embodiment of the present invention.

FIG. 9 is a third embodiment, a fourth embodiment and a fifth embodiment of the present invention.
It is a circuit diagram which shows the control circuit of the ground line which concerns on the 1st modification of embodiment.

FIG. 10 is a circuit diagram showing a memory cell according to a fourth modification of the third embodiment of the present invention.

FIG. 11 is a schematic diagram showing a memory cell array according to a fifth modification of the third embodiment of the present invention and a fourth modification of the fourth embodiment.

FIG. 12 is a circuit diagram showing a memory cell according to a sixth modified example of the third embodiment of the present invention.

13A and 13B are circuit diagrams showing a memory cell according to an eighth modified example of the third embodiment of the present invention.

FIG. 14A is a circuit diagram showing a memory cell according to a fourth embodiment of the present invention. FIG. 16B is a circuit diagram showing a part of the memory cell array according to the first modification of the fourth embodiment of the present invention.

FIG. 15A is a circuit diagram showing a memory cell according to a third modification of the fourth embodiment of the present invention. (B) is a circuit diagram showing a memory cell according to a fifth modification of the fourth embodiment of the present invention.

16A and 16B are circuit diagrams showing a memory cell according to a seventh modified example of the fourth embodiment of the present invention.

FIG. 17A is a circuit diagram showing a memory cell according to a fifth embodiment of the present invention and a second modification of the fifth embodiment. (B) is a circuit diagram showing a memory cell according to a second modification of the fifth embodiment of the present invention.

FIG. 18 is a circuit diagram showing a memory cell according to a first modification of the fifth embodiment of the present invention.

19A is a diagram showing a timing chart at the time of operation of the memory cell according to the second modification of the fifth embodiment of the present invention shown in FIG. 17A. FIG. FIG. 17B is a diagram showing a timing chart at the time of operation of the memory cell according to the second modification of the fifth embodiment of the present invention shown in FIG. 17B.

20A and 20B are circuit diagrams showing a memory cell according to a fourth modification of the fifth embodiment of the present invention.

FIG. 21A is a circuit diagram showing a bit line control circuit according to a sixth embodiment of the present invention. FIG. 16B is a circuit diagram showing a bit line control circuit according to a first modification of the sixth embodiment of the present invention.

FIG. 22A is a circuit diagram showing a sense amplifier according to a seventh embodiment of the present invention. FIG. 16B is a circuit diagram showing an equivalent circuit of the sense amplifier in the first half of the read period according to the seventh embodiment of the present invention. FIG. 13C is a circuit diagram showing an equivalent circuit of the sense amplifier in the latter half of the read period according to the seventh embodiment of the present invention.

FIG. 23 is a schematic diagram of a current flow at the time of reading in the SRAM semiconductor integrated circuit device according to the present invention,
(A) is a SRAM device, (b) is a timing chart.

FIG. 24 is a schematic diagram of the potential of the source line of the cross-coupled transistor at the time of writing in the SRAM semiconductor integrated circuit device according to the present invention, (a) is a schematic diagram of a memory cell having a common type source line, (B) is a schematic diagram of a memory cell having a separate source line.

FIG. 25 is an overall configuration diagram of a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 26 is a block diagram showing a column circuit according to the embodiment of the present invention.

FIG. 27A is a circuit diagram showing a bit line selection circuit according to an embodiment of the present invention. (B) is a circuit diagram showing a ground line selection circuit according to an embodiment of the present invention.

28 (a) and 28 (b) are circuit diagrams showing a selection circuit in the preceding stage of the sense amplifier according to the embodiment of the present invention.

FIG. 29 is a diagram showing a timing chart during operation of the memory cell according to the first and second embodiments of the present invention.

FIG. 30 is a diagram showing a timing chart at the time of operation of the memory cell according to the third and fourth embodiments of the present invention.

FIG. 31 is a circuit diagram showing a conventional memory cell.

FIG. 32 is a schematic diagram showing a current flow at the time of reading in a conventional SRAM device, FIG. 32 (a) is a first conventional SRA.
It is a schematic diagram of M apparatus, (b) is a first conventional SRAM
3 is a timing chart of the device, (c) is a schematic view of a second conventional SRAM device, and (d) is a timing chart of the second conventional SRAM device.

FIG. 33 is a schematic diagram of a write operation in a conventional SRAM device.

[Explanation of symbols]

P1 first load transistor N1 first inverting load transistor P2 second load transistor N2 second inverting load transistor N1 first drive transistor P1 first inverting drive transistor N2 second drive transistor P2 Two inverting drive transistors N3 first switch P3 first
Inverting switch N14 second switch P14 second inverting switch N24 second switch P24 second inverting switch N54 second switch P54 second inverting switch N15 third switch N25 third switch P25 Third inverting switch N35 Third switch N55 Third switch P55 Third inverting switch N26 Fourth switch N46 Fourth switch N56 Fourth switch P56 Fourth inverting switch N81 Fifth switch Switch P81 Fifth inverting switch N82 Sixth switch P82 Sixth inverting switch V1 First storage node V2 Second storage node V3 First connection point V53 First connection point V4 Second connection point V54 Second connection point WL Word line WL (m) Word line WLn Word line WLp Word line WLr For reading Word line WLw Write word line WT Write control line WT (m) Write control line BL Bit line BL (n) Bit line BLn Bit line BLp Bit line BLr Read bit line BLw Write bit line / BL Bit complementary line / BL (N) Bit complementary line / BLn Bit complementary line / BLp Bit complementary line / BLr Read bit complementary line / BLw Write bit complementary line Vcc First power supply Vss Second power supply Vs1 Third power supply Vs1 (n) Third power supply Vs2 Fourth power supply Vs2 (n) Fourth power supply Vsm Fifth power supply Vm Sixth power supply Vx1 Ground potential Vu1 First high data potential Vu2 Second high data potential Vu3 Ground line control potential A1 bit Line control circuit A2 Bit line control circuit WE Write request RE Read request Din Write data pBL (k) Previous bit line / pBL (k ) Previous bit complementary line P61 First P-type switch P62 Second P-type switch P63 Third P-type switch P64 Fourth P-type switch N61 First N-type switch N62 Second N-type switch N63 Third N-type switch N64 Fourth N-type switch N65 Fifth N-type switch N66 Sixth N-type switch Dout Read data / Dout Read reference data pDout Sense amplifier output / pDout Sense amplifier reference output XSA Sense amplifier activity Signal EQ equalize signal RD (k) of sense amplifier common data line / RD (k) common data reference line P71 first load transistor P72 second load transistor N71 first drive transistor N72 second drive transistor N73 3rd transistor N74 4th transistor P75 5th transistor 76 First switch N77 Second switch N78 Sixth transistor N79 Seventh transistor B Ground line control circuit PB1 First P-type switch PB2 Second P-type switch PB3 Third P-type switch PB4 Fourth P-type switch NB1 First N-type switch NB2 Second N-type switch NB3 Third N-type switch NB4 Fourth N-type switch NB5 Fifth N-type switch NB6 Sixth N-type switch pVs1 (k) 1st ground line pVs2 (k) 2nd previous ground line DSW1 Bit line selection circuit DSW2 Ground line selection circuit DSW3 Sense amplifier previous stage selection circuit Add Column address dT1 Word line rise time difference dT2 Read data output time difference

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 27/11

Claims (29)

[Claims] 1. A semiconductor integrated circuit device comprising a memory cell array in which memory cells are arranged in rows and columns, wherein the memory cell has a first transistor in which a gate electrode and a drain electrode are cross-coupled. And a second transistor pair, the absolute value of the difference between the gate-source voltage of at least one of the transistor pairs in the ON state is small when data is written to the memory cell. Thus, the semiconductor integrated circuit device is provided with the source potential changing means for changing the potential of the source electrode of the transistor. 2. The semiconductor integrated circuit device according to claim 1, wherein the transistor pair shares a source electrode. 3. The semiconductor integrated circuit device according to claim 1, wherein a source electrode of the transistor pair is separated. 4. The source potential changing means changes the potential of the source electrode of the transistor so that the absolute value of the difference between the gate-source voltage of the transistor in the transistor pair is in a more off state. The semiconductor integrated circuit device according to claim 3, wherein. 5. In the memory cell, the first transistor is a first drive transistor having a drain electrode connected to a first storage node, and the second transistor has a drain electrode in the first storage node. A second driving transistor connected to a second storage node having a complementary relationship with the node, wherein the memory cell has a gate electrode and a source electrode cross-coupled to each other, and one source / drain electrode has a first First load transistor connected to the power supply of the other and the other source / drain electrode connected to the first storage node, and one source / drain electrode connected to the first power supply of the other source / drain electrode.
A second drain electrode connected to the second storage node;
And the source potential changing means writes a signal potential opposite to the source / drain electrode of the first drive transistor to the first storage node,
A ground line control potential is applied to the third power source, a potential of the second power source is applied to the fourth power source, and a source / drain electrode of a first drive transistor is connected to the first storage node. When writing the same signal potential, the ground line control circuit applies the potential of the second power source to the third power source and applies the ground line control potential to the fourth power source. The semiconductor integrated circuit device according to claim 4. 6. The memory cell array has a first control line and a second control line for controlling the memory cells arranged in a column direction, and when reading data from the memory cell, the first control line is provided. A first potential is applied to the control line and the second control line, and when writing data in the memory cell, the first potential or the second potential is applied to the first control line, and
The semiconductor integrated circuit device according to claim 1, further comprising a bit line control circuit that applies a third potential to the second control line. 7. The memory cell is connected in series between the first storage node and the first control line, is controlled by a third control line, and has one source / drain electrode. A first switch transistor connected to the first control line, and one source / drain electrode connected to the first storage node and controlled by the second control line, the other source / drain electrode And a second switch transistor connected to the other source / drain electrode of the first switch transistor, the second switch transistor including the first storage node and the first drive transistor. 7. The semiconductor integrated circuit device according to claim 6, wherein the semiconductor integrated circuit device is connected in series between the two. 8. The semiconductor integrated circuit device according to claim 7, wherein the memory cells adjacent to each other are commonly connected to the third power supply and the fourth power supply. 9. The threshold voltage of the second switch transistor is set to be lower than the threshold voltage of any of the first drive transistor, the second drive transistor and the first switch transistor. 9. The semiconductor integrated circuit device according to claim 7, which is provided. 10. The size of the second load transistor is set to be smaller than the size of either of the first load transistor or the second drive transistor. The semiconductor integrated circuit device according to any one of 1. 11. The second control line is arranged in parallel with the third control line, and a power source line connected to the fourth power source and the first control line have a column address. 8. A bit line pair of the memory cell for decoding is formed.
11. The semiconductor integrated circuit device according to any one of 10. 12. The semiconductor integrated circuit device according to claim 11, wherein the second control line is shared by a plurality of memory cells in the same column. 13. The memory cell is connected between the second storage node and the fourth power supply in parallel with the second drive transistor, and the first switch transistor and the second switch transistor are connected in parallel. 13. The semiconductor integrated circuit device according to claim 7, further comprising a third switch transistor controlled by a potential at a connection point with the switch transistor. 14. The semiconductor integrated circuit device according to claim 7, wherein the first power supply is stepped down by a step-down circuit. 15. The semiconductor integrated circuit device according to claim 14, wherein the step-down circuit is a memory cell in which conductivity types of all transistors forming the memory cell are inverted. 16. The number of memory cells connected to the third control line is larger than the number of memory cells connected to the first control line and the second control line. The semiconductor integrated circuit device according to claim 7. 17. The memory cell is connected in series between the second storage node and the first control line, and is controlled by the third control line,
A first switch transistor having one source / drain electrode connected to the first control line, and one source / drain electrode controlled by the second control line, and one source / drain electrode connected to the second storage node A second switch transistor whose other source / drain electrode is connected to the other source / drain electrode of the first switch transistor; and a second switch transistor connected in series between the first switch transistor and the third power source. 7. The semiconductor integrated circuit device according to claim 6, further comprising a third switch transistor that is connected to the first storage node and is controlled by the first storage node. 18. The semiconductor integrated circuit device according to claim 17, wherein the memory cells adjacent to each other are commonly connected to the third power supply and the fourth power supply. 19. The semiconductor integrated circuit device according to claim 17, wherein the size of the first load transistor is set to be smaller than the size of the second load transistor. 20. The second control line is arranged in parallel with the third control line, and a power source line connected to the fourth power source and the first control line have a column address. The bit line pair of the memory cell for decoding is formed.
20. The semiconductor integrated circuit device according to claim 19. 21. The semiconductor integrated circuit device according to claim 20, wherein the second control line is shared by a plurality of the memory cells in the same column. 22. The memory cell is connected in parallel with the first drive transistor between the first storage node and the third power supply, and the first switch transistor and the second switch transistor are connected in parallel. 22. The semiconductor integrated circuit device according to claim 17, further comprising a fourth switch transistor controlled by a potential of a connection point with the switch transistor. 23. The semiconductor integrated circuit device according to claim 17, wherein the first power supply is stepped down by a step-down circuit. 24. The semiconductor integrated circuit device according to claim 23, wherein the step-down circuit is a memory cell in which conductivity types of all transistors forming the memory cell are inverted. 25. The number of memory cells connected to the third control line is larger than the number of memory cells connected to the first control line and the second control line. The semiconductor integrated circuit device according to any one of claims 17 to 24. 26. The memory cell array includes a first control line and a second control line for controlling the memory cells arranged in a column direction, and a third control line for controlling the memory cells arranged in a row direction. In the memory cell, the first transistor is a first drive transistor having a drain electrode connected to a first storage node, and the second transistor has a drain electrode in the first storage node. A second driving transistor connected to a second storage node having a complementary relationship with the node, wherein the memory cell has a gate electrode and a source electrode cross-coupled to each other, and one source / drain electrode has a first A first load transistor connected to the power supply of the other and the other source / drain electrode connected to the first storage node, and one source / drain electrode of the first power supply Connected to the other source /
A second drain electrode connected to the second storage node;
A load transistor of, and is connected in series between the first storage node and the first control line, controlled by the third control line,
One source / drain electrode is controlled by a first switch transistor having one source / drain electrode connected to the first control line, and one source / drain electrode controlled by the second storage node.
A second switch transistor whose drain electrode is connected to the other source / drain electrode of the first switch transistor; and a second switch transistor connected in series between the second storage node and the second control line. A third switch transistor controlled by the first storage node, and one source / drain electrode controlled by the first control line, one source / drain electrode of the third switch transistor being And a fourth switch transistor having the other source / drain electrode connected to the second control line, wherein the second switch transistor is connected to the first storage node and the first drive transistor. And a third switch transistor connected in series between the second storage node and the second drive transistor. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is connected in series. 27. The memory cell array has a first memory cell connected in series with each other, and a second memory cell in which a conductivity type of each corresponding transistor in the first memory cell is inverted. And the first memory cell and the second memory cell are the first memory cell
27. The semiconductor integrated circuit device according to claim 26, wherein the semiconductor integrated circuit device is applied to a potential which is substantially half of the potential of the power source of. 28. The absolute value of the threshold voltage of any of the first and fourth switch transistors and the first and second drive transistors is the same as that of the first and second switch transistors.
28. The semiconductor integrated circuit device according to claim 26, wherein the load transistor and the threshold voltages of the second and third switch transistors are set to be smaller than absolute values. 29. The first, second, and third control lines in the memory cell are read-only control lines, and the memory cell array is a write-only fourth control line in the memory cell in the column direction. And a fifth control line, a sixth control line dedicated to writing in the memory cell in the row direction, and a sixth control line, and one source / drain electrode is connected to the first storage node. The other source /
A fifth drain electrode is connected to the fourth control line.
Controlled by the sixth control line, one source / drain electrode is connected to the second storage node, and the other source / drain electrode is connected to the second storage node.
A sixth drain electrode connected to the fifth control line
An absolute threshold voltage of any one of the first and fourth switch transistors, the first and second drive transistors, and the fifth and sixth switch transistors. 27. The value is also set to be smaller than the absolute value of each threshold voltage of the first and second load transistors and the second and third switch transistors. 27. The semiconductor integrated circuit device according to item 27.