JP2003006265A - Behavioral model generation method and behavioral model generation device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve a difficulty in selecting architecture appropriately if system architecture is comparatively evaluated and selected with top-down approach from specification description or functional behavioral description because of no methods available to appropriately estimate performance of a block to be newly implemented on hardware or to perform a high-speed simulation modeling. SOLUTION: A transition state is assigned to the functional behavioral description using a high-level synthesis means, a cycle delay is counted at a state transition point and a model to add the delay is generated in outputting an outcome of processing. This enables to generate a behavioral model which has a processing delay based on a feasible hardware and can perform the high- speed simulation. This result makes it possible to evaluate the architecture with shorter turnaround time and higher accuracy.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a behavior model generation method and a behavior model generation device. More specifically, a method and apparatus for generating a behavior model for performing a cycle-based behavior simulation used when performing top-down design by trial evaluating the LSI circuit architecture to be realized from a functional behavior description and performing trial and error. Regarding

[0002]

2. Description of the Related Art With the progress of miniaturization and integration technology of LSI, it has become possible to integrate a system-level large-scale circuit into a one-chip LSI. Such a system LS
In the development of I, it is necessary to achieve top-down design and early commercialization while performing stepwise verification in a short period of time from designing the processing method to function / logic / layout design. Especially in the basic design of system-level processing method / implementation architecture, which is premised on LSI implementation, the system LSI processing performance and bottle It is required to analyze the neck part. For this, a functional behavioral description of the system is made using a C program or the like, and the behavior is estimated and the performance is estimated by a simulation that executes this program. In order to improve the accuracy of this simulation and make more appropriate design selection, an operation model that can be simulated with clock cycle accuracy is created and used based on the detailed design results for circuit blocks that have been designed in detail and are reused. For example, for a CPU, a pipeline simulator is created and used as an operation model for executing an instruction execution pipeline with clock cycle accuracy. For hardware engines or coprocessors that execute specific processing, analyze the delay from the detailed design result until the processing result is output after the input signal or trigger signal is received and the required number of cycles is analyzed. An operation model that outputs the simulation result after delaying by only is used. On the other hand, for a completely new hardware block, detailed design of the RTL (register transfer level) and HDL description are performed in advance and this is used, or the predicted value of the number of cycles required for processing is empirically determined. , Embedded in the C program as a delay process when outputting the simulation result and used as a behavior model.

[0003]

However, in the simulation for examining the architecture at the system level, it takes several weeks to several months to use the RTL model for some new blocks. In addition, since the simulation performance including the RTL model is 1/10 or less, it is difficult to evaluate it in accordance with an actual operation scenario. Therefore, there arises a problem that the comparison evaluation / judgment of the method of realizing the system LSI is delayed, or only limited options can be selected. Further, when empirically predicting the processing amount of a new hardware block, a difference from the actual RTL design result naturally occurs, and in some cases, a redundant design with a very large margin for new hardware block processing. In the worst case, the RTL design cannot be performed with the predicted processing performance, and the entire system design may fail.

In addition, when an operation model of a new hardware block is created based on the predicted value of the processing delay, it is not possible to observe the internal operation in synchronization with the clock cycle, or it is possible to compare it with other blocks in the system due to an interrupt or the like. There was also the problem that irregular synchronization could not be achieved.

The present invention has been made to solve the above problems, and an object thereof is to provide a method of generating a behavior model having a simulation performance almost equal to that of the original behavior model. .

[0006]

A behavioral model generation method according to the present invention is a method for generating a behavioral model for simulating a behavior for each synchronization cycle from a functional behavioral description of a digital circuit, which is a high-level synthesis step. And a delay adding step. In the high-level synthesis step, delay information in units of synchronization cycles such as clock signals is generated by high-level synthesis from a functional behavioral description such as a C program. In the delay adding step, the synchronous cycle delay behavior description is added to the functional behavior description based on the delay information.

[0007] Preferably, in the high-level synthesis step, a control / data flow graph is generated from the functional behavioral description, and the control / data flow graph is high-level synthesized to synchronize with a synchronization signal and make a state transition every cycle. The allocation information of the operation transition state and the hardware resource allocation information in the finite state transition model are generated.

Preferably, in the delay adding step, the cycle delay is counted for each operation description step of the state transition points assigned by the high-level synthesis step, and in the step of outputting the processing result, the cycle delay is counted according to the counted cycle delay number. Add a description to delay the output. That is, the state assigned by high-level synthesis is associated with the behavioral description that is the input, the cycle is counted at each step of the input behavioral description corresponding to the state transition point, and the counted number of cycles at the step of outputting the processing result. Add a description to delay the output according to.

In the above-mentioned behavior model generation method, high-level synthesis for generating a control / data flow graph or the like is performed to count the number of cycles required until the processing is completed based on one feasible RTL design, and can be realized. A behavior model that models various performances is generated.
On the other hand, the generated behavior model is basically a behavior description equivalent to that of a C program, and only a step of counting the number of cycles when the step is executed is added to a specific step. Therefore, high-speed simulation performance that is almost the same as the original behavior model can be expected.

Preferably, in the delay adding step, the synchronization signal is waited for each operation description step of the state transition point assigned by the high-level synthesis means, and a description for delaying one cycle operation is added.

In the above behavior model generation method, the behavior model of the generated specific hardware block is simulated in synchronization with a synchronization signal input from the outside.
That is, the input signal can be taken in every synchronous clock cycle. This makes it possible to correctly simulate an operation when an interrupt signal, a pause signal, or the like is input to the corresponding hardware block in synchronization with the surroundings.

[0012] Preferably, the behavior model generation method further includes an observation adding step. In the observation adding step, the description for observing the operation and the state change synchronized with the synchronization cycle is added to the functional operation description.

Preferably, in the observation adding step, a description for recording state transition and simulation time information at the time of transition is added for each behavior description step of the state transition point assigned by the high-level synthesis step.

In the above-mentioned behavior model generation method, it is possible to confirm the simulation status by the behavior model in units of synchronous clocks.

Preferably, in the observation adding step, a description for recording the variable value according to the resource type assigned by the high-level synthesis step is added.

In the above behavior model generation method, it is possible to trace the processing from the activation of the hardware block to the output of the result for each synchronous clock. As a result, not only a highly accurate motion model can be obtained, but also motion analysis inside the block can be performed while maintaining a high simulation speed.

Preferably, in the observation adding step, a description for recording the information on the toggle number of the variable assigned to the register for each cycle by the high level synthesis step is added.

In the above-mentioned behavior model generation method, the activity transition of the register can be analyzed, and static power consumption and peak power consumption can be realized.

A behavioral model generation device according to the present invention is a device for generating a behavioral model for simulating a behavior for each synchronization cycle from a functional behavioral description of a digital circuit, and includes a high-level synthesis means and a delay addition means. . The high-level synthesis means generates delay information in synchronization cycle units by high-level synthesis from the functional behavioral description. The delay adding means is
A synchronous cycle delay behavior description is added to the functional behavior description based on the delay information.

Preferably, the high-level synthesis means generates a control / data flow graph from the functional behavioral description, and performs high-level synthesis of the control / data flow graph to assign the operation transition state allocation information and the hardware resource allocation information. Produces and.

Preferably, the delay adding means counts the cycle delay for each operation description step of the state transition point allocated by the high-level synthesis means, and outputs the processing result in accordance with the counted cycle delay number. Add a description to delay the output.

Preferably, the delay adding means adds a description for delaying one cycle operation for each operation description step of the state transition point assigned by the high-level synthesis means.

Preferably, the behavior model generation device further comprises an observation addition means. The observation adding means adds a description for observing an operation and a state change synchronized with the synchronization cycle to the functional operation description.

Preferably, the observation adding means adds a description for recording the state transition and the information of the simulation time at the transition for each behavior description step of the state transition point assigned by the high-level synthesis means.

Preferably, the observation adding means adds a description for recording the variable value according to the resource type assigned by the high-level synthesis means.

Preferably, the observation adding means adds a description for recording the information on the toggle number of the variable assigned to the register by the high-level synthesis means.

[0027]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will now be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are designated by the same reference numerals, and the description thereof will not be repeated.

(First Embodiment) FIG. 1 is a flow chart showing the flow of processing in a behavior model generation method according to a first embodiment of the present invention. The behavior model generation method shown in FIG. 1 includes a high-level synthesis step ST1 and a behavior model synthesis step ST2. High-level synthesis step ST
In 1, the register transfer level circuit is generated using the input program file and the design constraint file. In the motion model generation step ST2, the high-level synthesis step ST1
The behavior model is synthesized from the control / data flow graph generated in. Behavior model generation step ST2
Is an extraction step ST21 and an insertion & generation step ST
22 and 22. In the extraction step ST21, the control / data flow graph is analyzed and the point where the state transition of the circuit occurs (that is, the point where the cycle delay occurs) and its generation condition are extracted. In the inserting & generating step ST22, a program for counting the cycle delay of the circuit is inserted to generate an operation model.

Next, an example of the generation process of the behavior model by the method shown in FIG. 1 will be described.

2 to 4 are flow charts showing in detail the flow of processing in the high-level synthesis step ST1, the extraction step ST21 and the insertion & generation step ST22 shown in FIG. 1, respectively. Hereinafter, description will be given with reference to FIGS. 2 to 4.

First, the input program file and the design constraint file described at the operation level are input. Figure 5
It is an example of an input program file described in C. The program of FIG. 5 is an operation description for performing the accumulation of the number of times designated by the input and the accumulation of the number of times designated by the input, and outputting the sum thereof.

Referring to FIG. 2, high-level synthesis step ST1
Then, first, a design constraint file describing constraints on the area, operating speed, power consumption, etc. of the circuit is given. Then, in step ST101, lexical analysis and syntax analysis of the input program are performed, and a symbol table is created and a basic block that is a basic unit of the program is extracted. A symbol table as shown in FIG. 6 is generated for the input program shown in FIG.

Next, in step ST102, the semantic relationship of the program is analyzed by extracting the dependency relationships between the basic blocks to generate a control / data flow graph. For the input program shown in FIG.
A control / data flow graph as shown in Figure 3 is generated. Each node shown in FIG. 7 becomes a basic block.

Next, in step ST103, the control / data flow graph is analyzed, and according to the design constraint specified in the design constraint file, the state of the FSM and the arithmetic unit resource are assigned to each process of the input program. , Allocate storage resources to each variable. Then, in step ST104, the state allocation information, the arithmetic unit resource allocation information, and the storage resource allocation information are added to the control / data flow graph, and the storage resource allocation information is added to the symbol table. For the description example shown in FIG. 5, the FSM state is assigned as shown in FIG. 8, and the resource: register is assigned to each symbol as shown in FIG. In FIG. 8, the state is assigned to four states 1-4 indicated by broken lines. Also, the basic block that initializes (sets to 0) the variable j is merged with the first basic block.

With the above, the processing in the high-level synthesis step is completed, and then the process proceeds to the extraction step ST21.

Referring to FIG. 3, in extraction step ST21, first in step ST211, control / control is performed.
From the origin of the dataflow graph, select the first basic block to analyze.

Next, in step ST212, the number of state transitions occurring in the basic block is extracted from the state allocation information, and the state transition number information is added to the control / data flow graph.

Next, in step ST213, regarding the movement from another basic block to the basic block currently being analyzed, it is searched from the state assignment information whether or not there is a movement accompanied by the occurrence of a state transition. If there is a movement accompanied by a state transition, the process proceeds to step ST214, and the point at which the state transition occurs and the generation condition are added to the basic block as information. If there is no movement accompanied by state transition, the process proceeds to step ST215. Then, in step ST215, it is determined whether the analysis of all the basic blocks is completed. When the analysis of all the basic blocks is completed, the processing in the extraction step ST21 is completed, and when not completed, the step ST211 is completed.
Return to. In the control / data flow graph shown in FIG. 8, there is no state transition within the basic block, and the movement points between the basic blocks that move between the states indicated by the broken lines are listed as state transition occurrence points.

With the above, the processing in the extraction step ST21 is completed, and then the process proceeds to the insertion & generation step ST22,
Generates a behavior model program. In the insertion & generation step ST22, a behavior model program having a program structure as shown in FIG. 10 is generated. Figure 10
The behavior model shown in is assumed to be incorporated and executed in a simulation program having a control structure as shown in FIG. In the simulation program 7 shown in FIG. 11, the simulation control unit 8 manages the time progress of the entire simulation, and also has a data table 9 of the input / output signals (variables) of the incorporated operation models 11 and 12 and manages the data. . Further, the update data buffer 10 controls the update of data that occurs with a delay with respect to the simulation time.

The above structure is the same as the structure of the event, time hole, signal value table, etc. in the event driven system processing executed by the logic simulator of the electronic circuit. Further, 81 and 82 in FIG. 11 indicate a control flow, 83-86 indicate a data flow, and 87 and 88 indicate pointer information flows.

FIG. 12 is a diagram showing a control flow of the simulation controller 8 in the simulation program 7 shown in FIG. This will be described below with reference to FIGS. 12 and 11. The behavior model 11 is activated by the simulation controller 8 at time T by polling control or event driven (81). At this time, as an input, the data value 83 on the data table, the pointer 87 of the update data buffer for returning the output result,
A pointer 88 for returning delay information (the number of delayed cycles) until the output result is written in the data table 9 is used as an argument. The behavior model program is executed in Δ time on the simulation, and the output result 84 and the delay information 85 (assuming N cycles) are returned to the simulation controller 9 within the processing at time T and stored in the update data buffer 10. When the simulation control unit 8 advances the processing and the delay cycle N of the delay information 85 elapses, the output result 86 of the behavior model 11 at time (T + N) is written in the data table 9 and the data table 9 is updated.

The behavior model program incorporated in such a simulation has a structure as shown by reference numeral 3 in FIG. 10, and is analyzed and extracted in the variable and cycle counter initialization unit 4 and in the high-level synthesis step ST1. , Corresponding to basic blocks, and a return step 6 for returning output data and a cycle counter. Here, the cycle counter is a variable for pairing with the output data and for calculating the delay information indicated by 84 in FIG. In the basic block processes 51 and 52 in FIG. 10, the step of counting up the cycle counter in response to the conditional state transition and the step of counting up the cycle counter in accordance with the number of state transitions occurring in the basic block without condition are counted up. Steps and are included. With such a program, the operation is simulated and the cycle delay is calculated.

Referring to FIG. 4, insertion & generation step ST
In 22, first, in step ST221, a variable used for a behavioral description and a program for initializing a cycle counter for counting a cycle delay are generated.

Next, in step ST222, the basic block to be converted into the behavioral description is selected from the starting point of the control / data flow graph. And step ST22
In 3, the program description for executing the processing in the basic block is sequentially generated.

Next, in step ST224, it is checked whether or not the basic block conditionally contains information regarding the state transition. If the conditional state transition information is included, the process proceeds to step ST225, and a step of counting the cycle delay at the point where the condition is satisfied and the program is executed, that is, a step of counting up the cycle counter is generated. If the conditional state transition information is not included, the process proceeds to step ST226.

Then, in step ST226, it is checked whether or not the state transition occurs once or more in the basic block. When the number of state transitions occurring in the basic block is 1 or more, the process proceeds to step ST227, and a step of counting up the cycle counter according to the number of state transitions is generated. If the number of state transitions that occur in the basic block is less than 1, that is, if they do not occur, step ST2
Proceed to 28.

Then, in step ST228, it is determined whether or not the analysis of all the basic blocks is completed. When it is determined that the analysis of all the basic blocks is completed, the process proceeds to step ST229, and after the program description for all the basic blocks is generated, a return step that returns the cycle counter together with the processing result is generated. If there is a basic block that has not been analyzed yet, the process returns to step ST222.

FIG. 13 is a diagram showing an operation model generated from the control / data flow graph shown in FIG. In this example, a step of counting cycles using a cycle counter cycle is inserted when moving between basic blocks that are state transition points. For example, for this behavior model, (input
1 = 3, input2 = 4, indata1 = 1
2, indata = 20) is given, after initialization is performed, the process corresponding to the state 2 shown in FIG. 8 is repeated three times until the condition i <input1 is satisfied.
Let e be 3. Next, the process corresponding to the state 3 shown in FIG. 8 is repeated four times until the condition j <input2 is satisfied, and the cycle is set to 7. Finally, in the output calculation corresponding to the state 4 shown in FIG. 8, the cycle is set to 8 and output = 36 + 160000 = 160036.
And cycle = 8 are returned.

As described above, according to the first embodiment, it is possible to extract the control / data flow graph and the state allocation information from the high-level synthesis system and generate the behavior model in which the cycle delay count is inserted.

(Second Embodiment) A behavior model generation method according to a second embodiment of the present invention is based on the insertion & insertion process shown in FIG.
The generation step ST22 is performed according to the flowchart shown in FIG. 14, and the behavior model as shown in FIG. 15 is generated. The flow of other processes is the same as the flow shown in FIG.

The operation model shown in FIG. 15 is assumed to be incorporated and executed in a simulation program having a control structure as shown in FIG. Figure 1
In the simulation program 17 shown in FIG. 6, the simulation control unit 18 manages the time progress of the entire simulation, and also incorporates the operation model 21.
And input / output signal (variable) data table 19 of 22
And manages the data by securing it as a shared memory between processes. A variable 20 having simulation time information is also stored in this shared memory.

In the simulation program 17 shown in FIG. 16, the behavior models 21 and 22 are activated as separate processes, and the simulation controller 18 and the process executing each behavior model proceed with the simulation while synchronizing the simulation times. Reference numerals 201, 191, and 192 in FIG. 16 indicate correspondence between data reference and writing.

FIG. 17 shows the simulation program 1
7 is a diagram showing a flow of execution of processes of 7 and the behavior model 21. FIG. The process of the behavior model 21 is activated by the simulation controller 18 at time T by polling control or event driven. At this time, the pointer of the time variable and the pointer of the input / output data on the data table are used as arguments as inputs. When the process of the behavior model 21 is started by the process at time T, it executes the process up to the next state transition point, and enters the wait until the time is updated. When the simulation control unit 18 advances the time to (T + 1), the execution is started again, the process is advanced to the next state transition point, and the wait state is entered again. The process is repeated in the same manner, and the final exit is performed to end the process.

The program of the behavior model incorporated in such a simulation has a structure as shown by reference numeral 13 in FIG. 15, and has a variable and time counter (weight counter) initialization unit 14 and a high-level synthesis step ST.
The processing unit 15 corresponding to the basic block analyzed and extracted in 1.
, And an exit step 16 for terminating the process. Here, the time counter is a counter for the behavior model to synchronize with the simulation control unit 18, and is set to the value of the time variable pointer of the argument at initialization. The processing 151 and 152 of each basic block shown in FIG. 15 waits for the time variable on the shared memory to be updated by one unit time in response to the conditional state transition, and the processing occurs in the basic block without a condition. Processing for weighting the time according to the number of state transitions to be performed.

Referring to FIG. 14, in the insertion & generation step in the second embodiment, first, step ST2210.
At, a program for initializing a variable used for behavioral description and a time counter for counting wait time is generated.

Next, in step ST2220, the basic block to be converted into the behavioral description is selected from the starting point of the control / data flow graph. And step ST2
At 230, a program description for executing the processing in the basic block is sequentially generated.

Next, in step ST2240, it is checked whether or not the basic block conditionally contains information regarding the state transition. When the conditional state transition information is included, the process proceeds to step ST2250, and the step of counting and waiting the time counter at the point where the condition is satisfied and the program is executed, that is, the time counter is advanced by one time and the corresponding time is reached. A program for waiting is inserted until the time variable on the shared memory is updated by the simulation controller 18. If the conditional state transition information is not included, the process proceeds to step ST2260.

Then, in step ST2260, it is determined whether or not one or more state transitions occur in the basic block. If the number of state transitions occurring in the basic block is 1 or more, the process proceeds to step ST2270, the time counter is counted up according to the number of state transitions, and the time variable on the shared memory is kept until the corresponding time. Insert a program that waits until it is updated by. If the number of state transitions that occur in the basic block is less than 1, that is, if they do not occur, the process proceeds to step ST2280.

Then, in step ST2280, it is determined whether or not the analysis of all the basic blocks is completed. When it is determined that the analysis of all the basic blocks is completed, the process proceeds to step ST2290, and after generating program descriptions for all the basic blocks, an exit step for ending the process is generated. If there is a basic block that has not been analyzed yet, step S
Return to T2220. The output data is directly written in the data table through the pointer of the argument to generate a program for updating.

When the above embodiment is applied, the behavior model generated from the behavior description of FIG. 5 can obtain the description as shown in FIG. In FIG. 18, a for statement that waits for one cycle time defined at the state transition point is generated.

As described above, according to the second embodiment, it is possible to generate a behavior model in which a synchronization signal is waited for each behavior description step at a state transition point and a description for delaying one cycle operation is added. As a result, the operation model of the specific hardware block generated by the present invention can be simulated in synchronization with the synchronization signal input from the outside, that is, the input signal can be taken in every synchronization clock cycle. As a result, it becomes possible to correctly simulate the operation when an interrupt signal, a pause signal, or the like is input to the corresponding hardware block in synchronization with the surroundings.

It should be noted that the wait process in this embodiment may not be inserted into every state transition unit, but may be inserted into a designated specific state transition.

In addition, a sub-group in which the basic blocks of the operation model of the first embodiment are put together is created, divided into a plurality of programs corresponding thereto, and the processing and state transition of the basic blocks in each sub-group are executed. Therefore, it is possible to incorporate a mechanism to wait until the entire simulation time has elapsed.

(Third Embodiment) A behavior model generating method according to a third embodiment of the present invention is based on the insertion & insertion process shown in FIG.
The generation step ST22 is performed according to the flowchart shown in FIG. 19 to generate a behavior model having a program configuration as shown in FIG. The flow of other processes is the same as the flow shown in FIG.

In the program shown in FIG. 20, for each designated observation resource, a pointer indicating an area for storing the observation result, that is, an observation resource state pointer is passed as an argument. Each pointer is a resource identifier, value,
It points to the beginning of the array area of the data structure including the cycle number and toggle counter. The structure of this sequence region is shown in FIG.
As shown in FIG. 20, basic block processes 251, 252
When the cycle counter is counted up in response to the conditional state transition, the observed value of the specified resource, the number of cycles, and the presence or absence of the toggle are recorded in the array position corresponding to the cycle counter value in the observed resource state pointer. The same applies when the cycle counter is incremented according to the number of state transitions that occur in the basic block, and also in the case of initialization 24. When the program ends, the observation resource status pointer is returned to the simulation control unit, formatted and displayed in chronological order. When observing the registers tmp1 and tmp2 in the operation model shown in FIG. 13, the observation resource state pointer shown in FIG. 22 is passed. Further, as an input (input1 = 3, inp
ut2 = 4, indata1 = 12, indata
= 20), 8 cycles are returned as a cycle delay, and the observation resource state at this time has the content as shown in FIG.

Referring to FIG. 19, in the insertion & generation step in the third embodiment, first, step ST2211.
First, a program that initializes variables used for behavior description and a cycle counter that counts cycle delays, and sets a resource name, cycle counter value, lease value, and number of toggles in the first data structure of the observation resource state pointer To generate.

Next, in step ST2221, the basic block to be converted into the behavioral description is selected from the starting point of the control / data flow graph. And step ST2
At 231, a program description for executing the processing in the basic block is sequentially generated.

Next, in Step ST2241, it is checked whether or not the basic block conditionally contains information regarding the state transition. If the conditional state transition information is included, the process proceeds to step ST2251, and the step of counting the cycle delay at the point where the condition is satisfied and the program is executed, that is, the step of counting up the cycle counter, is followed by , Storing the number of cycles, the value of the observation resource, and the number of toggles from the observation resource state pointer to the data at the position corresponding to the cycle counter value. If the conditional state transition information is not included, the process proceeds to step ST2261.

Then, in step ST2261, it is determined whether or not a state transition occurs once or more in the basic block. If the number of state transitions occurring in the basic block is 1 or more, the process proceeds to step ST2261, and the step of counting up the cycle counter in accordance with the number of state transitions, and subsequently, the cycle counter value from the observation resource state pointer And a step of storing the number of cycles, the value of the observation resource, and the number of toggles in the data at the position corresponding to. If the number of state transitions that occur in the basic block is less than 1, that is, if they do not occur, the process proceeds to step ST2281.

Then, in step ST2281, it is judged whether or not the analysis of all the basic blocks is completed. When it is determined that the analysis of all the basic blocks is completed, the process proceeds to step ST2291, and after generating program descriptions for all the basic blocks, generates a return step that returns a cycle counter and an observation resource state pointer together with the processing result. To do. If there is a basic block that has not been analyzed yet, the process returns to step ST2221.

[0071]

According to the behavioral model generation method of the present invention, the states assigned by high-level synthesis are associated with the behavioral description to be an input, the cycle is counted at each step of the behavioral description corresponding to the state transition point, and the processing is performed. By adding the description that delays the output according to the counted number of cycles in the step of outputting the result, the number of cycles required to complete the process is counted based on one feasible RTL design, which can be realized. Generates a behavior model that models the performance of various circuits. On the other hand, the generated behavior model is basically a behavior description equivalent to that of a C program, and only a step of counting the number of cycles when the step is executed is added to a specific step. Therefore, high-speed simulation performance that is almost the same as the original behavior model can be expected.

Further, in the delay adding step, since the synchronization signal is waited for each operation description step at the state transition point and the description for delaying one cycle operation is added, the operation model of the generated specific hardware block is externally It is possible to perform the simulation in synchronization with the synchronization signal input from the input terminal, that is, the input signal can be taken in every synchronization clock cycle. This makes it possible to correctly simulate an operation when an interrupt signal, a pause signal, or the like is input to the corresponding hardware block in synchronization with the surroundings. In addition to this, it becomes possible to obtain a behavior model that can more faithfully simulate the behavior of the actual circuit.

Further, since the observation adding step is provided, the simulation status by the operation model can be confirmed in units of synchronous clocks.

Further, in the observation adding step, since the description for recording the value of the variable according to the resource type allocated by the high-level synthesis is added, the processing from the activation of the hardware block to the output of the result is performed by the synchronous clock. It becomes possible to trace every time. As a result, not only a highly accurate motion model can be obtained, but also motion analysis inside the block can be performed while maintaining a high simulation speed. Further, in the observation adding step, since the description for recording the toggle number of the variable assigned to the register for each cycle is added, the transition of the activity of the register can be analyzed, and static power consumption and peak power consumption can be performed.

[Brief description of drawings]

FIG. 1 is a flowchart showing a processing flow in a behavior model generation method according to a first embodiment of the present invention.

FIG. 2 is a flowchart showing in detail the flow of processing in the high-level synthesis step shown in FIG.

FIG. 3 is a flowchart showing in detail the flow of processing in the extraction step shown in FIG.

FIG. 4 is a flowchart showing in detail the flow of processing in the insertion & generation step shown in FIG.

FIG. 5 is a diagram showing an example of an input program file.

6 is a diagram showing a symbol table generated for the input program shown in FIG.

FIG. 7 is a diagram showing a control / data flow graph generated for the input program shown in FIG.

8 is a diagram showing a state of an FSM assigned to the control / data flow graph shown in FIG. 7. FIG.

9 is a diagram showing a result of allocating resources to the symbol table shown in FIG.

10 is a diagram showing a program structure of an operation model generated by the inserting & generating step shown in FIG.

FIG. 11 is a diagram showing a structure of a simulation program.

FIG. 12 is a diagram showing a control flow of the simulation controller shown in FIG. 11.

13 is a diagram showing an operation model generated from the control / data flow graph shown in FIG.

FIG. 14 is a flowchart showing in detail the flow of processing in the inserting & generating step according to the second embodiment of the present invention.

15 is a diagram showing a program structure of an operation model generated by the inserting & generating step shown in FIG.

FIG. 16 is a diagram showing a structure of a simulation program.

17 is a diagram showing a control flow of the simulation controller shown in FIG.

18 is a diagram showing an operation model generated from the operation description shown in FIG.

FIG. 19 is a flowchart showing in detail the flow of processing in the inserting & generating step according to the third embodiment of the present invention.

20 is a diagram showing a program structure of an operation model generated by the inserting & generating step shown in FIG.

FIG. 21 is a diagram showing a structure of observation resource state data.

FIG. 22 is a diagram showing an observation resource state pointer passed when observing a register.

FIG. 23 is a diagram showing an example of data in which observation results are stored.

[Explanation of symbols]

ST1 High-level synthesis step ST2 Behavior model synthesis step ST21 extraction step ST22 Insert & create step

Claims (16)

[Claims] 1. A method for generating an operation model for simulating an operation in each synchronization cycle from a functional operation description of a digital circuit, wherein delay information in a synchronization cycle unit is obtained from the functional operation description by high-level synthesis. A behavior model generation method comprising: a high-level synthesis step of generating; and a delay addition step of adding a synchronous cycle delay behavior description to the functional behavior description based on the delay information. 2. The behavior model generation method according to claim 1, wherein in the high-level synthesis step, a control / data flow graph is generated from the functional behavioral description, and the control / data flow graph is high-level synthesized. A behavior model generation method characterized by generating allocation information of a motion transition state and hardware resource allocation information. 3. The behavior model generation method according to claim 1, wherein in the delay addition step, a cycle delay is counted for each behavior description step of a state transition point assigned by the high level synthesis step, and a processing result is output. A behavior model generation method, wherein a description for delaying the output according to the counted cycle delay number is added in the step. 4. The behavior model generation method according to claim 1, wherein in the delay adding step, a description for delaying one cycle operation is added for each behavior description step of a state transition point assigned by the high-level synthesis means. A behavior model generation method characterized by the above. 5. The behavior model generation method according to claim 1, further comprising an observation adding step of adding a description for observing a behavior and a state change synchronized with a synchronization cycle to the functional behavior description. Behavior model generation method. 6. The behavior model generation method according to claim 5, wherein in the observation adding step, state transition and simulation time information at the time of transition for each behavior description step of the state transition point assigned by the high-level synthesis step. A behavior model generation method characterized by adding a description for recording. 7. The behavior model generating method according to claim 5, wherein the observation adding step adds a description for recording a variable value according to the resource type assigned by the high-level synthesis step. Behavior model generation method. 8. The behavior model generation method according to claim 5, wherein in the observation adding step, a description for recording the information on the toggle number of the variable assigned to the register in the high level synthesis step is added. Behavior model generation method. 9. An apparatus for generating an operation model for simulating an operation in each synchronization cycle from a functional operation description of a digital circuit, wherein delay information is generated in synchronization cycle units by high-level synthesis from the functional operation description. A behavior model generation device comprising: a high-level synthesis means; and a delay addition means for adding a synchronous cycle delay behavior description to the functional behavior description based on the delay information. 10. The behavior model generation device according to claim 9, wherein the high-level synthesis means generates a control / data flow graph from the functional behavioral description and high-level synthesizes the control / data flow graph. An operation model generation device, which generates allocation information of an operation transition state and hardware resource allocation information. 11. The behavior model generation device according to claim 9, wherein the delay adding unit counts a cycle delay for each behavior description step of a state transition point assigned by the high-level synthesis unit and outputs a processing result. In the step of, the behavior model generation device is characterized in that a description for delaying the output according to the counted cycle delay number is added. 12. The behavior model generation device according to claim 9, wherein the delay adding unit adds a description for delaying a one-cycle operation for each behavior description step of a state transition point assigned by the high-level synthesis unit. A behavior model generation device characterized by the above. 13. The behavior model generation device according to claim 9, further comprising observation adding means for adding a description for observing a behavior and a state change synchronized with a synchronization cycle to the functional behavior description. Behavior model generator. 14. The behavior model generation device according to claim 13, wherein the observation adding means includes state transition and simulation time information at the time of transition for each behavior description step of the state transition point assigned by the high-level synthesis means. A behavior model generation device characterized in that a description for recording is added. 15. The behavior model generation device according to claim 13, wherein the observation adding unit adds a description for recording a variable value according to the resource type assigned by the high-level synthesis unit. Behavior model generator. 16. The behavior model generation device according to claim 13, wherein the observation adding unit adds a description for recording information on a toggle number of a variable assigned to the register by the high-level synthesis unit. Behavior model generating device.