JP2003006053A - Data processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To give priority to suppression of lowering of reliability in information storage only in an area in which rewrite is frequently performed to one nonvolatile memory. SOLUTION: A part of an area in which the rewrite is frequently performed to one nonvolatile memory (2) is defined as a specific block (11), duplicate write to another address to one piece of data in rewrite to the specific block is performed, an error correction based on duplicated data read from other corresponding address is performed in reading and both processings are realized by a program of a CPU (3). Priority is given to the suppression of the lowering of reliability in the information storage to a part of a storage area of the nonvolatile memory. In an area where only the small number of rewrites is required, priority is given to maximization of use efficiency of a memory cell without defining the area as a processing object as the specific block.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device such as a single chip microcomputer having a built-in non-volatile memory such as a flash memory or an EEPROM (Electrical Erasable and Programmable Read Only Memory). For example, the present invention relates to a technique effective when applied to a single-chip microcomputer for device embedded control.

[0002]

2. Description of the Related Art An electrically rewritable nonvolatile memory such as a flash memory stores information by a threshold voltage according to the amount of electrons or holes injected into the floating gate of a memory cell. The threshold voltage characteristic of such a memory cell deteriorates with time as the number of rewrites increases. As the characteristics deteriorate, the probability that a write error will occur in the verify operation at the time of rewriting data increases. As described above, in the flash memory, as writing and erasing are repeated, the characteristic deteriorates, and "missing bit" occurs in which information cannot be normally retained. The number of times of rewriting guaranteed by the flash memory or its on-chip microcomputer is limited by the characteristic deterioration. The following techniques have been conventionally known as methods for improving the number of times of rewriting.

The first technique is a method realized as a circuit structure of a flash memory. For example, the same bit information is written to two (generally a plurality of) cells at the time of writing, the data is read from both memory cells at the time of reading, and a logical value corresponding to the high threshold state if at least one is in the high threshold state. It is configured to output the data of. Alternatively, the circuit of the flash memory is configured so that the same bit information is written to three or more memory cells at the time of writing, and the data is read from these cells at the time of reading and the majority logic is output. Japanese Patent Application Laid-Open No. 3-57048 is an example of a document describing a flash memory having such a configuration.

The second technique is to provide an error correction function block on a chip, and to generate a check bit at the time of writing, and to detect and correct an error from the original information and the check bit at the time of reading. Is. As an example of literature describing this technology, 2000 Sym
Posium on VLSI CircuitsDi
best of Technical Papers,
pp162-165.

As a third technique, Japanese Patent Laid-Open No. 7-21021
As described in Japanese Patent No. 5 publication, when the CPU writes to the EEPROM, the two areas in the EEPROM and the E
When writing data to three locations, a backup memory other than the EPROM, and the CPU reads data,
There is a method in which data is read from the above-mentioned three places, and when two data among them are matched, the data related to the match is judged to be correct.

[0006]

However, in the above-mentioned first technique, there are applications in which a large number of times of rewriting is required (for example, the cell usage efficiency is sacrificed by the configuration of 2 memory cells / bit), and the number of times of rewriting is small. However, it is not possible to apply the flash memory of the same configuration to the application that requires the maximum cell usage efficiency (that is, 1 memory cell / bit configuration), so prepare or mount multiple types of flash memory according to the application. There is a need to. As a result, the development efficiency of the flash memory deteriorates. In addition, the number of circuit modules also increases, which eventually becomes a factor of increasing the chip area.

The second technique has a problem that the chip area is increased and the cost is increased by providing hardware having an error correction function such as ECC. Even if the ECC function can be realized by software, an enormous amount of arithmetic processing is required as soon as the error correction capability becomes a plurality of bits, and a large load is imposed on the CPU to maintain a low error occurrence rate.

In the third technique, the EE originally mounted is used.
A backup memory different from the PROM is required. In this regard, in the literature describing the third technique, EPROM is used.
It is stated that the number of times of writing is reduced and the chance of being affected by an error during writing is reduced as compared with a case where the same data is written into each of the three divided. In short, we have found the advantage of using a backup memory other than the EEPROM.

According to a study by the present inventor, the flash memory on-chip in the microcomputer is used to store data and programs, and in the case of the data area, it is frequently rewritten like parameters. As expected, the program area is almost never rewritten except for version upgrades. In consideration of such a situation, the present inventor has found that it is necessary to purposefully optimize the function or performance of a plurality of storage areas.
For example, since the degree of deterioration in the characteristics of memory cells increases for storage applications such as parameters that require a large number of rewrites, priority is given to suppressing the decrease in reliability of information storage even if the memory cell usage efficiency is sacrificed. In the region where the temperature is good, the deterioration of the characteristics is slow, so it is appropriate to give priority to maximizing the usage efficiency of the memory cell.

The object of the present invention is to cope with a small number of rewritings and a large number of rewritings with one non-volatile memory,
It is an object of the present invention to provide a data processing device such as a microcomputer that does not need to be equipped with new hardware in order to improve the reliability of information storage or the upper limit number of rewrites.

Another object of the present invention is to prioritize suppression of deterioration in reliability of information storage in a region where rewriting is frequent with respect to one non-volatile memory, and to use a memory cell in a region where the number of rewriting is small. It is to provide a data processing device capable of giving priority to maximizing efficiency.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0013]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows.

That is, the data processing device has a CPU and a rewritable nonvolatile memory. The CPU is
When writing information in a specific block which is a part of the storage area in the non-volatile memory, one data is stored in memory cells of different addresses, and when reading data from the specific block, data is written from the memory cells of different addresses. Is read out, and a logical operation is executed on the read-out plurality of data, so that necessary error correction can be performed.

From the above, by writing a part of the area that is frequently rewritten to one non-volatile memory as the specific block and subjecting it to the necessary error correction processing, the information storage of the part of the storage area can be improved. It is possible to give priority to the suppression of reliability deterioration. Then, by maximizing the use efficiency of the memory cell by not treating it as the specific block in the area where the number of times of rewriting may be small, it can be prioritized. As a result, one nonvolatile memory can be used for applications where the number of rewrites is small to many, and new hardware is not required to improve the reliability of information storage or the upper limit of the number of rewrites.

The logical operation executed by the CPU is, for example, when the number of different addresses is 2 or more, the CP
It may be a logical OR operation or a logical AND operation by executing the instructions included in the instruction set of U. For example, when the non-volatile memory is a flash memory capable of storing information according to the level of the threshold voltage, the stored information of the memory cell is determined by the amount of electrons or holes held by the floating gate. If the stored information that responds to a state in which the threshold voltage is higher than the threshold voltage has a logical value of “1” and the stored information that responds to a lower state has a logical value of “0”, the higher threshold voltage will be Assuming that the data is changed to the lower side, by using a logical OR operation, unless all of the data stored at the different addresses for one data are inverted to “0”,
Undesired destruction of stored information from "1" to "0" due to characteristic deterioration can be prevented. On the other hand, assuming that the threshold voltage is changed from a lower value to a higher value due to characteristic deterioration, all the data stored at the different addresses are inverted to "1" by using a logical AND operation. Unless otherwise specified, due to characteristic deterioration
Undesired destruction of stored information from "0" to "1" can be prevented. On the contrary, for example, the storage information responding to the state in which the threshold voltage is higher than the threshold voltage in the thermal equilibrium state is the logical value "0", and the storage information responding to the low state is the logical value "1".
If it is assumed that the threshold voltage is changed from the higher side to the lower side due to the characteristic deterioration, by using the logical AND operation, all the data stored in the different plural addresses for one data is “1”. Unless it is inverted, it is possible to prevent undesired destruction of stored information from "0" to "1" due to characteristic deterioration. On the other hand, at this time, if it is assumed that the threshold voltage is changed from a lower value to a higher value due to the characteristic deterioration, all the data stored in the different plural addresses for one data is set to "0" by using the logical OR operation. Unless it is inverted to "", it is possible to prevent undesired destruction of stored information from "1" to "0" due to characteristic deterioration.

The logical operation executed by the CPU is
For example, when the number of the different addresses is 3 or more, the arithmetic processing may be a majority decision performed by executing a plurality of instructions. Both a defect from "1" to "0" and a defect from "0" to "1" can be dealt with.

The nonvolatile memory stores a program for storing the one data in a memory cell at a different address, a program for performing error correction, and another program in a block different from the specific block. You may

The specific block has a product specification that guarantees a larger number of rewrites than other blocks.

The nonvolatile memory is, for example, an electrically erasable and writable flash memory. CP
The U and the non-volatile memory may be formed on one semiconductor chip forming a microcomputer. Also, the CP
The U and the non-volatile memory may be formed on different semiconductor chips.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a microcomputer which is an example of a data processing device according to the present invention. The microcomputer 1 shown in the figure is a flash memory 2, a CPU 3, a RAM (random access memory), which is an example of a rewritable nonvolatile storage device.
4 and an interface circuit 5, which are connected by an internal address bus 6, an internal data bus 7 and a control bus (not shown). The interface circuit 5 can be connected to a peripheral circuit (not shown) or the like via an external address bus 8, an external data bus 9 and an external control bus (not shown). The microcomputer 1 shown in the figure is formed on a single semiconductor substrate or semiconductor chip such as single crystal silicon by a CMOS integrated circuit manufacturing technique, for example.

Although not shown in the drawing, the CPU 3 has an instruction control unit and a calculation unit, the instruction control unit fetches an instruction, decodes the fetched instruction, and generates a control signal according to the decoding result. Based on the control signal, the arithmetic unit executes an address arithmetic operation, a data arithmetic operation, etc. for realizing the instruction by the instruction. The RAM 4 is used as a work area of the CPU 3 or a temporary data storage area. The instruction set of the CPU includes a data transfer instruction, a logical operation instruction, an arithmetic operation instruction, a bit operation instruction, a branch instruction and the like. As logical operation instructions, there are generally instructions for performing logical operation processing such as AND, OR, and exclusive OR.

The flash memory 2 is not particularly limited as a non-volatile storage area in which non-volatile memory cells are arranged in a matrix, but a specific block area 11 as a first area where frequent rewriting is planned and a frequent area. The program area 12 is provided as a second area which is not scheduled to be rewritten. The program area 12 stores, for example, a program used for accessing the specific block area 11 and other programs. Figure 1
In the specific block area 11 and the program area 1
2 are shown as physically separated,
It can be located in the same memory array.

FIG. 2 illustrates the Ids-Vgs characteristics of the nonvolatile memory cell arranged in the nonvolatile storage area. In this example, the memory cells holding the logical values “0” and “1” are in the low threshold state and the high threshold state, respectively. Therefore, when an appropriate voltage is applied between the gate and the source (selection), the memory cell holding the logical values “0” and “1” becomes conductive and non-conductive between the drain and source, respectively, depending on the stored information. The data can be read.

FIG. 3 illustrates the structure of a non-volatile memory cell for producing the low threshold state and the high threshold state as shown in FIG. 2 and its write state and erase state. Although not particularly limited, here, a state where the threshold voltage of the non-volatile memory cell is high (“1” state) is a program (write) state, and a state where the threshold voltage of the non-volatile memory cell is low (“0” state). Defined as an erased state.

The non-volatile memory cell is of an n-channel type and floats on the channel forming region between the source SC and the drain DR formed in the P well (P type well region) PW via an oxide film. A gate FG is provided, and a control gate CG is stacked on the gate FG via a gate insulating film.

In the erase state, for example, a high positive voltage (10V) is applied to the source SC and a high negative voltage (-10V) is applied to the control gate CG, and the floating gate FG is applied.
From the source SC to the source SC. In the programmed state, for example, a positive voltage (7V) is applied to the drain DR, a circuit ground voltage (0V) is applied to the source SC, and a high positive voltage (10V) is applied to the control gate CG,
This is achieved by passing a current between the drain and the source and accumulating hot electrons generated thereby in the floating gate FG.

FIG. 4 shows an example of the flash memory. In the figure, a large number of non-volatile memory cells 21, which are typically shown, are arranged in a matrix in a memory array 20. The control gate (CG) of the nonvolatile memory cell is connected to the word line 22, the drain (DR) is connected to the bit line 23, and the source (SC) is connected to the source line 24. Although not shown, the word line 22 and the bit line 2
Many 3 and source lines 24 are arranged in the matrix direction of the memory cell 21.

The X decoder 25 decodes the X address supplied to the address buffer 26 and selectively drives the word line 22. The drive voltage of the word line 22 is determined according to the operating power supply voltage supplied from the power supply circuit 27 according to the operation mode of the flash memory such as reading and writing. The source / substrate control circuit 28 selectively controls the voltages of the source line 24 and the well region of the nonvolatile memory cell 21. The voltage supplied to the source line 22 and the well region is determined by the voltage of the operation power supply supplied from the power supply circuit 27 according to the operation mode of the flash memory. The bit line 23 is selected by the Y selector 29 and connected to the sense amplifier 30 or the write buffer 31. The Y decoder 32 decodes the Y address supplied to the address buffer 26 and generates a selection control signal for the Y selector 29. The write buffer 31 latches write data via the input buffer 33, and drives the bit line 23 to change the erased memory cell 21 to the programmed state. The bit line drive voltage is determined by the voltage of the operating power supply supplied from the power supply circuit 27 according to the operating mode. The sense amplifier 30 amplifies the read signal read from the memory cell to the bit line by the verify operation in the read operation or the write operation. The amplified read signal is output buffer 34 as read data.
Is output to the internal data bus 7.

The control unit 36 receives the access instruction from the CPU 3 and controls the internal operation of the flash memory 2. When the CPU 2 instructs the read operation to the control unit 36,
The address given from the internal address bus 6 is decoded by the X decoder 25 and the Y decoder 32 to select the word line 21 and the bit line 23, thereby selecting the memory cell corresponding to the access address. The control unit 36 activates the sense amplifier 30 and the output buffer 34 during the read operation and outputs the read data to the internal data bus 7.

The control unit 36 has a control register REG for writing operation, and the control register R by the CPU 3 is used.
A write operation is performed according to the setting state of EG. The control register REG has control bits such as a program bit P and an erase bit E, and further has a designated area EBLK of an erase block (erase area). Here, erasing is performed by using a memory cell group having a common source line as a minimum unit, and an erasing block is designated by designating an erasing target block from a plurality of blocks each having a common source line. The minimum unit of data rewriting is the erase block unit. When the erase bit E is enabled, the erase voltage for the erase state is applied to the memory cells in the block designated by the erase block designation area EBLK. The erase voltage is applied in a plurality of times, each time a verification is made as to whether or not the specified threshold voltage has been reached, and when the specified threshold voltage is reached, the operation to the erased state is terminated. When the program bit P is enabled, the program voltage application and the program voltage application for the program state are applied to the target memory cell of the write operation specified by the address according to the logical value of each bit of the write data. Blocking is controlled. The application of the program voltage is divided into a plurality of times, and each time, verification is performed as to whether or not the specified threshold voltage has been reached, and when the specified threshold voltage is reached, the operation to the programmed state ends.

Next, a write operation and a read operation for improving the reliability of information storage in the specific block area 11 in which rewriting is frequently performed will be described. The CPU 3 stores one data in memory cells of different addresses when writing information in the specific block area 11, and reads data from memory cells of different addresses when reading data from the specific block area 11, A logical operation is performed on the read plurality of data to perform necessary error correction. On the other hand, the CPU 3 performs a conventional flash memory access to the program area 12 and performs processing such as duplicate writing of one data to another address and necessary error correction based on the duplicate data read from the corresponding address. Absent.

FIG. 5 exemplifies a processing flow of duplicate writing of one data to another address and necessary error correction based on the duplicate data read from the corresponding address. The CPU 3 controls the processing flow. In short, the duplication writing of one data to another address and the necessary error correction processing based on the duplication data read from the corresponding address are defined by the operation program of the CPU 3. This program may be provided to the user by the manufacturer of the microcomputer, or may be created by the chip user.

Specific block area 11 executed by CPU 3
The access program for accessing the data is roughly classified into one that controls the data write operation and one that controls the data read operation. From the description, the CPU 3 executes steps S1 to S4 if the data is written, and steps S5 to S9 if the data is read.

The case of writing one data will be described. The specific block area 11 is assumed to include 2K addresses from A0 to A0 + 2K-1, as illustrated in FIG. When writing to the specific block area 11, first, in order to specify the address to be written, the address Ai is set in the address register of the CPU 3.
(A0≤Ai≤A0 + K-1) is set and output to the internal address bus 6 (S1), the program bit P of the flash memory 2 is set via the internal data bus 7, and the write data Di is output. The data Di is written to the address Ai of the flash memory 2 (S2). The operation itself of the address setting (S1) and data writing (S2) is the same as the program and program verify operation in the normal operation. Next, shift the write address by K (set to Ai + K) CP
It is set in the address register of U3, the address is output to the internal address bus 6 (S3), and the same data Di as described above is written to the address Ai + K of the flash memory 2 (S4). The operation itself of the address setting (S3) and data writing (S3) is the same as the program and program verify operation in the normal operation.

The case of reading data will be described.
First, the address Ai of the flash memory to be read
(A0 ≦ Ai ≦ A0 + K-1) is output to the bus 6 (S
5), CPU3 register (eg general-purpose register) R0
The data is loaded into (S6). Next, the address (Ai + K) shifted by K is output to the bus 6 (S7), and CP
The data is loaded into the register (for example, general-purpose register) R1 of U3 (S8). Now, it is assumed that the state in which the floating gate of the flash memory cell has a charge and the state in which there is no charge correspond to logical values "1" and "0", respectively. A defect in which the charge that originally existed in the floating gate disappears (a defect in which the logical value "1" turns into a logical value "0")
Assuming that only the error occurs and the opposite does not occur, the CPU 3 is caused to execute the logical OR operation instruction of the value of the register R0 and the value of the register R1 (S9). This allows
As a result of the logical OR operation, if a defect occurs in only one of the data, the error is corrected and the original correct value is obtained. Therefore, the CPU 3 has such a logical OR.
By processing the calculation result as read data,
The reliability of data that is frequently rewritten in the flash memory 2 can be improved, and the number of guaranteed rewrites can be substantially increased. In the example of FIG. 5, the data is written twice and the logical OR operation is performed for reading, but when the data is written three times or more and the logical OR operation is performed and read, the cell is used. Less efficient, but more reliable data.

When accessing (writing and reading) other blocks other than the specific block area 11, the user performs the access by a normal method without activating the above access program. Therefore, since the data is not redundantly provided in the other blocks, the cell use efficiency does not deteriorate, but the reliability of the data as much as the specific block area 11 cannot be maintained, and the guaranteed rewrite count in the specific block area 11 is not maintained. Less than the value. A user who does not require a particularly high number of rewrites in all the blocks including the specific block area 11 does not start the cell in all blocks unless the above-mentioned access program to the specific block area 11 is started even when accessing the specific block area 11. It does not deteriorate the usage efficiency. Further, for a user who needs a large number of rewriting times in some of the other blocks in addition to the specific block area 11, an access program for performing the above-mentioned multiple write and logical OR operation in these plural blocks Can be dealt with by providing. In this way, it is possible to meet the needs of various users by only using / not using a program such as an access program to a specific block area, or by changing the content, and there is no need to change the hardware configuration of the flash memory at all. .

When the above-mentioned access program to the specific block area is applied, since reading from the block to be applied (for example, the specific block area 11) requires a plurality of CPU instruction steps for one data, the wait is performed. It is not possible to continuously access data randomly without cycles. As a suitable application example of the present invention, an application is conceivable in which data is written from the RAM 4 to the flash memory 2 before power-off of the system, and data is read from the flash memory 2 to the RAM 4 immediately after power-on. For example, the learned value and the self-diagnosis result of the in-vehicle component are stored in the flash memory 2 in the vehicle-mounted electronic control device, and the favorite set value designated by the user in the air-conditioning system is stored in the flash memory 2.
Flash memory 2 in the video game device
It can be used for such purposes as storing in.

In FIG. 7, it is assumed that the defect occurring in the flash memory is the opposite of that of FIG. 5, and one data is duplicately written to another address and the necessary data is read based on the duplicated data read from the corresponding another address. A processing flow of error correction is illustrated. Here, contrary to the case of FIG. 5, it is an example of an access program to a specific block area when dealing with a defect in which a logical value “0” becomes a logical value “1”. The difference from FIG. 5 is that step S9 is changed to step S9a, and in step S9a, a logical AND operation instruction is executed at the time of reading. In this case as well, the result of the logical AND operation is corrected to an error and becomes an original correct value if at most one of the data has a defect. Therefore, the CPU 3 can improve the reliability of the data frequently rewritten in the flash memory 2 by processing the result of such logical AND operation as the read data, and substantially increase the guaranteed rewrite frequency. Can be made. In the example of FIG. 7, the data is written twice and the logical AND operation is performed for reading. However, when the data is written three times or more and the logical AND operation is performed and read, the cell is used. Less efficient, but more reliable data.

FIG. 8 shows three addresses (A
i, Ai + K, Ai + 2K), and the control flow of writing and reading by an access program that writes and outputs the same data by reading the majority logic at the time of reading.

Programs for accessing the specific block area executed by the CPU 3 are roughly classified into those which control the data write operation and those which control the data read operation. From the description, the CPU 3 executes steps S11 to S16 if the data is written, and executes the steps S17 to S26 if the data is read.

The case of writing one data will be described. As illustrated in FIG. 9, the specific block area 11 is assumed to include 3K addresses from A0 to A0 + 3K-1. When writing to the specific block area 11, first, in order to specify the address to be written, the address Ai is set in the address register of the CPU 3.
(A0≤Ai≤A0 + K-1) is set and output to the address bus 6 (S11), the program bit P of the flash memory is set via the internal data bus 7, and the write data Di is output to output the flash memory 2 The data Di is written to the address Ai (S12). The address setting (S11) and data writing (S12) operations themselves are the same as the program and program verify operations in the normal operation. Next, the write address is shifted by K and set in the address register of the CPU 3 (set to Ai + K) and output to the internal address bus 6 (S13).
The same data Di as described above is written in i + K (S14).
This address set (S13) and data writing (S1
4) The operation itself is the same as the program and program verify operation in the normal operation. Furthermore,
The write address is shifted by 2K and set in the address register of the CPU 3 (set to Ai + 2K) and output to the address bus 6 (S15), and the same data Di is written to the address Ai + 2K of the flash memory (S).
16). The address setting (S15) and data writing (S16) operations themselves are the same as the program and program verify operations in the normal operation.

The case of reading data will be described.
First, the address Ai of the flash memory to be read
(A0 ≦ Ai ≦ A0 + K-1) is output to the bus 6 (S1
7), CPU3 register (for example, general-purpose register) R0
The data is loaded into (S18). For example, R0 = 011
0 is loaded. Next, the address shifted by K (A
i + K) is output to the bus 6 (S19), and data is loaded into the register (for example, general-purpose register) R1 of the CPU 3 (S20). For example, R1 = 0111 is loaded. Furthermore, the address (Ai + 2K) shifted by 2K is used for bus 6
(S21), and the data is loaded into the register (for example, general-purpose register) R2 of the CPU 3 (S22). For example, R2 = 0111 is loaded.

Here, in general, three values (P, Q, R)
Majority logic is (P ・ / Q + / P ・ Q) ・ R + P ・ Q
Represented by The symbol / means the inversion of the value to which it is attached. In steps S23 to S25, the operation is executed by a combination of logical operation instructions included in the instruction set of a general microcomputer. In step S23, register R
An exclusive OR operation is performed on the data of 0 and the data of the register R1 to obtain the operation result in the register R3. In step S24, the data in the register R0 and the register R1
And the result of the logical AND operation is stored in the register R1. In step S25, a logical AN is applied to the data in register R2 and the data in register R3.
The D operation is performed and the operation result of s is stored in the register R2. In step S26, the logical OR operation of R1 and R2 is performed and the result is stored in R1. The result of the operation obtained in the register R1 in step S26 is set as two matching data among the three data. Therefore, the CPU 3 can improve the reliability of the data frequently rewritten in the flash memory 2 by processing the result of such a majority logic operation as the read data. In particular, as compared with the examples of FIGS. 5 and 7, the use efficiency of the memory cell is deteriorated and the number of instruction steps is increased, but there is a disadvantage that the logical value changes from “1” to “0” and “0”. There is a merit that it is possible to deal with both defects that change from "1" to "1".

FIG. 10 shows an example of a data processing device using an off-chip flash memory. In FIG. 10, a microcomputer 1A and a flash memory 2A
Are formed on separate chips, and the microcomputer 1A
The flash memory 2 is not on-chip, and the flash memory 2A is independently made into a semiconductor integrated circuit. Even in the configuration of FIG. 10, the flash memory 2A
Has the specific block area 11, and writing and reading to and from the specific block area 11 are performed by the microcomputer 1 as described above.
It is controlled by a program executed by the CPU 3 of A. Even in this multi-chip configuration, it is possible to relax the substantial limit of the number of times of rewriting of a specific block area of the flash memory 2A that is frequently rewritten, and improve the reliability of the frequently rewritten data.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited thereto, and it goes without saying that various modifications can be made without departing from the scope of the invention. Yes.

For example, writing and erasing are relative concepts, and may be defined in reverse to the above. The method of injecting electrons into the floating gate of the flash memory is not limited to hot electron injection, and tunnel injection may be used. Further, the non-volatile memory is not limited to a configuration in which one memory cell holds binary data, and may have a configuration in which multi-value storage of four values or the like is performed. Further, the non-volatile memory is not limited to the flash memory and may be a rewritable structure having another storage format such as a ferroelectric memory. Further, the flash memory cell transistor may be a p-channel type.

The method of dividing the specific block area is shown in FIG.
9 is not limited to the method of separating by giving an offset such as K as illustrated in FIG. 9, and it is theoretically possible to sequentially set the areas in which one data is written to adjacent addresses. . It is easier to create a program and easier to grasp the data by the method of separating by giving an offset such as K pieces.

The circuit module included in the data processing device is not limited to the RAM or the interface circuit, but may be a ROM, a coprocessor, an accelerator, or other peripheral circuits.

[0050]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, a part of the non-volatile memory that is frequently rewritten is set as a specific block. When writing to this specific block, duplicate writing of one data to another address is performed, and when reading, correspondence is determined. Since the error correction is performed based on the duplicated data read from the address and both the above processes are realized by the program of the CPU, priority should be given to suppressing the deterioration of reliability of information storage with respect to a part of the storage area of the nonvolatile memory. You can It is possible to give priority to maximizing the use efficiency of the memory cell by not treating the area as the specific block in the area where the number of times of rewriting may be small.
As a result, one nonvolatile memory can be used for applications where the number of rewrites is small to many, and new hardware is not required to improve the reliability of information storage or the upper limit of the number of rewrites.

Logical OR for logical operation executed by the CPU
If either the operation or the logical AND operation is adopted, it is possible to deal with only one of the defects of the stored information, "1" to "0" or "0" to "1". The use efficiency of the memory cell need only be reduced by half compared to the usual case. If majority logic is adopted for the logical operation, it is possible to deal with both the defect from "1" to "0" and the defect from "0" to "1".

[Brief description of drawings]

FIG. 1 is a block diagram showing a microcomputer which is an example of a data processing device according to the present invention.

FIG. 2 is a characteristic diagram illustrating an Ids-Vgs characteristic of a nonvolatile memory cell arranged in a nonvolatile storage area.

FIG. 3 is an explanatory diagram illustrating the structure of a nonvolatile memory cell for producing the low threshold state and the high threshold state shown in FIG. 2, and its erase state and program state.

FIG. 4 is a block diagram showing an example of a flash memory.

FIG. 5 is a flowchart illustrating a processing flow of duplicate writing of one data to another address and necessary error correction (logical OR operation) based on the duplicate data read from the corresponding address.

FIG. 6 is an explanatory diagram illustrating a usage pattern of a specific block specific block area including 2K addresses from A0 to A0 + 2K−1.

FIG. 7 is a flowchart illustrating a processing flow of duplicate writing of one data to another address and necessary error correction (logical AND operation) based on duplicate data read from the corresponding address.

FIG. 8 shows three addresses (Ai, Ai + K, Ai + 2).
9 is a flow chart illustrating a control flow of writing and reading by an access program that writes the same data to K) and adopts and outputs these majority logics at the time of reading.

FIG. 9 is an explanatory diagram illustrating a usage pattern of a specific block area 11 including 3K addresses from A0 to A0 + 3K-1.

FIG. 10 is a block diagram illustrating a data processing device using an off-chip flash memory.

[Explanation of symbols]

1 microcomputer 1A microcomputer 2 Flash memory 2A flash memory 3 CPU 11 Specific block area 12 program area 21 Non-volatile memory cell

Claims (10)

[Claims] 1. In a data processing device having a CPU and a rewritable nonvolatile memory, the CPU differs from one data when writing information to a specific block which is a part of a storage area in the nonvolatile memory. When the data is stored in the memory cell of the address and the data is read from the specific block, the data is read from the memory cell of the different address, and the necessary error correction is performed by executing the logical operation on the read plurality of data. A data processing device, which is capable of 2. The semiconductor integrated device according to claim 1, wherein the number of different addresses is two or more, and the logical operation is a logical OR operation by executing an instruction included in an instruction set of the CPU. circuit. 3. The semiconductor integrated device according to claim 1, wherein the number of different addresses is two or more, and the logical operation is a logical AND operation by executing an instruction included in the instruction set of the CPU. circuit. 4. The number of the different addresses is 3 or more, and the logic operation is performed on a plurality of data read from the memory cells of the different addresses by executing an instruction included in an instruction set of the CPU. The semiconductor integrated circuit according to claim 1, wherein the operation is a calculation. 5. The non-volatile memory has a program area for storing a program executed by the CPU as an area different from the specific block. The semiconductor integrated circuit according to claim 1. 6. The program area holds a program for storing the one data in memory cells at different addresses, a program for performing the error correction, and other programs. The semiconductor integrated circuit according to claim 5. 7. The semiconductor integrated circuit according to claim 1, wherein the specific block has a product specification that guarantees a larger number of rewrites than other blocks. 8. The semiconductor according to claim 1, wherein the non-volatile memory is a flash memory capable of storing information depending on whether the threshold voltage of a memory cell is high or low. Integrated circuit. 9. The semiconductor integrated circuit according to claim 1, wherein the CPU and the non-volatile memory are formed on one semiconductor chip forming a microcomputer. . 10. The semiconductor integrated circuit according to claim 1, wherein the CPU and the non-volatile memory are respectively formed on separate semiconductor chips.