JP2002523913A5 - - Google Patents
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- Publication number
- JP2002523913A5 JP2002523913A5 JP2000565606A JP2000565606A JP2002523913A5 JP 2002523913 A5 JP2002523913 A5 JP 2002523913A5 JP 2000565606 A JP2000565606 A JP 2000565606A JP 2000565606 A JP2000565606 A JP 2000565606A JP 2002523913 A5 JP2002523913 A5 JP 2002523913A5
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/134,248 US6148317A (en) | 1998-08-14 | 1998-08-14 | Method and apparatus for compressing signals in a fixed point format without introducing a bias |
| US09/134,248 | 1998-08-14 | ||
| PCT/US1999/018546 WO2000010253A2 (en) | 1998-08-14 | 1999-08-13 | A method and apparatus for compressing signals in a fixed point format without introducing a bias |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2002523913A JP2002523913A (ja) | 2002-07-30 |
| JP2002523913A5 true JP2002523913A5 (US07585860-20090908-C00162.png) | 2006-10-05 |
| JP4354648B2 JP4354648B2 (ja) | 2009-10-28 |
Family
ID=22462453
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000565606A Expired - Fee Related JP4354648B2 (ja) | 1998-08-14 | 1999-08-13 | バイアスを招かないで固定少数点フォーマットに信号を圧縮するための方法と装置 |
Country Status (11)
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6243728B1 (en) * | 1999-07-12 | 2001-06-05 | Sony Corporation Of Japan | Partitioned shift right logic circuit having rounding support |
| GB0031771D0 (en) * | 2000-12-29 | 2001-02-07 | Lsi Logic Corp | Bit reduction using dither,rounding and error feedback |
| JP3755602B2 (ja) * | 2003-03-04 | 2006-03-15 | ソニー株式会社 | 信号処理装置、信用処理装置用プログラム、信号処理装置用プログラムを記録した記録媒体、及び信号処理方法 |
| US8301803B2 (en) * | 2009-10-23 | 2012-10-30 | Samplify Systems, Inc. | Block floating point compression of signal data |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3199371B2 (ja) * | 1990-07-30 | 2001-08-20 | 松下電器産業株式会社 | 丸め装置 |
| JPH05503178A (ja) * | 1990-11-09 | 1993-05-27 | アダプティブ・ソリューションズ・インコーポレーテッド | 偏りのないビット廃棄装置および方法 |
| US5214598A (en) * | 1990-11-09 | 1993-05-25 | Adaptive Solutions, Inc. | Unbiased bit disposal apparatus and method |
| US5424967A (en) * | 1993-11-29 | 1995-06-13 | Hewlett-Packard Company | Shift and rounding circuit and method |
| US5696710A (en) * | 1995-12-29 | 1997-12-09 | Thomson Consumer Electronics, Inc. | Apparatus for symmetrically reducing N least significant bits of an M-bit digital signal |
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1998
- 1998-08-14 US US09/134,248 patent/US6148317A/en not_active Expired - Lifetime
-
1999
- 1999-08-13 DE DE69918313T patent/DE69918313T2/de not_active Expired - Fee Related
- 1999-08-13 WO PCT/US1999/018546 patent/WO2000010253A2/en not_active Application Discontinuation
- 1999-08-13 RU RU2001107011/09A patent/RU2233024C2/ru not_active IP Right Cessation
- 1999-08-13 AT AT99941157T patent/ATE270009T1/de not_active IP Right Cessation
- 1999-08-13 CN CN99811666A patent/CN1321269A/zh active Pending
- 1999-08-13 AU AU54866/99A patent/AU767325B2/en not_active Ceased
- 1999-08-13 CA CA002340421A patent/CA2340421A1/en not_active Abandoned
- 1999-08-13 JP JP2000565606A patent/JP4354648B2/ja not_active Expired - Fee Related
- 1999-08-13 EP EP99941157A patent/EP1110325B1/en not_active Expired - Lifetime
- 1999-08-13 KR KR1020017001935A patent/KR20010072504A/ko not_active Application Discontinuation
