JP2002374234A - Bit synchronization circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a bit synchronization circuit that can normally extract data, so as to realize high-speed data transfer whose duty is deteriorated due to a difference of a delay time between a trailing of the data and a leading of the data at high-speed data transmission. SOLUTION: The bit synchronization circuit is provided with a clock generating means, an input data leading/trailing detection means, a data width detection means that detects a data width from the detected leading/trailing, a reference phase detection means that detects a reference phase from the data width, a reference phase selection means that selects the detected reference phase, a data width correction means that corrects the data width, on the basis of the selected reference phase, and a data extract means that extracts the data, on the basis of the corrected leading/trailing edges. The bit synchronization circuit extracts the received data, whose leading/trailing edges have a constant phase difference and whose duty has deteriorated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bit synchronization circuit, and more particularly, to a bit synchronization circuit that normally extracts data with a changed duty and realizes high-speed data transfer.

[0002]

2. Description of the Related Art FIG.
FIG. 36 is a block diagram showing a configuration of a conventional bit synchronization circuit disclosed in Japanese Patent Publication No. 36-36. As shown in the figure, the bit synchronization circuit includes a rise / fall detection circuit, a center phase detection circuit, a phase selection circuit, and a data extraction circuit.

FIG. 9 is an operation timing chart of the conventional bit synchronization circuit. Data extraction is performed as follows. The rise / fall detection circuit detects the rise / fall of data. The retiming point having the largest margin (near the center of the data) is calculated by the center phase detection circuit. A clock selectable at the retiming point is selected by a phase selection circuit. Extract data at the selected clock.

[0004]

Since the conventional bit synchronization circuit is configured as described above, the problem arises that the duty is lost due to the difference between the delay time of the rising edge and the falling edge of the data as the data speeds up. However, if the data is taken in at the center of the data as in the above-described conventional bit synchronization circuit, the data cannot be normally extracted (FIG. 11).

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and it is possible to normally extract data whose duty is lost due to a difference between a fall time and a rise delay time in high-speed data transmission, and to realize high-speed data transmission. An object of the present invention is to obtain a bit synchronization circuit for realizing data transfer.

[0006]

A bit synchronizing circuit according to the present invention comprises a clock generating means for generating a plurality of clocks having different phases from a reference clock, and a rise / fall detection for detecting a rise / fall from input data. Means, data width detecting means for detecting a data width from rising / falling detected by the rising / falling detecting means, and reference phase detecting means for detecting a reference phase from the data width detected by the data width detecting means. A reference phase selector for selecting a reference phase detected by the reference phase detector, a data width corrector for correcting a data width based on the reference phase selected by the reference phase selector, and a data width corrector. Data extraction means for extracting data based on rising / falling edges corrected by , And extracting the broken data duty rising / falling edge is respectively received while maintaining a constant phase.

Further, the clock generation means for generating a plurality of clocks having different phases from the reference clock, the rise / fall detection means for detecting the rise / fall from the input data, and the rise / fall detection means A data width detecting means for detecting a data width from a rise / fall, a reference phase detecting means for detecting a reference phase from a data width detected by the data width detecting means, and a reference phase detected by the reference phase detecting means Reference phase selecting means, delay means for delaying a rising / falling signal based on the reference phase selected by the reference phase selecting means, and delay means for delaying rising / falling based on the reference phase. Data width correcting means for correcting the data width, and a height corrected by the data width correcting means. It includes a data extracting means for extracting the data based on the rise / fall edge, a rising /
The present invention is characterized in that data whose duty is changed without falling edges, such as long-period jitter, that is not maintained at a fixed phase, is extracted.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. Embodiment 1 FIG. 1 to 4 show the first embodiment, FIG. 1 shows the definition of the input data waveform, FIG. 2 is a block diagram showing the configuration of the bit synchronization circuit, and FIG. FIG. 4 is a timing chart, and FIG.
FIG. 11 is an operation timing chart of the case of FIG.

An input data waveform is defined as shown in FIG.
In FIG. 1, Ta + Tb = 2. Here, Ta =
ta / F, Tb = tb / F, F = one cycle time of ideal data. (ta, tb) = each cycle of input data. Here, Ta ≦ Tb is defined as ｛Ta = 1−a, Tb = 1 +
a, a> 0｝. For this input data, (Ta, Tb) → (Ta ′, Tb ′) = (Ta + a, T
When the data width conversion of b−a) is performed, Ta ′ = (1−a) + a = 1, and Tb ′ = (1 + a) −a = 1, and the conversion of ta = Ta ′ · F and tb = Tb ′ · F , The input signals having the period F are restored.

Actually, the present algorithm is realized by configuring the bit synchronization circuit of FIG. 2 (FIGS. 3 and 4). As shown in FIG. 2, the bit synchronization circuit includes a polyphase clock source, a rise / fall detection circuit, a data width correction circuit,
It is composed of a data restoration unit.

In the multi-phase clock source, a multi- (N) -phase clock having the same frequency as the input data is created in the receiving LSI (FIG. 3 * 1). The rise / fall detection circuit detects the rise / fall of the input data based on the N-phase clock (FIG. 3 * 2).

The data width correction circuit operates using the following algorithm (FIG. 3 * 3). (A) The criterion for data extraction is either rising or falling timing. (B) If a falling edge is input within one clock after the rising edge is detected, or a rising edge is detected within one clock after the falling edge is detected, the detected phase on the front side is used as the reference phase. (C) If the next fall is detected one clock or more after the rise is detected, or if the next rise is detected one or more clocks after the fall is detected, the reference phase is not changed.

The data restoration unit sets the data to "H" after the rising edge and sets the data to "L" after the falling edge based on the corrected rising / falling edge output from the data width correcting circuit. Is restored (Fig. 3 * 4).

According to the above-described embodiment, it is possible to extract data with a changed duty, and to perform high-speed data transfer. As a prerequisite in this case, it is assumed that the rising / falling edges are received with a fixed phase.

Embodiment 2 5 to 7 show the second embodiment. FIG. 5 shows the definition of the input data waveform.
7 is an operation timing chart of the case of the input data example 4, and FIG. 7 is an operation timing chart of the case of the input data example 5. An input waveform is defined as shown in FIG. In FIG. 5, Ta +
Define Tb = 2 + D. Here, similarly to the first embodiment, Ta ≦ Tb ｛Ta = 1 + D / 2−a, Tb = 1 + D / 2
+ Ta, a> 0} and (Ta, Tb) → (Ta ″, T
b ″) = (Ta− (D / 2−a), Tb− (D / 2 +
a)), the following is obtained: Ta ″ = (1 + D / 2−a) − (D / 2−a) = 1 Tb ″ = (1 + D / 2 + a) − (D / 2 + a) = 1, and ta = Ta ".F and tb = Tb" .F, the input signal having the period F is restored.

Actually, the present algorithm is realized by configuring the following circuit. A multiple (N) phase clock having the same frequency as the input data is created in the receiving LSI (FIG. 3 * 1). The rising / falling edge of the input data is detected based on the N-phase clock (FIG. 3 * 2).

The data width correction circuit operates using the following algorithm (FIGS. 6 and 7). (A) The reference for data extraction is either rising or falling timing. (B) If a falling edge is input within one clock after the rising edge is detected, or a rising edge is detected within one clock after the falling edge is detected, the detected phase on the front side is used as the reference phase. (C) If the next fall is detected one clock or more after the rise is detected, or if the next rise is detected one or more clocks after the fall is detected, the reference phase is not changed. (D) Insert a delay of δ into the detected rising / falling signal. (E) After the δ delay, the rising / falling is retimed by the reference phase.

Based on the corrected rising / falling edge output from the data width correction circuit, the data restoring unit sets the data to "H" after the rising edge, and sets the data to "L" after the falling edge to change the data to "L". Restore (Fig. 3 * 4). However, when the data is restored based on the reference clock, ta
= Ta "(1 + D / 2) F, tb = Tb" (1 + D /
2) It becomes F.

Since ta and tb ≠ F as described above, the reference clock is transmitted in parallel with the data at the time of restoration. This clock cycle is (1 + D / 2) F. Actually, the data is transmitted after a delay corresponding to the time required for the restoration is inserted in the data restoration unit.

In the above-described second embodiment, bit synchronization can be performed without erroneous recognition even when the rising / falling edges are not received while maintaining a constant phase, such as when receiving long-period jitter. .

[0021]

According to the bit synchronization circuit of the first aspect, it is possible to extract data whose duty has been lost, thereby performing high-speed data transfer. As a prerequisite in this case, it is assumed that the rising / falling edge is received with a constant phase.

The bit synchronization circuit according to the second aspect is capable of performing bit synchronization without erroneous recognition even when the rising / falling edge is not received while maintaining a fixed phase, such as receiving long-period jitter. Become.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a first embodiment and is a diagram illustrating definitions of input data waveforms.

FIG. 2 is a diagram illustrating Embodiment 1 and is a block diagram illustrating a configuration of a bit synchronization circuit.

FIG. 3 is a diagram illustrating the first embodiment and is an operation timing chart in the case of input data example 1;

FIG. 4 is a diagram showing the first embodiment, and shows input data examples 2 and 3;
FIG. 14 is an operation timing chart of the third case.

FIG. 5 is a diagram illustrating the second embodiment, and is a diagram illustrating definitions of input data waveforms.

FIG. 6 shows the second embodiment, and is an operation timing chart in the case of input data example 4;

FIG. 7 shows the second embodiment, and is an operation timing chart in the case of input data example 5;

FIG. 8 is a block diagram showing a configuration of a conventional bit synchronization circuit.

FIG. 9 is an operation timing chart of a conventional bit synchronization circuit.

FIG. 10 is an operation timing chart when the duty of the conventional bit synchronization circuit is changed.

FIG. 11 is an operation timing chart of a conventional bit synchronization circuit when data cannot be normally extracted.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Tetsuhiro Fuka 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Inside Mitsubishi Electric Corporation (72) Inventor Harubo Kondo 2-3-2 Marunouchi, Chiyoda-ku, Tokyo (72) Inventor Masahiko Ishiwaki 2-3-2 Marunouchi, Chiyoda-ku, Tokyo F-term (reference) 5J106 BB02 CC21 DD09 DD26 KK02 KK25 5K029 AA11 BB03 CC01 DD02 DD22 EE04 FF10 HH13 HH27 5K047 AA06 GG07 GG09 GG24 GG29 MM36

Claims (2)

[Claims] 1. A clock generating means for generating a plurality of clocks having phases different from each other from a reference clock; a rising / falling detecting means for detecting rising / falling from input data; A data width detecting means for detecting a data width from a rise / fall, a reference phase detecting means for detecting a reference phase from a data width detected by the data width detecting means, and a reference phase detected by the reference phase detecting means Reference width selecting means for performing data width correction on the basis of the reference phase selected by the reference phase selecting means; and a rising / falling edge corrected by the data width correcting means. Data extracting means for extracting data, wherein rising and falling edges each maintain a fixed phase. A bit synchronization circuit for extracting data with a changed duty received by the bit synchronization circuit. 2. A clock generating means for generating a plurality of clocks having phases different from each other from a reference clock; a rising / falling detecting means for detecting rising / falling from input data; A data width detecting means for detecting a data width from a rise / fall; a reference phase detecting means for detecting a reference phase from a data width detected by the data width detecting means; and a reference phase detected by the reference phase detecting means. Reference phase selecting means, delay means for delaying a rising / falling signal based on the reference phase selected by the reference phase selecting means, and delay means for delaying rising / falling based on the reference phase. A data width correcting means for correcting the data width, and a height corrected by the data width correcting means. Data extracting means for extracting data based on rising / falling edges, and extracting data with irregular duty which rising / falling edges are received without maintaining a constant phase such as long-period jitter. A bit synchronization circuit.