JP2002369147A - Data processor and data processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data processor and a data processing method which reduce an overhead of a device on a host side, and can obtain a superior data recording and reproduction. SOLUTION: The following devices solve the problems. A buffer memory 10 is divided into a plurality of storage regions 104 to 107, 119 for management, and reproduced data is stored in the first storage regions 104 to 106 of the plurality of storage regions 104 to 107, 119. A descriptor is downloaded from a host controller and the descriptor is stored in the second storage region 119. A programmable controller reads the descriptor from the second region, and data I/O operations and data storage operations of the buffer memory 10 are independently controlled from the host controller via a buffer memory manager based on this descriptor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention has a plurality of circuit blocks,
A first circuit block of the plurality of circuit blocks;
The present invention relates to a data processing device for transferring data via a transfer bus between a second circuit block and a buffer memory for buffering data, and a data processing method.

[0002]

2. Description of the Related Art As in the system disclosed in U.S. Pat. No. 5,799,209 (patent date: Aug. 29, 1998), in a conventional system, a central processing unit is used as a host and provided therein. Parallel port is connected to a plurality of target circuit blocks via a bus line, and an arbiter functioning as a data processing device receives an instruction from a central processing unit and transfers data via a bus line. DRA which is a control and buffering memory
For the cache control of M, data arbitration control and cache control are performed each time an instruction from the central processing unit is received.

That is, the central processing unit, which is the host, controls the arbiter in a state where the arbiter is subordinate to the slave, and performs data arbitration control and cache control.
Although an arbiter intervenes, it cannot be executed unless an instruction from the central processing unit is received for each control job, and the central processing unit, which is the host, increases the amount of control jobs processed per unit time, and There is a lot of overhead, which is the load of the system.

[0004] Such a large amount of overhead hinders the continuity of data transfer required for recording or decoding of video data or compressed video data, and stops recording or interrupts an image displayed on a monitor. Was causing it.

[0005]

As described above, in the data processing device, the overhead in the host device has broken the continuity of data reproduction.

Accordingly, an object of the present invention is to provide a data processing device and a data processing method capable of reducing overhead of a host device and reproducing data satisfactorily.

[0007]

To solve the above problems, a data processing apparatus according to the present invention comprises a first circuit block,
A second circuit block, the first circuit block and a second
A bus for transferring data between the first and second circuit blocks, a host control circuit for transferring first instruction data for controlling the operation of the first circuit block and the second circuit block, and a transfer through the bus A buffer memory for storing the data to be stored, a buffer memory manager for controlling the buffer memory and storing the data, and a second command data supplied from the host control circuit, and using the buffer memory manager A programmable control circuit for controlling a data input / output operation of the buffer memory and a data storage operation, and manages the buffer memory by dividing the buffer memory into a plurality of storage areas; Storing the data in the storage area of, downloading the second command data from the host control device, Storing the second instruction data in the second storage area, the programmable control circuit, the second
Reading the instruction data from the second area, and controlling the data input / output operation and the data storage operation of the buffer memory via the buffer memory manager based on the second instruction data. And

According to another aspect of the present invention, there is provided a data processing method comprising: a first circuit block; a second circuit block; and a first circuit block between the first circuit block and the second circuit block. A bus for transferring data, a host control circuit for transferring first command data for controlling operations of the first circuit block and the second circuit block via the bus, and data transferred for the bus A buffer memory that stores the data, a buffer memory manager that controls the buffer memory to store the data, and a buffer memory that uses the second command data supplied from the host control circuit, through the buffer memory manager. A data processing device comprising a data input / output operation and a programmable control circuit for controlling a data storage operation. A data processing method used, wherein the step of managing the buffer memory by dividing the buffer memory into a plurality of storage areas; the step of storing the data in a first storage area of the plurality of storage areas; Downloading second instruction data from a device and storing the second instruction data in a second storage area, wherein the programmable control circuit reads the second instruction data from the second area Step, based on the second command data, the programmable control circuit, via the buffer memory manager,
Controlling a data input / output operation of the buffer memory and a data storage operation.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG.
This will be described with reference to FIG.

FIG. 1 is a block diagram of a system employing the data processing apparatus of the present invention.

In FIG. 1, 1 is Y / C (luminance signal /
A composite video signal S
_vi is entered. This Y / C (luminance signal / color signal)
The separation circuit 1 separates an analog luminance signal and a video signal from the composite video signal S _vi and transfers them to a subsequent stage.

A video AD (analog-to-digital) converter 2 is connected to a stage subsequent to the Y / C (luminance signal / color signal) separation circuit 1. This video AD converter 2
, A luminance signal and a video signal are transferred, and the video A
The D converter 2 transfers these to the subsequent stage as digitized video data.

The DVD is provided at the subsequent stage of the video AD converter 2.
(Digital versatile disk) The stream encoder 3 is connected.

In FIG. 1, reference numeral 4 denotes an audio AD converter. The audio AD converter 4 receives analog audio signals S _ALI and S _ARI. The audio signals S _ALI and S _ARI are digitized and then converted as audio data to an audio encoder 5 connected to a subsequent stage. Will be transferred.

In the audio encoder 5,
The audio data is processed to adjust the data length so that it becomes audio sample data specified by the DVD video recording format, and one sample data is linear PCM (pulse code modulation) data in units of 16 bits, 20 bits or 24 bits. DVD stream encoder 3
Transfer to

In the DVD stream encoder 3, the transferred video data and audio data are
Once buffered in the buffer memory 6, encoding processing is performed on a video pack and an audio pack each having a code amount of 2048 bytes in a DVD stream specified by the DVD video recording format.

Also, the DVD stream encoder 3
Data for synchronous playback of the recorded video data and the recording time, display control data, and copy protection data are also encoded as an RDI (Real Time Data information) pack.

In the DVD stream encoder 3,
A video pack packed by encoding,
The audio pack and the RDI pack are transferred to the encoder interface 7 connected to the subsequent stage of the DVD stream encoder 3.

The encoder interface 7 transfers the transferred video pack, audio pack and RDI pack to a block connected at a later stage at an appropriate timing.

In the subsequent stage of the encoder interface 7, a buffer memory manager 9,
Stream output interface 10, IDE
(Integrated Data Information) Each block of the interface controller 11 is connected, and between each block, a video pack, an audio pack, or an RDI pack is transferred via a data bus.

A buffer memory 10 is connected to the buffer memory manager 9 connected to the data bus, and video packs, audio packs, and RDI packs transferred via the data bus are temporarily stored in the buffer memory 10. Buffering is performed, and input / output from / to the buffer memory 10 is controlled by the control of the buffer memory manager 9.

Further, the buffer memory manager 9
The programmable controller 8, the IDE interface controller 12, and each block of the stream output interface 11 are connected to each other via a data bus.

Further, a DVD audio / video decoder 15 is connected downstream of the stream output interface 11.

In particular, the buffer memory manager 9
And the IDE interface controller 12 are connected to the data buses 28, 29, and 35, and enable data transfer therebetween.

The data bus 28 is connected to a primary IDE port inside the IDE interface controller 12, and the data bus 29 is connected to the primary IDE port.
Connected to port.

Further, IDE is set to the primary IDE port.
The hard disk drive 30 is connected via a bus 26, and the secondary IDE port is connected to a DVD-RAM drive 31 via an IDE bus 27.

The primary IDE port and the hard disk drive 30 can mutually transfer data via the IDE bus 26.
Data can be transferred to and from the D-RAM drive 31 via the IDE bus 27.

The IDE interface controller 12 is provided with a sub-IDE port 34, which is connected to the sub-IDE port 34 via a sub-IDE bus 36.
The EE1394 IDE bridge 37 is connected.
A cable 38 is connected to the IEEE 1394 IDE bridge 37, and an external input interface connector 39 is provided at a distal end of the cable 38.

The buffer memory manager 9 transfers data such as video packs, audio packs, and RDI packs buffered in the buffer memory to the hard disk drive 30 or the DVD-RAM drive 31 via the IDE interface controller 12. Can be.

When the buffer memory manager 9 transfers data, a video pack, an audio pack, and an RDI pack can be recorded on the recording medium of the hard disk drive 30 or the DVD-RAM drive 31.

Further, the hard disk drive 30
A video pack on a recording medium of the VD-RAM drive 31,
When recording audio packs and RDI packs,
From the VD-RAM drive 31 to the recording medium of the hard disk drive 30, a video pack, an audio pack,
Also in the case of recording the DI pack, the buffer memory manager 9 transfers the data so that the data is buffered in the buffer memory 10, so that the data can be mutually recorded between the hard disk drive 30 and the DVD-RAM drive 31. .

When reproducing data read from a recording medium of the hard disk drive 30 or the DVD-RAM drive 31, a copy control code stored in a predetermined field in the RDI pack indicates that copying is permitted. Then, the hard disk drive 30
Alternatively, data can be transferred from the DVD-RAM drive 31 and the buffer memory manager 9 can transfer the data to the stream output interface 11 after buffering the data in the buffer memory 10.

At the subsequent stage of the stream output interface 11, a video pack, an audio pack, an RD
DV for decoding I-pack and extracting and reproducing video data, audio data, and control data as reproduction data
A D audio video decoder 15 is connected.

The video data is MPEG (Motion)
This is video data compressed by the Picture Expert Group (Picture Expert Group) method, and the DVD audio video decoder 15 expands the compressed video data.

A buffer memory 16 is connected to the DVD audio / video decoder 15. The DVD audio / video decoder 15 decodes a video pack, an audio pack, and an RDI pack while buffering data in the buffer memory 16.

The video data and audio data extracted by the DVD audio video decoder 15 are
The data is transferred to the video encoder 18 or the audio DA decoder 17 connected to the subsequent stage of the DVD audio / video decoder 15.

The audio DA decoder 17 converts audio data into S _ALO and S _ARO into analog audio signals, and outputs them from an audio output terminal.

The video encoder 18 converts the video data into an analog video signal, performs processing such as adding a synchronization signal, and outputs a synchronization signal S _Y , a color signal S _C , and a composite video signal S _NTSC from a video signal output terminal. I do.

On the other hand, the control data extracted from the RDI pack is transferred to the host MPU 19 via the host MPU bus 22 to which the host MPU 19 is connected.

The control data transferred to the host MPU 19 is transferred to the system RAM 20 via the host MPU bus 22.
And buffered in the system RAM 20.

The host MPU 19 has a host MP
The system ROM 21 is connected via the U bus 22, and the host MPU 19 fetches the instructions of the control program from the system ROM 21.

A button input / display control circuit 25 is connected to the host MPU 19. The button input / display control circuit 25 includes an operation button 2 as a user interface.
3 and a display 24 for displaying the state of the system.

The host MPU 19 includes the DVD A / V trim encoder 3, the IEEE 1394 IDE bridge 37, and the IDE interface controller 12.
And each block of the DVD audio / video decoder 15 via a host MPU bus 22.

The host MPU 19 has a system ROM 21
The operation by the control data corresponding to the control data of the RDI pack and the user operation input via the button input / display control circuit 25 by the control program stored in the
This is realized by controlling each block connected to the host MPU bus 22.

In the present invention, the buffer memory manager 9 exchanges data such as video packs, audio packs, and RDI packs stored in the buffer memory 10 with the hard disk drive 30 or the DVD-RAM drive 31 via the IDE interface controller 12. Can be forwarded to

The management of the full / empty state of the buffer memory 10 during the transfer operation is performed by a command output from the programmable controller 8.

This command is generated by the programmable controller, which is a programmable controller, based on the descriptor storing the control data issued by the host MPU 19, which is the host controller.

In the present invention, the buffer memory manager 9 manages the buffer memory 10 by dividing it into a plurality of storage areas in advance, and downloads the descriptor issued by the host MPU 19 via the host MPU bus 22 and Is stored in one of the plurality of storage areas in the buffer memory 10.

Here, the control operation of the buffer memory 10 by the buffer memory manager 9 will be described with reference to FIG.

FIG. 2 shows the buffer memory manager 9.
Is an allocation map of the buffer memory 10 that is divided and managed.

As described above, the buffer memory manager 9 manages the storage area of the buffer memory 10 in the plurality of storage areas 104 to 107 and 119. Specifically, each area is divided and managed by setting a boundary address Vad in a boundary value register set in the buffer memory 10.

In other words, by setting the boundary address in the boundary register in this way, each storage area of the buffer memory has an independent FIFO (Fast Input Fast) having a storage area whose upper limit is the boundary address Vad.
It functions as an (Output) type memory.

Next, each of the plurality of storage areas divided in the buffer memory 10 will be described.

The storage areas 104, 105, and 106 are allocated as areas for temporarily storing video packs, audio packs, and RDI packs, which are video data for reproduction.

The microcode storage area 107 is allocated as an area for storing microcode for controlling the programmable controller 8 at the time of initialization processing at the time of power-on.

Reference numeral 119 is allocated as a descriptor storage area for storing a descriptor downloaded from the host MPU 19.

In the descriptor storage area 119, as shown in FIG. 2, 1 to m descriptors are stored over the entire area of the descriptor storage area with the upper limit of the boundary address.

Here, FIGS. 3 to 6 are used to describe in detail the data structure and function of the descriptor.

FIG. 3 is a diagram showing the data structure of the descriptor. FIG. 4 is a first descriptor function table showing the function of each record constituting the descriptor.
Is a second descriptor function table, and FIG. 6 is a third descriptor function table.

FIG. 3 shows the structure of one descriptor. As shown in FIG. 3, the descriptor has a data amount of 16 bytes, and is composed of 16 records of 1 byte per record.

In FIG. 3, the vertical column indicates the byte number of each record allocated in the descriptor in the sequential organization, and the horizontal line indicates the leftmost bit as the MSB (Most).
Significant Bit), and the rightmost bit is LSB (Lowest Significant B).
It shows the bits of each record set as (it).

The following briefly describes each record of the descriptor. (1) The record allocated to the 0th byte in the descriptor is an Allocate_FIFO that performs allocation processing on each area of the buffer memory 10. (2) The record allocated to the first byte in the descriptor is enabled by designating an arbitrary area divided and managed in the buffer memory 10 and enabling it.
ve_FIFO. (3) The record assigned to the second byte in the descriptor is an Update_FIFO for rewriting and updating data by designating an arbitrary area divided and managed in the buffer memory 10. (4) The third record in the descriptor is a FIFO indicating the type of data stored in the buffer memory 10.
_Data_Type. (5) The record allocated to the fourth byte in the descriptor is F that sets the size of the storage area 104.
IFO0_SIZE. (6) The record allocated to the fifth byte in the descriptor is the F that sets the size of the storage area 105.
IFO1_SIZE. (7) The record allocated to the sixth byte in the descriptor is F that sets the size of the storage area 106.
IFO2_SIZE. (8) The record assigned to the seventh byte in the descriptor is a null record with each bit set to “00h”. (H indicates that the hexadecimal system is used.) (9) The record assigned to the eighth byte in the descriptor is a FIF that specifies the transfer mode of data written or read to / from the storage area 104.
O0_Connection_Mode. (10) The record assigned to the ninth byte in the descriptor is a FIFO0_Connection_Port that specifies a transfer port for writing or reading data to or from the storage area 104. In this record, the upper 4 bits are FIFO0_WR_Port that specifies data writing, and the lower 4 bits are
Bit is FIFO0_RD that specifies data reading
_Port. (11) The record allocated to the 10th byte in the descriptor is an F that specifies the transfer mode of data written or read to / from the storage area 105.
IFO1_Connection_Mode. (12) The record assigned to the eleventh byte in the descriptor is a FIFO1_Connection_Port that specifies a transfer port for writing or reading data to or from the storage area 105. In this record, the upper 4 bits are FIFO1_WR_Port that specifies data writing, and the lower 4 bits are
Bit is FIFO1_RD that specifies data reading
_Port. (13) The record allocated to the twelfth byte in the descriptor is an F that specifies the transfer mode of the data written to or read from the storage area 107.
IFO2_Connection_Mode. (14) The record assigned to the 13th byte in the descriptor is a FIFO2_Connection_Port that specifies a transfer port for writing or reading data to or from the storage area 107. In this record, the upper 4 bits are FIFO2_WR_Port that specifies data writing, and the lower 4 bits are
The bit is FIFO2_RD that specifies data reading.
_Port. (15) The record assigned to the 14th byte in the descriptor is a null record with each bit set to “00h”. (H indicates hexadecimal notation.) (16) The record allocated to the fifteenth byte in the descriptor is a record indicating the presence / absence of a descriptor executed following the descriptor to which this record belongs.

The specific descriptions and functions of these records are shown in FIGS. Byte = 0, <Allocate_FIFO> bit7-bit3: Reserved (“0” is assigned to all bits.) Bit2: Assigns the storage area 106 by DEF2 = “1”. bit1: DEF1 = "1" instructs the allocation of the storage area 105. bit0: DEF0 = "1" instructs the allocation of the storage area 104.

For example, if the value of this record is “0000”
0100 ", the storage area 106 is designated,
It is defined that no designation is made for the other storage areas 104 and 105. Byte = 1, <Active_FIFO> bit7-bit3: Reserved (“0” is assigned to all bits.) Bit2: The storage area 106 is enabled by AF2 = “1”. bit1: AF1 = "1" enables the storage area 105. bit0: The storage area 104 is enabled when AF0 = "1".

For example, if the value of this record is “0000”
0100 ", it is defined that only the storage area 106 is enabled and the other storage areas 104 and 105 are disabled. Byte = 2, <Update_FIFO> bit7-bit3: Reserved (all bits have" 0 ") Bit2: UF2 = “1” enables the storage area 106 to be updated bit1: UF1 = “1” enables the storage area 105 to be updated bit0: UF0 = “1” and the storage area 104 can be updated.

For example, if the value of this record is “0000”
0100 ", it is defined that only the storage area 106 can be updated and the other storage areas 104 and 105 cannot be updated. Byte = 3, <FIFO_Data_Type> bit7-bit3: Reserved (all bits are" 0 ") Bit2: TYP2 = “1” / “0” and storage area 106
Shows the type of data stored in. bit1: storage area 10 with TYP1 = "1" / "0"
5 shows the type of data stored. bit0: TYP0 = “1” / “0” and storage area 10
4 shows the type of data stored.

In the bit description, "1" indicates a DVD stream and "0" indicates a CD stream.

For example, if the value of this record is “0000”
0100 ", the storage area 106 has a DVD
The stream is stored, and the other storage areas 104 and 105 are stored.
Defines storing a CD stream. Byte = 4, <FIFO0_SIZE> The size of the storage area 104 is set in units of 16 Kbytes.

For example, if the value of this record is “0000”
0100 ", the size of the storage area 104 is defined as 4h × 16 = 64K bytes (h
Means that the data is hexadecimal. Byte = 5, <FIFO1_SIZE> The size of the storage area 105 is set in units of 16 Kbytes.

For example, if the value of this record is “0000”
0100 ", the size of the storage area 105 is defined as 4h × 16 = 64K bytes (h
Means that the data is hexadecimal. Byte = 6, <FIFO2_SIZE> The size of the storage area 106 is set in units of 16 Kbytes.

For example, if the value of this record is “0000”
0100 ", the size of the storage area 106 is defined as 4h × 16 = 64K bytes (h
Means that the data is hexadecimal. Byte = 7, <Reserve> Since this record is a null record, the description is omitted. Byte = 8, <FIFO0_Connection_
Mode> As shown in FIG. 5, Write to FIFO0
Stream (number of write streams): Read S
stream (the number of read streams). F0CM1 = "0", FOCM0 = "0": Inact
Indicates that the transfer is invalid. F0CM1 = "0", FOCM0 = "1": Indicates that the number of write streams is 1 and the number of read streams is 1. F0CM1 = "1", FOCM0 = "0": Indicates that the number of write streams is 1 and the number of read streams is 2. F0CM1 = "1", FOCM0 = "1": Indicates that the number of write streams is 1 and the number of read streams is 3. Byte = 9, <FIFO2_Connection_
Port> As shown in FIG. 6, input ports INP0 to INP3 and output port OP0 provided for buffer memory 10 are provided.
By setting a flag for ~ OP3, the storage area 104 in the buffer memory, the encoder interface 7 connected via the buffer memory manager 9, the IDE interface controller 12 (primary IDE port), and the IDE interface controller 12 ( Secondary IDE port), input ports INP0 to INP3, and output port O in each interface of stream output interface 11.
It controls whether data transfer is possible in P0 to OP3.

INP0, OP0: enable / disable of the input port INP0 or the output port OP0 for the encoder interface 7.

INP1, OP1: Input port INP1 or output port OP1 for IDE interface controller 12 (primary IDE port)
Are enabled / disabled.

INP2, OP2: Input port INP2 or output port OP3 for IDE interface controller 12 (primary IDE port)
5 shows an enable enable / disable of the first embodiment.

INP3, OP3: Input ports IN for the stream output interface 11
Enable enable of P3 or output port OP3 /
Indicates disable. Byte = 10, <FIFO1_Connection
_Mode> As shown in FIG. 5, Write to FIFO0
Stream (number of write streams): Read S
stream (the number of read streams).

F0CM1 = 0, FOCM0 = 0: Ina
Indicates active transfer (transfer invalid).

F0CM1 = 0, FOCM0 = 1: Indicates that the number of write streams is 1 and the number of read streams is 1.

F0CM1 = 1, FOCM0 = 0: Indicates that the number of write streams is 1 and the number of read streams is 2.

F0CM1 = 1, FOCM0 = 1: Indicates that the number of write streams is 1 and the number of read streams is 3. Byte = 11, <FIFO1_Connection
_Port> As shown in FIG. 6, input ports INP0 to INP3 and output port OP0 provided for buffer memory 10 are provided.
By setting flags for OP3 to OP3, the storage area 105 in the buffer memory, the encoder interface 7, the IDE interface controller 12 (primary IDE port) connected via the buffer memory manager 9, and the IDE interface controller 12 ( Secondary IDE port), input ports INP0 to INP3, and output port O in each interface of stream output interface 11.
It controls whether data transfer is possible in P0 to OP3.

INP0, OP0: enable / disable of the input port INP0 or the output port OP0 for the encoder interface 7. INP1, OP1: enable / disable of the input port INP1 or the output port OP1 to the IDE interface controller 12 (primary IDE port).

INP2, OP2: Input port INP2 or output port OP3 for IDE interface controller 12 (primary IDE port)
5 shows an enable enable / disable of the first embodiment.

INP3, OP3: Input ports IN for the stream output interface 11
Enable enable of P3 or output port OP3 /
Indicates disable. Byte = 12, <FIFO1_Connection
_Mode> As shown in FIG. 5, Write for FIFO1
Stream (number of write streams): Read S
stream (the number of read streams).

F1CM1 = 0, F1CM0 = 0: Ina
Indicates active transfer (transfer invalid).

F1CM1 = 0, F1CM0 = 1: Indicates that the number of write streams is 1 and the number of read streams is 1.

F1CM1 = 1, F1CM0 = 0: Indicates that the number of write streams is 1 and the number of read streams is 2.

F1CM1 = 1, F1CM0 = 1: Indicates that the number of write streams is 1 and the number of read streams is 3. Byte = 13, <FIFO2_Connection
_Port> As shown in FIG. 6, input ports INP0 to INP3 and output port OP0 provided for buffer memory 10 are provided.
By setting flags for OP3 to OP3, the storage area 105 in the buffer memory, the encoder interface 7, the IDE interface controller 12 (primary IDE port) connected via the buffer memory manager 9, and the IDE interface controller 12 ( Secondary IDE port), input ports INP0 to INP3, and output port O in each interface of stream output interface 11.
It controls whether data transfer is possible in P0 to OP3.

INP0, OP0: Indicates enable / disable of the input port INP0 or the output port OP0 for the encoder interface 7. INP1, OP1: enable / disable of the input port INP1 or the output port OP1 to the IDE interface controller 12 (primary IDE port).

INP2, OP2: Input port INP2 or output port OP3 for IDE interface controller 12 (primary IDE port)
5 shows an enable enable / disable of the first embodiment. INP3, OP3: Indicates enable / disable of the input port INP3 or the output port OP3 for the stream output interface 11. Byte = 14, <Reserve> Since this record is a null record, the description is omitted. Byte = 15, <NEXT> NEXT = 01h: Indicates that the descriptor specified by the host MPU 19 is stored immediately after the area in the buffer memory 10 where the main descriptor is stored.

NEXT = 01h: indicates that the next descriptor specified by the host MPU 19 is stored immediately after the area in the buffer memory 10 where this descriptor is stored.

NEXT = 00h: This descriptor is
It indicates whether the descriptor is the last one of the consecutively executed descriptors specified by the host MPU 19, or whether only this descriptor is to be executed.

These descriptors correspond to the host MPU
The host MPU is generated in the descriptor storage area 119 generated by the server 19 or stored in the system ROM and divided and managed in the buffer memory 10 as necessary.
19 through the host MPU bus 22.

Next, FIG. 7 will be used to describe the operation of the data processing device of the present invention using this descriptor.

FIG. 7 is a diagram showing an example of a change in the operating state of a system using the data processing device of the present invention.

FIGS. 7 (a) and 7 (b) show the state of the system in which the data processing apparatus of the present invention is used, respectively. .

The DVD A / V stream encoder 3, hard disk drive 30, DVD-R in the figure
AM drive 31, DVD audio / video decoder 1
5 is the same as the block shown in FIG.

The storage areas 104 and 105 are the same as the blocks shown in FIG.

However, originally, as shown in FIG. 1, the storage areas 104 and 105 of the buffer memory 10 and other DVDs
The A / V stream encoder 3, the hard disk drive 30, the DVD-RAM drive 31, and the DVD audio / video decoder 15 are connected with a plurality of circuit blocks such as the buffer memory manager 9 interposed therebetween.

In particular, the IDE interface controller 12 is interposed between the hard disk drive 30 and the buffer memory 10, and between the DVD-RAM drive 31 and the buffer memory 10.

That is, data transfer between the hard disk drive 30 and the buffer memory 10 and data transfer between the DVD-RAM drive 31 and the buffer memory 10 are performed via the IDE interface controller 12.

However, in FIG. 7, the storage areas 104 and 105, the other DVD A / V stream encoder 3, the hard disk drive 30, and the DVD-RA
M drive 31, DVD audio / video decoder 15
Blocks intervening between are omitted.

First, when the power supply of the system is turned on, the host MPU downloads the descriptor stored in the internal memory to the descriptor storage area 119 which is divided and managed in the buffer memory 10 via the host MPU bus 22.

At this time, the host MPU 19 prepares to transfer a descriptor, which is control data for controlling the operation of the buffer memory 10, to the buffer memory controller 9.

The host MPU 19 also transfers data indicating that the descriptor is ready to be transferred to the programmable controller 8 for controlling the operation of the buffer memory controller 9.

The programmable controller 8 having received the data transfer issues and transfers a command to the buffer memory controller 9 to store the descriptor in the descriptor storage area 119 of the buffer memory 10.

At this time, the buffer memory controller 9 receiving this command receives the transfer of status data from the buffer memory 10 for checking the free area of the descriptor storage area of the buffer memory 10, and sends the status data to the descriptor storage area of the buffer memory 10. It is determined whether or not the descriptor can be written in the empty area.

The buffer memory controller 9 sends a signal to the programmable controller 8 based on the result.
It transfers data indicating whether it is possible to receive the transfer of the descriptor from the host MPU 19.

Upon receiving the data transfer, the programmable controller 8 notifies the host MPU of data indicating that the descriptor can be transferred.

The host MPU 1 receiving this data notification
9 is a descriptor via the host MPU bus 22;
Transfer to the buffer memory manager 9.

The buffer memory manager 9 having received the transfer of the descriptor from the host MPU 19 transfers the descriptor to the buffer memory 10.

At this time, the buffer memory manager 9
Addressing the descriptor storage area 119 and transferring the descriptor to the buffer memory 10.

The buffer memory 10 receiving the transfer of the descriptor starts storing the transferred descriptor in the addressed descriptor storage area 119.

The descriptor stores the data of the descriptor until data is written to the storage element stored in the boundary value address register and addressed by the boundary address Vad.

Here, as long as there is an empty area in the descriptor storage area 119 of the buffer memory 10 and the writing of the descriptor is possible, the buffer memory 10 can receive the transfer of the descriptor from the host MPU 19 to the programmable controller. Continue to transfer data indicating whether or not it is possible.

Receiving this data, the programmable controller 8 continues to notify the host MPU of data indicating that the descriptor can be transferred, as described above.

The host MPU 19 receiving this data continues transferring the descriptor to the memory manager 9.

Then, the buffer memory manager 9 receiving the transfer of the descriptor from the host MPU 19
Keeps transferring the descriptor to the buffer memory 10.

Further, the buffer memory 10 which has received the descriptor transfer stores the descriptor transferred to the descriptor storage area 119 in the boundary address V.
This continues until data is written to the storage element addressed by adi.

When the descriptor data is written to the storage element addressed by the boundary address Vadi, the buffer memory 10 stores the descriptor storage area 11
The data indicating that the descriptor is stored in the storage area 9 in a full state is transferred to the buffer memory manager 9.

The buffer memory manager 9 that has received the data transfer similarly transfers data indicating that the transfer of the descriptor to the buffer memory manager 9 should be stopped to the host MPU.

The host MPU 1 receiving this data transfer
9 stops the transfer of the descriptor to the buffer memory manager 9.

The host MPU 19 transfers data to the effect that the transfer of the descriptor has been stopped to the programmable controller 8.

The programmable controller 8 having received the data transfer starts controlling the memory manager 9 by the descriptor stored in the descriptor storage area 119 of the buffer memory 10.

That is, the programmable controller 8
The host M controls the data input / output operation and the data storage operation of the buffer memory 10 via the buffer memory manager 9.
It can be controlled independently of the PU 19.

First, the programmable controller 8
A command is transferred to the memory manager 9 so as to transfer the descriptor stored in the descriptor storage area 119 of the buffer memory 10 to the programmable controller 8.

The memory manager 9 having received the transfer of the instruction data reads out the descriptor stored in the descriptor storage area 119 and transfers it to the programmable controller 8.

The programmable controller 8 having received the transfer of the descriptor stored in the descriptor storage area 119 transmits a command for controlling the memory manager 9 based on the description of the descriptor in order to control the buffer memory 10. Transfer to 9

The memory manager 9 having received the command controls the data input / output operation and the data storage operation of the buffer memory 10 based on the command.

Here, an example of a control operation for the buffer memory 10 of the data processing device of the present invention will be described with reference to FIGS. 7 (a) and 7 (b).

FIG. 7A illustrates a data input / output operation and a data storage operation for the storage area 104 shown in FIG.

The descriptor includes 16 records as described with reference to FIG. 2, but here, for simplicity of description, the FIFO in the descriptor is used.
The operation based on O0_Connection_Port will be described.

The programmable controller 8 reads the record of the descriptor, issues a command based on the read record, and sends it to the buffer memory manager 9.
Forward to

Of these descriptors, FIFO0_
As shown in FIG. 7, the record to which the Connection_Port is assigned has the output port OP0 =
0, a flag of the input port INP0 = 1 is described.

Therefore, based on this description, the programmable controller 8 controls the buffer memory manager 9 so that the DVD A / V stream data from the DVD A / V stream encoder 3 is written from the storage area 104 in the buffer memory 10. Transfer command to control.

At this time, in the buffer memory 10, the FIFO0 write address generator 110 shown in FIG. 7 operates to sequentially address the storage elements in the free area of the storage area 104 and to record them in the hard disk drive 30. DVD A / V stream data is sequentially written.

Thus, the storage area 104 has the DV
DA / V stream data is written.

Similarly, FIFO0_Connect
In the record to which the “ion_Port” is assigned, FIG.
As shown in the figure, flags of output port OP1 = 1 and input port INP1 = 0 are described.

Therefore, based on this description, the programmable controller 8 reads data from the storage area 104 in the buffer memory 10
A command for controlling the buffer memory manager 9 is transferred so that the VDA / V stream data is read.

At this time, in the buffer memory 10, the FIFO0 read address generator a 107 a shown in FIG. 7 operates to sequentially address the storage elements in the storage area 104 in which data has already been stored, and perform DVD A / A The V stream data is read and transferred to the hard disk drive 30.

Similarly, FIFO0_Connect
In the record to which the “ion_Port” is assigned, FIG.
As shown in the figure, the flags of the output port OP2 = 1 and the input port INP2 = 0 are described.

Therefore, based on this description, the programmable controller 8 reads the D-ROM from the storage area 104 in the buffer memory 10 to the DVD-RAM drive 31.
A command for controlling the buffer memory manager 9 is transferred so that the VDA / V stream data is read.

At this time, in the buffer memory 10, the FIFO0 read address generator b107b shown in FIG. 6 operates to sequentially address the storage elements in the storage area 104 in which data has already been stored, and to perform DVD A / A The V stream data is sequentially read and transferred to the DVD-RAM drive 30.

Similarly, FIFO0_Connect
In the record to which the “ion_Port” is assigned, FIG.
As shown in the figure, the flags of the output port OP3 = 0 and the input port INP3 = 0 are described.

This description describes the output port OP3 and the input port INP3 of the stream output interface 11 connected to the DVD audio video decoder 15.
Since both are disabled, the programmable controller 8 transfers a command not to perform an input / output operation to the storage area 104 in the buffer memory 10 according to this description.

At this time, the storage area 104 in the buffer memory 10 and the DVD audio / video decoder 1
No data transfer is performed between the device and the device.

Next, a case where the system changes from the state shown in FIG. 7A to the state shown in FIG. 7B will be described.

FIG. 7B shows the storage area 104 shown in FIG.
2 illustrates a data input / output operation and a data storage operation with respect to the storage area 105.

The system is switched from the state shown in FIG.
When the state changes to the state shown in FIG. 7B, the program controller 8 executes the next descriptor following the descriptor executed in FIG.

Here, the storage area to be controlled is 10
4 and 105, the FIFO0_Connection_Port in this descriptor
And the operation based on FIFO1_Connection_Port will be described.

[0149] Among the descriptors, FIFO0_Co
As shown in FIG. 7, the record to which the nection_Port is assigned includes output ports OP0 = 0,
The flag of the input port INP0 = 1 is described.

Therefore, based on the description, the programmable controller 8 controls the buffer memory manager 9 so that the DVD A / V stream data is written from the DVD A / V stream encoder to the storage area 104 in the buffer memory 10. Transfer command to control.

At this time, in the buffer memory 10, the FIFO0 write address generator 110 shown in FIG. 7 operates to sequentially address the storage elements in the empty area of the storage area 104 to store the DVD A / V stream data. Write sequentially.

In this manner, the operation of storing the DVD A / V stream data in the storage area 104 is controlled.

[0153] Of the descriptors, the FIF
As shown in FIG. 7, the output port O is assigned to the record to which O1_Connection_Port is assigned.
A flag of P0 = 0 and input port INP1 = 1 is described.

Therefore, based on the description, the programmable controller 8 controls the buffer memory manager 9 so that the DVD A / V stream data read from the hard disk drive 30 is written into the storage area 105 in the buffer memory 10. Transfer the command to be controlled.

At this time, in the buffer memory 10, the FIFO1 write address generator 111 shown in FIG. 7 operates to sequentially address the storage elements in the free area of the storage area 105 to store the DVD A / V stream data. Writing is performed sequentially.

In this way, the operation of storing the DVD A / V stream data in the storage area 105 is controlled.

Similarly, FIFO1_Connect
In the record to which the “ion_Port” is assigned, FIG.
As shown in the figure, the flags of the output port OP2 = 0 and the input port INP2 = 0 are described.

This description is based on the DVD-RAM drive 31
Are disabled, the programmable controller 8 does not perform an input / output operation on the storage area 105 in the buffer memory 10 based on this description. Is transmitted.

Therefore, at this time, no data is transferred between the storage area 105 in the buffer memory 10 and the DVD-RAM drive 31.

Similarly, FIFO1_Connect
In the record to which the “ion_Port” is assigned, FIG.
As shown in the figure, the flags of the output port OP3 = 1 and the input port INP3 = 0 are described.

Therefore, according to this description, the programmable controller 8 operates in the storage area 10 in the buffer memory 10.
5 to the stream output interface 11 connected to the DVD audio / video decoder 15, the command data for controlling the buffer memory manager 9 so that the DVD A / V stream data as the reproduction data is read out. I do.

At this time, in the buffer memory 10, the FIF1 read address generator 108 shown in FIG. 7 operates to sequentially address the storage elements in the storage area 105 in which the data has already been stored, and reproduce the data for reproduction. DVD A / V stream data is sequentially read and transferred to the DVD audio / video decoder 15 through the stream output interface 11.

As described above, according to the present invention, the host MPU 19
, The descriptor is downloaded to the descriptor storage area of the buffer memory 10, and the programmable controller 8 controls the data input / output operation and the data storage operation of the buffer memory 10 via the buffer memory manager 9 so that the buffer memory 10 Is performed independently of the host MPU 19.

That is, the programmable controller 8 controls the data input / output operation and the data storage operation in the buffer memory 10 which is a part of the system control by the descriptor given by the host MPU 19, thereby controlling the entire system. The overhead of the host MPU 19 is reduced.

Further, since the programmable controller 8 is in charge of controlling the buffer memory 10, the host MPU 19 can control the DVD A / V stream encoder 3 based on different control data different from the descriptor.
And the DVD audio / video decoder 15 can be controlled.

Therefore, the host MPU 19 controls the DVD audio / video decoder 15, and the programmable controller 8 controls the data input / output operation and the data storage operation of the buffer memory 10, and these parallel controls are performed on the system. Will be done.

Further, by this parallel processing, the host MP
The DVDA / V stream encoder 3 controlled by U19 can perform MPEG video compression video data encoding processing, and the DVD audio video decoder 15 can perform video data and MPEG video compression video data decoding processing in real time. In addition, the continuity of data recording / reproduction required for digital video reproduction and recording is maintained, and good data recording and reproduction without discontinuity of an image displayed on a monitor can be performed.

[0168]

As described above, according to the present invention, it is possible to provide a data processing apparatus and a data processing method capable of reducing the overhead of the host-side device and capable of recording and reproducing good data.

[Brief description of the drawings]

FIG. 1 is a block diagram of a system employing a data processing device of the present invention.

FIG. 2 is an allocation map of a buffer memory 10;

FIG. 3 is a data structure diagram of a descriptor.

FIG. 4 is a first descriptor function table.

FIG. 5 is a second descriptor function table.

FIG. 6 is a third descriptor function table.

FIG. 7 is a diagram showing an example of a change in an operation state of a system using the data processing apparatus.

[Explanation of symbols]

 19 Host MPU 10 Buffer memory 9 Buffer memory manager 8 Programmable controller 104-105 Storage area 119 Descriptor storage area

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference) GK12 HL11

Claims (8)

[Claims] 1. A first circuit block, a second circuit block, a bus for transferring data between the first circuit block and the second circuit block, and a bus for transferring data between the first circuit block and the second circuit block. A host control circuit that transfers first command data for controlling the operation of the second circuit block; a buffer memory that stores the data transferred through the bus; and a buffer memory that controls the buffer memory to store the data. And a programmable control circuit for controlling the data input / output operation and the data storage operation of the buffer memory through the buffer memory manager using the second command data supplied from the host control circuit. Wherein the buffer memory is divided into a plurality of storage areas and managed, and a first of the plurality of storage areas is provided. Storing the data in a storage area, downloading second instruction data from the host control device, storing the second instruction data in a second storage area, the programmable control circuit Reading instruction data from the second area;
A data processing device for controlling a data input / output operation and a data storage operation of the buffer memory via the buffer memory manager based on the second command data. 2. The data processing apparatus according to claim 1, wherein said data is video data. 3. The data is compressed video data, and one of the first circuit block and the second circuit block is a decoder for expanding the compressed video data. And The data processing device according to claim 1. 4. The host control circuit controls the first circuit block and the second block based on the first command data, and the programmable control circuit controls a data input / output operation of the buffer memory. 2. The method according to claim 1, wherein the data storage operations are independently controlled in parallel.
The data processing device according to claim 1. 5. A first circuit block, a second circuit block, a bus for transferring data between the first circuit block and the second circuit block, and a first bus through the bus. A host control circuit that transfers first command data for controlling operations of the circuit block and the second circuit block; a buffer memory that stores data transferred through the bus; And a programmable control for controlling a data input / output operation of the buffer memory and a data storage operation through the buffer memory manager using the second command data supplied from the host control circuit. A data processing method used in a data processing device comprising: a buffer memory; Managing the data by dividing the data into a plurality of storage areas; storing the data in a first storage area of the plurality of storage areas; downloading second command data from the host control device; A step of storing the second command data in a second storage area; a step of the programmable control circuit reading the second command data from the second area; and Controlling the data input / output operation and the data storage operation of the buffer memory via the buffer memory manager by the programmable control circuit. 6. The data processing method according to claim 5, wherein said data is video data. 7. The data is compressed video data, and one of the first circuit block and the second circuit block is a decoder for expanding the compressed video data. Claim 5
Data processing method described. 8. The host control circuit connects the first circuit block and the second circuit block based on the first command data, and the programmable control circuit controls data input / output of the buffer memory. 6. The data processing method according to claim 5, wherein the operation and the data storage operation are independently controlled in parallel.