JP2002369026A - Horizontal deflection circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that a conventional horizontal deflection circuit has caused an error due to dispersion in circuit components when adopting a configuration providing separate sawtooth wave signals to two drive pulse generating systems. SOLUTION: A ramp signal RAMP generated by a single ramp generator 31 is given in common to voltage comparators 21, 22 and voltage comparators 23, 24 in two drive pulse generating systems generating horizontal drive pulses HD1, HD2 respectively in a horizontal drive circuit that generates the horizontal drive pulses HD1, HD2. Further, the horizontal drive pulse HD1 is generated on the basis of a comparison result between a main phase control voltage VCONT1 and the ramp signal RAMP and an error signal VERR' is added to/subtracted from the main phase control voltage VCONT1 at adders 33, 34 and the horizontal drive pulse HD2 is generated on the basis of the result of comparison between arithmetic outputs V3, V4 of the adders 33, 34 and the ramp signal RAMP.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a horizontal deflection circuit for supplying a sawtooth current to a horizontal deflection coil of a cathode ray tube.

[0002]

2. Description of the Related Art In order to facilitate horizontal image size adjustment and distortion correction, two sets of parallel circuits each comprising a switching element, a damper diode and a resonance capacitor are provided, and these two sets of parallel circuits are connected in series. Then, power is supplied from the connection point through a flyback transformer, and a signal proportional to the deflection current flowing through the horizontal deflection coil is fed back to one switching element to control the deflection current flowing through the horizontal deflection coil. A deflection circuit has been proposed by the present applicant (see Japanese Patent Application Laid-Open No. H11-127364).

In this horizontal deflection circuit, a horizontal drive circuit for applying first and second horizontal drive pulses HD1 and HD2 to two switching elements (hereinafter, referred to as output transistors) is used. FIG. 5 shows a configuration of a horizontal drive circuit according to a conventional example.

[0004] The horizontal drive circuit is provided with four comparators 101 to 104. Comparator 10
A horizontal drive pulse HD is given to each of 1, 102 as a comparison input through two-stage inverters 105, 106 and a time constant circuit 107. The time constant circuit 107 includes a resistor R1 and a capacitor C1.
A horizontal drive pulse HD is given to each of the comparators 103 and 104 as a comparison input through a one-stage inverter 108 and a time constant circuit 109. Time constant circuit 10
9 comprises a resistor R2 and a capacitor C2.

The comparators 101 and 103 include:
As each reference input, a reference voltage generated by a reference voltage generation circuit 110 is applied via a buffer 111. The reference voltage generating circuit 110 includes resistors R3 and R4 connected in series between the power supply VCC and the ground, and generates a reference voltage determined at each connection point by each resistance ratio.

On the other hand, after the deflection current is rectified by the diode D, it is supplied as a feedback signal to the inverting (-) input terminal of the error amplifier 113 via the time constant circuit 112 including the resistor R5 and the capacitor C3. A non-inverting (+) input terminal of the error amplifier 113 is supplied with a parabolic waveform control signal for correcting pincushion distortion. The error signal output from the error amplifier 113 is passed through an integration circuit 114 to the comparators 102 and 1.
04 is given as each reference input.

The integrating circuit 114 includes an operational amplifier OP, a resistor R6 having one end connected to the inverting input terminal of the operational amplifier OP, and a capacitor C4 connected in parallel between the inverting input terminal and the output terminal of the operational amplifier OP. It is constituted by a resistor R7. The reference voltage generated by the reference voltage generation circuit 115 is applied to the non-inverting input terminal of the operational amplifier OP. The reference voltage generation circuit 115 includes resistors R8 and R9 connected in series between the power supply VCC and the ground, and generates a reference voltage determined at each connection point between the resistors R8 and R9.

The output of the comparator 101 has two NAs.
It becomes a set input of an RS flip-flop 116 composed of a combination of ND gates G1 and G2. The output of the comparator 102 becomes a set input of an RS flip-flop 117 composed of a combination of two NAND gates G3 and G4. The output of the comparator 103 is the reset input of the RS flip-flop 116. The output of the comparator 104 becomes the reset input of the RS flip-flop 117. Then, the output of the RS flip-flop 116 becomes the horizontal drive pulse HD1 and
The output of the S flip-flop 117 is derived as a horizontal drive pulse HD2.

FIG. 6 shows a horizontal drive pulse HD (a),
Comparison input (b) of comparators 101 and 102, comparison input (c) of comparators 103 and 104, horizontal drive pulse HD1 (d) and horizontal drive pulse HD2
(E) shows each waveform.

In the horizontal drive circuit having the above configuration, each timing of the horizontal drive pulses HD1 (d) and HD2 (e) is determined by the delay amount of the rising edge of the comparison input (b) of the comparators 101 and 102,
The delay amount of the rising edge of the comparison input (c) of the comparators 3 and 104, the reference input of the comparators 101 and 102 (hereinafter, referred to as threshold Vth1), and the comparators 103 and 104
(Hereinafter referred to as threshold Vth2).

That is, the horizontal drive pulse HD1
The rising timing of FIG.
The horizontal drive pulse HD2 is determined by the delay amount of the rising edge of the comparison input (b) 102 and the threshold value Vth1.
The rising timing of (e) is the comparator 103,
It is determined by the delay amount of the rising edge of the comparison input (c) 104 and the threshold value Vth2. Here, threshold Vth1 is given by a reference voltage generated by reference voltage generation circuit 110, and threshold Vth2 is given by a reference voltage generated by reference voltage generation circuit 115.

[0012]

As described above, in the conventional horizontal drive circuit, the comparator 101,
The time constant circuit 107 is used to determine the delay amount of the rising edge of the comparison input (b) of the comparator 102, and the comparators 103, 1
The time constant circuit 115 is used to determine the amount of delay in the rise of the comparison input (c) in FIG. 04, the reference voltage generation circuit 110 is used to determine the threshold Vth1, and the reference voltage generation circuit 115 is used to determine the threshold Vth2. Because
The resistance and capacitance values of these circuit components vary independently. This causes the following problem during mass production.

That is, the horizontal drive pulses HD1, HD1
The variation of the relative delay amount of No. 2 becomes large. In the system, since the relative delay amount determines the magnitude of the horizontal deflection current, the variation of the relative delay amount becomes the variation of the horizontal deflection current. Further, the relative variation in the delay amount of the rise of the comparison inputs (b) and (c) increases. In the system, this variation is caused by horizontal drive pulses HD1, HD2
, The drive condition of the output transistor changes, causing an increase in power consumption and a shortage of drive capability.

If the timing relationship between the horizontal drive pulse HD (a) and the horizontal drive pulse HD1 (d) is to be changed, the horizontal drive pulse HD1 (d),
Since the relative timing of HD2 (e) also changes, timing adjustment becomes very difficult. The same can be said for the case where the timing of the horizontal drive pulse HD2 (e) with respect to the horizontal drive pulse HD (a) is changed.

Further, horizontal drive pulses HD1, HD
Even if a limiter is added so that the relative delay amount of 2 does not change beyond a certain value, the horizontal drive pulses HD1, H
The limiter operates at the rise of D2, but there is a region where it does not operate at the fall,
There were problems such as difficulty in brushing up this system.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to reduce the variation in the duty of the horizontal drive pulses HD1, HD2 and to stably generate the horizontal drive pulses HD1, HD2. To provide a horizontal deflection circuit having a horizontal drive circuit.

[0017]

The horizontal deflection circuit according to the present invention has two sets of parallel circuits consisting of a switching element, a damper diode, and a resonance capacitor.
A pair of parallel circuits are connected in series, power is supplied from the connection point via a flyback transformer, and a signal proportional to the current flowing through the horizontal deflection coil is fed back to one switching element and deflection current flowing through the horizontal deflection coil A sawtooth wave generating means for generating a sawtooth wave signal in synchronization with the rising and falling timings of a reference horizontal drive signal, and a first horizontal driving circuit for driving the other switching element. First control voltage generating means for generating a first control voltage for determining the timing of rise / fall of the drive pulse; and the first control voltage based on a comparison result between the sawtooth wave signal and the first control voltage. A first drive pulse generating means for generating a horizontal drive pulse, and a second horizontal drive pulse for driving one of the switching elements. A second control voltage generating means for generating a second control voltage serving as a reference for deciding timing of rising / falling of a pulse based on a signal proportional to a current flowing through the horizontal deflection coil; Calculating means for adding and subtracting the first control voltage to and from the second drive pulse generating means for generating the second horizontal drive pulse based on a comparison result between the sawtooth wave signal and a calculation output of the calculating means. Means.

In the horizontal deflection circuit having the above configuration, first,
The sawtooth wave generating means applies the sawtooth wave signal generated in synchronization with the horizontal drive signal to the first and second drive pulse generating means in common, so that another sawtooth wave signal is individually given. This eliminates errors caused by variations in circuit components. Further, based on a comparison result between the first control voltage and the sawtooth wave signal, the first drive pulse generation means generates a first horizontal drive pulse, and the arithmetic means generates a first horizontal drive pulse with respect to the second control voltage. The first control voltage is added and subtracted, and the second drive pulse generating means generates the second horizontal drive pulse based on the result of the comparison between the operation output and the sawtooth signal. When the phase of the first horizontal drive pulse is adjusted by the control voltage, the phase of the second horizontal drive pulse also changes in conjunction with the adjustment. That is,
When the phase is adjusted by the first control voltage, the delay times of the two horizontal drive pulses automatically change to the same value.

[0019]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a circuit diagram showing a configuration example of a horizontal deflection circuit to which the present invention is applied. As is clear from FIG. 1, the horizontal deflection circuit to which the present invention is applied includes first and second parallel circuits 11 and 12, a flyback transformer 13, resonance capacitors C1 and C2, a horizontal deflection coil 15, an S-shaped correction. The configuration includes a capacitor 16 and a horizontal drive circuit 17. Further, the resonance capacitor 14 may be loaded according to the conditions at the time of design.

The first parallel circuit 11 has a configuration in which a switching element, for example, an output transistor Q1 comprising a bipolar transistor, a damper diode D1, and a resonance capacitor C1 are connected in parallel with each other.
Similarly, the second parallel circuit 12 has an output transistor Q2 composed of a bipolar transistor and a damper diode D
2 and the resonance capacitor C2 are connected in parallel with each other. These parallel circuits 11 and 12 are connected in series with each other.

The primary winding of the flyback transformer 13 is
It is connected between the connection point (node N1) of the parallel circuits 11 and 12 and the power supply. The resonance capacitor 14 includes a collector (node N2) between the collector of the output transistor Q1, the cathode of the damper diode D1, and one end of the resonance capacitor C1, the emitter of the output transistor Q2, the anode of the damper diode D2, and the resonance capacitor C2.
Is connected to a connection point (node N3) at one end.

One end of the horizontal deflection coil 15 is connected to the node N2. One end of the S-shaped correction capacitor 16 is connected to the other end of the horizontal deflection coil 15, and the other end is connected to the node N3. Node N3 is grounded. The horizontal drive circuit 17 is a circuit part which is a feature of the present invention.
Occurs. These horizontal drive pulses HD1, HD2
Is inverted by the inverters 18 and 19 and applied to the bases of the output transistors Q1 and Q2.

The horizontal deflection circuit having the above configuration has two sets of parallel circuits 11 and 12. These parallel circuits 11 and 12 are connected in series and a flyback transformer 13 is connected from the connection point N1.
, And a signal proportional to the deflection current flowing through the horizontal deflection coil 15 is fed back to the base of one of the output transistors Q2 as a feedback signal to control the deflection current flowing through the horizontal deflection coil 15. so,
Horizontal image size adjustment and distortion correction can be easily realized. Since this is not the gist of the present invention, a specific description thereof will be omitted here.

In the horizontal deflection circuit according to the above-described circuit example, an output transistor formed of a bipolar transistor is used as the switching element (Q1, Q2) of the first and second parallel circuits 11, 12, but the field effect is not changed. Of course, an output transistor composed of a transistor or an element having a function equivalent to these may be used.

Next, a specific configuration example of the horizontal drive circuit 17 will be described. FIG. 2 shows a horizontal drive circuit 17.
FIG. 3 is a block diagram showing an example of a specific configuration of FIG. Also,
FIG. 3 shows the timing relationship of the signals of each unit.

As shown in FIG. 2, the horizontal drive circuit 17 according to the present embodiment includes four voltage comparators 21 to 24, trigger control circuits 25 and 26 for two systems, flip-flops 27 and 28, and a driver. 29, 30, a ramp generator 31 as a sawtooth wave generating means, three adders 32-34, two control voltage generators 35, 36, a reference voltage source 37, an error amplifier 38, The phase shift amount limiter 39 is provided.

A horizontal drive signal (pulse signal) HD having a duty ratio of about 50% is input to the ramp generator 31. The ramp generator 31 is configured by a time constant circuit including, for example, a resistor and a capacitor, and generates a ramp signal RAMP that is a sawtooth wave in synchronization with the rise and fall of the horizontal drive pulse HD. Specifically, as is clear from the timing chart of FIG. 3, the ramp signal RAMP having a predetermined inclination angle is generated at each of the rising timing and the falling timing of the horizontal drive pulse HD.

The control voltage generator 35 is composed of, for example, a variable resistor connected between the reference voltage source 37 and the ground, and has a main phase control voltage (first control voltage) for determining an operating point of the entire system. Generate VCONT1. Similarly, the control voltage generator 36 is composed of, for example, a variable resistor connected between the reference voltage source 37 and the ground, and has a duty ratio adjustment voltage (third control voltage) for adjusting the duty ratio of the output pulse. Generate VCONT2.

The error amplifier 38 compares the above-described feedback signal, that is, a signal proportional to the current flowing through the horizontal deflection coil, with a control signal having a parabolic waveform for correcting pincushion distortion, and compares the error signal VERR. Output. This error signal (second control voltage) VERR
Is the rising of a horizontal drive pulse HD2 described later /
This is a reference for determining the fall timing. here,
The control signal performs position modulation on a time axis of a later-described horizontal drive pulse HD2 in order to obtain a target horizontal deflection current.

The adder 32 adds and subtracts the main phase control voltage VCONT1 generated by the control voltage generator 35 and the duty ratio adjustment voltage VCONT2 generated by the control voltage generator 36. The adder 33 has a main phase control voltage VCO
The addition and subtraction of NT1 and the error signal VERR 'of the error amplifier 38 supplied via the phase shift amount limiter 39 are performed. The adder 34 performs addition and subtraction between the main phase control voltage VCONT1, the duty ratio adjustment voltage VCONT2, and the error signal VERR '.

The ramp signal RAMP output from the ramp generator 31 is supplied to voltage comparators 21 to 24 as their respective comparison inputs. The voltage comparator 21 uses the main phase control voltage VCONT1 generated by the control voltage generator 35 as a reference voltage V1, and generates a ramp signal R generated at the rising timing of the reference voltage V1 and the horizontal drive pulse HD.
AMP and AMP, and the rising timing (trigger timing 1) of the horizontal drive pulse HD1 is determined based on the comparison result. That is, the main phase control voltage VC
By changing ONT1, the horizontal drive pulse HD
1 can be adjusted.

The voltage comparator 22 uses the operation output of the adder 32 as a reference voltage V2, compares the reference voltage V2 with the ramp signal RAMP generated at the falling timing of the horizontal drive pulse HD, and compares the result of the comparison. The falling timing (trigger timing 2) of the horizontal drive pulse HD1 is determined based on this. That is, the duty ratio adjustment voltage VCONT2 which is one of the addition inputs of the adder 32
Is changed, the duty ratio can be adjusted independently of the rising timing of the horizontal drive pulse HD1.

Each comparison output VCO of the voltage comparators 21 and 22
MP1 and VCOMP2 are supplied to the trigger control circuit 25. The trigger control circuit 25 outputs the comparison outputs VCOMP1 and VCOMP of the voltage comparators 21 and 22 which are constantly operating.
2 in the subsequent flip-flop 27 at the correct timing.
, Each comparison output VCOMP1, VCOM
A gate is applied to P2, and a trigger signal supplied to the flip-flop 27 is controlled.

The voltage comparator 23 sets the operation output of the adder 33 as a reference voltage V3, compares the reference voltage V3 with the ramp signal RAMP generated at the rising timing of the horizontal drive pulse HD, and based on the comparison result. Thus, the rising timing (trigger timing 3) of the horizontal drive pulse HD2 is determined. Note that the phase shift amount limiter 39 interposed between the adder 33 and the error amplifier 38 does not operate during normal operation. During the non-operation period of the phase shift amount limiter 39, VERR = VERR '. The details of the phase shift amount limiter 39 will be described later.

Here, since the main phase control voltage VCONT1 generated by the control voltage generator 35 is supplied to the adder 33 as one of its addition inputs, the rising timing of the horizontal drive pulse HD2 is increased. Changes according to the adjustment of the main phase control voltage VCONT1. That is, the horizontal drive pulse HD2 is synchronized with the change of the rising timing of the horizontal drive pulse HD1.
Rise timing also changes. Therefore, when the operating point of the present system is determined by changing the main phase control voltage VCONT1, it is not necessary to adjust the main phase for each of the horizontal drive pulses HD1 and HD2.

The voltage comparator 24 sets the operation output of the adder 34 as a reference voltage V4, compares the reference voltage V4 with the ramp signal RAMP generated at the falling timing of the horizontal drive pulse HD, and compares the result of the comparison. The fall timing (trigger timing 4) of the horizontal drive pulse HD2 is determined based on this. Here, since the main phase control voltage VCONT1 and the duty ratio adjustment voltage VCONT2 are added to and subtracted from the reference voltage V4,
The falling timing of the horizontal drive pulse HD2 also
It changes in synchronization with the main phase control voltage VCONT1 and the duty ratio adjustment voltage VCONT2.

That is, the fall timing of the horizontal drive pulse HD2 changes in synchronization with the change of the rise timing of the horizontal drive pulse HD1 due to the main phase control voltage VCONT1, and the duty of the horizontal drive pulse HD1 due to the duty ratio adjustment voltage VCONT2 also changes. The duty ratio of the horizontal drive pulse HD2 also changes in synchronization with the change in the ratio. Therefore, it is not necessary to adjust the duty ratio for each of the horizontal drive pulses HD1 and HD2.

Each comparison output VCO of the voltage comparators 23 and 24
MP3 and VCOMP4 are supplied to the trigger control circuit 26. As in the case of the trigger control circuit 25, the trigger control circuit 26 gates the comparison outputs VCOMP3 and VCOMP4 of the voltage comparators 23 and 24 which are always operating, and supplies a trigger supplied to the flip-flop 28. Control the signal.

As described above, the horizontal drive pulses HD1, HD for driving the output transistors Q1, Q2 of FIG.
In the horizontal drive circuit 17 that generates the horizontal drive pulses HD1 and HD2, a single ramp generator 3 is provided for two drive pulse generation systems that respectively generate the horizontal drive pulses HD1 and HD2.
By providing the ramp signal RAMP generated in step 1 in common, it is possible to eliminate errors caused by variations in circuit components as compared with the case where the ramp signal RAMP is separately supplied to two drive pulse generation systems. Can be.

The horizontal drive pulse HD1 is generated based on the result of comparison between the main phase control voltage VCONT1 and the ramp signal RAMP, while the adders 33 and 34 generate the main phase control voltage VCON 'with respect to the error signal VERR'.
T1 is added and subtracted, and the horizontal drive pulse HD2 is generated based on the comparison result between the operation outputs V3 and V4 and the ramp signal RAMP, so that the main phase control voltage V
When the phase of the horizontal drive pulse HD1 is adjusted by the CONT1, the two systems of the horizontal drive pulse HD1,
The delay time of HD2 changes the same. As a result, one control voltage generator 35 generates two horizontal drive pulses H.
Since the delay times of D1 and HD2 can be adjusted, the circuit scale can be reduced, and the horizontal drive pulses HD1 and HD2 can be adjusted.
2 can eliminate the variation of the relative delay amount,
Variations in the duty ratio of the horizontal drive pulses HD1, HD2 can be suppressed.

Further, with respect to the position modulation on the time axis of the horizontal drive pulse HD2 for obtaining the target horizontal deflection current by the control signal, the horizontal drive is automatically and simultaneously performed by using the adders 33 and 34. Pulse HD
Since the rising / falling timing of 2 is modulated, only one error amplifier 38 is required, and the circuit scale can be reduced accordingly.

Next, the phase shift amount limiter 39 interposed between the adder 33 and the error amplifier 38 will be described.
In the deflection system, when the phase difference between the horizontal drive pulse HD1 and the horizontal drive pulse HD2 becomes negative, the horizontal deflection current continues to increase, and the output transistors Q1 and Q2 (see FIG. 1) are destroyed. In order to prevent the output transistors Q1 and Q2 from being destroyed, a phase shift amount limiter 39 is provided.

That is, the phase shift amount limiter 39 is provided to prevent the output transistors Q1 and Q2 from being destroyed.
Horizontal drive pulse HD1 and horizontal drive pulse HD2
It has a function to limit so that the phase difference between and does not exceed the set value. Specifically, the error signal VER
When the voltage of R exceeds the set value, the error signal VERR is replaced with a predetermined limit voltage, and this is replaced with the error signal VER.
Output as R '. As already described, the error signal VE
Since RR determines the phase difference between the horizontal drive pulse HD1 and the horizontal drive pulse HD2, setting this limit voltage eliminates the need to change the setting even if the operating point is changed, and protects the output transistors Q1 and Q2. Functions can be realized stably.

Further, by using the protection function of the phase shift amount limiter 39, a function of preventing a large horizontal deflection current from flowing when the power is turned on (so-called soft start function) can be realized. That is, in the present deflection system, when the horizontal drive pulse HD2 has a phase delay, the horizontal deflection current decreases. By utilizing this phenomenon, when the power is turned on, regardless of the error signal VERR, the error signal V
By starting ERR 'from a voltage value corresponding to a large delay phase and gradually decreasing the voltage value from there, the deflection current can be gradually increased. This forced voltage is released when approaching the original control voltage. As a result, a normal control voltage is output as the error signal VERR.

In this horizontal deflection circuit, the ramp signal R
It also has a protection function when the AMP exceeds the normal operation range. That is, in order to realize the present protection function, the ramp generator 31 is provided with a self-resetting capability. If the output transistors Q1 and Q2 continue to be turned on, an excessive deflection current will flow. Therefore, when an abnormal situation occurs, the output transistors Q1 and Q2 need to be turned off. The self-reset function of the ramp generator 31 is one way to achieve this.

For some reason, the flip-flop 27,
If the horizontal drive pulse HD1 and HD2 remain at the low level in the set state, that is, in the timing chart of FIG. 4, the output transistors Q1 and Q2 remain on for at least one cycle of the horizontal drive pulse HD.

As described above, the horizontal drive pulses HD1, HD when the ramp signal RAMP is in the normal operation range.
In order to prevent the disconnection of the lamp 2, the ramp generator 31 shown in FIG.
As can be seen from the timing chart of FIG. 5, at the timing when the ramp signal RAMP reaches the set voltage V5 (trigger timing 5), a forced reset signal VRESET is generated to reset its own circuit state to the initial state. .

Also, the forced reset signal VRESET
Is also supplied to the trigger control circuits 25 and 26, and the flip-flop 2 is supplied through the trigger control circuits 25 and 26.
In the timing chart of FIG. 4, the horizontal drive pulses HD1 and HD2 are reset to a high level. However, in a state where the normal operation is performed, the trigger control circuits 25 and 26 control the forced reset signal VR so that the forced reset signal VRESET does not affect the operation of the flip-flops 27 and 28.
I control ESET. Thereafter, when a normal signal is input, the circuit returns to a normal operation.

[0049]

As described above, according to the present invention,
The duty variation of the horizontal drive pulses HD1, HD2 is reduced, and the horizontal drive pulses HD1, HD2
Can be generated stably.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a circuit configuration example of a horizontal deflection circuit to which the present invention is applied.

FIG. 2 is a block diagram illustrating an example of a specific configuration of a horizontal drive circuit.

FIG. 3 is a timing chart showing a timing relationship between signals of respective units in FIG. 2;

FIG. 4 is a timing chart for explaining a reset function of the ramp generator.

FIG. 5 is a circuit diagram showing a configuration of a horizontal drive circuit according to a conventional example.

FIG. 6 shows a horizontal drive pulse (a), comparison inputs (b) and (c) of a comparator, and a horizontal drive pulse HD1.
It is a waveform diagram which shows each waveform of (d) and HD2 (e).

[Explanation of symbols]

11, 12 first and second parallel circuits, 13 flyback transformer, 14 resonance capacitor, 15 horizontal deflection coil, 17 horizontal drive circuit, 21 to 24 voltage comparator, 31 lamp generator, 32-34 ... adder, 35,
36: Control voltage generator, 38: Error amplifier, 39: Phase shift amount limiter, Q1, Q2: Output transistor, D
1, D2: damper diode, C1, C2: resonance capacitor

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Osamu Yoshioka, Inventor 6-7-35 Kita-Shinagawa, Shinagawa-ku, Tokyo Inside Sony Corporation (72) Yoshiyuki Takayanagi 6-35, Kita-Shinagawa, Shinagawa-ku, Tokyo Sony Corporation F term (reference) 5C068 AA20 BA02 BA07 BA23

Claims (4)

[Claims] 1. A semiconductor device comprising two sets of parallel circuits comprising a switching element, a damper diode, and a resonance capacitor,
These two sets of parallel circuits are connected in series, power is supplied from the connection point via a flyback transformer, and a signal proportional to the current flowing through the horizontal deflection coil is fed back to one switching element to flow through the horizontal deflection coil. A horizontal deflection circuit for controlling a deflection current, comprising: a sawtooth wave generating means for generating a sawtooth wave signal in synchronization with rising and falling timings of a reference horizontal drive signal; and a first driving means for driving the other switching element. A first control voltage generating means for generating a first control voltage for determining a rising / falling timing of the horizontal drive pulse; and a second control voltage generating means for generating a first control voltage based on a comparison result between the sawtooth wave signal and the first control voltage. A first drive pulse generating means for generating one horizontal drive pulse; and a second drive pulse for driving one of the switching elements. A second control voltage generating means for generating, based on a signal proportional to a current flowing through a horizontal deflection coil, a second control voltage serving as a reference for determining the rising / falling timing of the horizontal drive pulse; Calculating means for adding and subtracting the first control voltage to and from the control voltage; and a second drive for generating the second horizontal drive pulse based on a comparison result between the sawtooth wave signal and a calculation output of the calculating means. A horizontal deflection circuit comprising a pulse generation means. 2. The first control voltage generating means also generates a third control voltage for controlling a duty ratio of the first and second horizontal drive pulses, and the arithmetic means generates the first and second horizontal drive pulses. 2. The horizontal deflection circuit according to claim 1, wherein the third control voltage is added to or subtracted from the first and second control voltages that determine the timing of each fall of the second horizontal drive pulse. 3. The horizontal deflection circuit according to claim 1, wherein said second control voltage generating means has a limiter for limiting a voltage value of said second control voltage. 4. The sawtooth wave generating means according to claim 1, wherein:
It has a set voltage higher than the second control voltage, and when the generated sawtooth signal reaches this set voltage,
2. The horizontal deflection circuit according to claim 1, wherein the horizontal deflection circuit has a function of forcibly resetting the second drive pulse generation means.