JP2002368079A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve flatness in a main surface of a wafer by CMP treatment. SOLUTION: After isolation grooves 4 are formed in the main surface of a semiconductor substrate 1S, an insulation film 6 having a thickness of not less than D+W/2, wherein D denotes the depths of the isolation grooves 4 and W denotes a minimum width of active regions surrounded by the isolation grooves 4, is deposited on the main surface by a high density plasma chemical vapor phase deposition method. Then, after a photoresist pattern PR2 is formed on the insulation film 6 so as to cover the film 6 except protrusions 6a of the film 6 which are exposed from the pattern PR2, the exposed top parts of the insulation film 6 are removed by etching. After that, the photoresist pattern PR2 is removed and the insulation film 6 is subjected to a CMP treatment to make parts of the insulation film 6 left in the isolation grooves 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing technique, and more particularly to a technique effective when applied to a trench filling technique.

[0002]

2. Description of the Related Art The present inventors have studied a technique of embedding a so-called element isolation groove for electrically isolating a plurality of elements formed in a semiconductor substrate. The outline is, for example, as follows. First, after a groove is dug in the main surface of a semiconductor substrate, a thermal chemical vapor deposition (T) method using a mixed gas of, for example, TEOS (Tetraethoxysilane) and ozone (O ₃ ) is performed.
An insulating film is deposited on the main surface of the semiconductor substrate by hermal chemical vapor deposition so as to fill the trench. Thereafter, the insulating film is removed by CMP (Chemical Mechanical Polish) so that the insulating film remains only in the groove.
ing) polishing. Thus, a groove-shaped element isolation portion is formed.

[0003]

By the way, the present inventors have proposed a high density plasma chemical vapor deposition (High Density Plasma) method in which a narrow groove can be buried at the same time as the above thermal CVD method. An experiment was conducted to examine the case of using CVD. As a result, they found for the first time that they had the following problems.

That is, when a buried insulating film is formed by a high-density plasma enhanced chemical vapor deposition method, the sectional shape of the insulating film and the manner of attaching the film are different from those of the insulating film formed by the chemical vapor deposition method. For this reason, the uniformity of the insulating film thickness within the main surface of the semiconductor wafer cannot be ensured, and the polishing of the insulating film by CMP may cause a problem such as grinding the main surface of the semiconductor wafer. It is difficult to achieve the flatness of the insulating film in which is embedded the main surface of the semiconductor wafer. In addition, in order to suppress the variation in the insulating film thickness in the main surface of the semiconductor wafer, it is necessary to optimize the arrangement of the dummy patterns and the arrangement of the inversion patterns of the active regions. Furthermore, in the field of semiconductor devices, the diameter of semiconductor wafers and the degree of integration of elements have been increasingly increased, but the above-mentioned problems have been accompanied by the increase in diameter of semiconductor wafers and the miniaturization of separation parts. It becomes remarkable.

An object of the present invention is to provide a technique capable of improving flatness in a main surface of a semiconductor substrate by a CMP process.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0007]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, according to the present invention, when a groove is formed on a main surface of a semiconductor substrate and then the groove is filled with an insulating film deposited by high-density plasma chemical vapor deposition, the thickness of the insulating film at the time of deposition is reduced. Accordingly, a process for improving the flatness of the insulating film before the polishing process is performed.

Further, the present invention is directed to a case where a groove is formed on a main surface of a semiconductor substrate, and the depth of the groove is D and the minimum width of an active region surrounded by the groove is W on the main surface. And D
Depositing an insulating film having a thickness of + W / 2 or more by high-density plasma chemical vapor deposition;
Forming a masking pattern on the insulating film such that a relatively large protrusion formed on the upper surface of the insulating film is exposed and the other portion is covered, and the masking pattern is exposed from the masking pattern as a mask. Etching the upper portion of the insulating film, and polishing the insulating film such that the insulating film remains in the groove after removing the masking pattern.

Further, the present invention provides a step of forming a groove in the main surface of a semiconductor substrate, wherein D is the depth of the groove, and W is the minimum width of the active region surrounded by the groove. Depositing an insulating film having a small thickness on the main surface of the semiconductor substrate by high-density plasma chemical vapor deposition, depositing a sacrificial film on the insulating film, and etching the sacrificial film and the insulating film. A backing step, and a step of forming a groove-type separation portion on the main surface of the semiconductor substrate by polishing the insulating film so that the insulating film after this step is left in the groove.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Before describing the present invention in detail,
The meaning of the terms in the present application is as follows.

1. A wafer is a silicon single crystal substrate (also referred to as a semiconductor wafer, generally having a substantially circular shape), a sapphire substrate, a glass substrate, other insulating, anti-insulating or semiconductor substrates used for manufacturing integrated circuits, and a composite substrate thereof. And the like.

2. High density plasma chemical vapor deposition (HD
P-CVD: High Density Plasma-Chemical Vapor Dep
Osition) is one method of forming a buried insulating film, and is generally a CVD method using plasma having an ion density of about 10 ¹² to 10 ¹³ / cm ³ . Due to the high ion density, applying a bias RF (high frequency) voltage to the substrate side adds the effect of sputter etching due to collision of active species with the substrate surface, making it possible to form a film while performing sputter etching. Become. Thereby, the film can be embedded in the narrow groove. The embedding performance and the like can be controlled by changing the ratio between the sputter etching rate and the film forming rate.

3. Chemical mechanical polishing (CMP: Chemical Mec)
In general, hanical polishing is a process in which a surface to be polished is brought into contact with a polishing pad made of a relatively soft cloth-like sheet material or the like, and polishing is performed by moving the surface relatively while supplying slurry. In addition, in the present application, a CML (Chemical Mechanical Lap) that performs polishing by relatively moving a surface to be polished with respect to a hard grindstone surface.
ping), other types that use fixed abrasives, and abrasive-free CMP that does not use abrasives.

In the following embodiments, when necessary for the sake of convenience, the description will be made by dividing into a plurality of sections or embodiments, but unless otherwise specified, they are not irrelevant to each other. One has a relationship with some or all of the other, such as modified examples, details, and supplementary explanations.

Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, amount, range, etc.), the number is particularly limited and is limited to a specific number in principle. Except in some cases, the number is not limited to the specific number, and may be more than or less than the specific number.

Furthermore, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily essential unless otherwise specified and when it is deemed essential in principle. Needless to say, there is nothing.

Similarly, in the following embodiments, when referring to the shapes, positional relationships, and the like of the constituent elements, etc., unless otherwise specified, and unless otherwise apparently in principle, it is substantially the same. And those similar or similar to the shape or the like. This is the same for the above numerical values and ranges.

In all the drawings for describing the embodiment, parts having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.

In the drawings used in the present embodiment, hatching may be used even in a plan view so as to make the drawings easy to see.

In this embodiment, a MIS • FET (Metal Insula) representing a field effect transistor is used.
tor Semiconductor Field Effect Transistor)
S is abbreviated, p-channel MIS • FET is abbreviated as pMIS, and n-channel MIS • FET is abbreviated as nMIS.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1) A method of manufacturing a semiconductor device according to the present embodiment will be described with reference to FIGS.

FIG. 1 is a sectional view of a main part of a wafer 1 during a manufacturing process of the semiconductor device. Wafer 1
For example, it is made of a flat circular thin plate having a diameter of about 300 mm. A semiconductor substrate (hereinafter, simply referred to as a substrate) 1S constituting the wafer 1 is made of, for example, single-crystal silicon, and its main surface (device formation surface) is made of, for example, silicon oxide (SiO _x ) having a thickness of about 10 nm. The insulating film 2 is formed by a thermal oxidation method or the like. Further, on the insulating film 2, for example, silicon nitride (Si
_{xN y} ) or the like (first insulating film) 3 is formed by low-pressure CVD.
It is formed by a method or the like.

First, on the insulating film 3 of such a substrate 1,
As shown in FIG. 2, for example, a photoresist pattern PR
1 is formed by a photolithography technique. The photoresist pattern PR1 is patterned so as to cover the active region (device formation region) and expose the other region (isolation region).

Subsequently, the photoresist pattern PR
1 is used as an etching mask, the insulating films 2 and 3 exposed therefrom are removed, and then the photoresist pattern PR1 is removed. Thereafter, using the remaining insulating films 2 and 3 as an etching mask, the substrate 1 exposed therefrom is removed by etching, thereby forming a separation groove (groove) 4 in the main surface of the substrate 1 as shown in FIG. . At this stage, the depth of the separation groove 4 (the distance from the main surface of the substrate 1 to the bottom surface of the separation groove 4) is
For example, it is about 200 to 350 nm. Here, a group of relatively wide separation grooves 4, narrow width separation grooves 4, separation grooves 4 arranged relatively apart and separation grooves 4 arranged relatively densely are illustrated. are doing. The distance between the separation grooves 4 adjacent to each other, ie, the width WL of the widest active region is, for example, about 100 μm.

Next, by subjecting the substrate 1 to a thermal oxidation treatment, as shown in FIG. 4, an insulating film 5 made of, for example, silicon oxide having a thickness of about 30 nm is formed on the inner surface (side surface and bottom surface) of the separation groove 4. To form At this time, as shown in FIG. 4B, the depth of the isolation groove 4 at this stage, that is, the distance from the upper surface of the insulating film 3 to the upper surface of the insulating film 5 on the bottom surface of the isolation groove 4 is determined by the step D and the device. The minimum width of the region (active region) is defined as a minimum device region width W.

Subsequently, as shown in FIGS. 5 and 6, for example, a monosilane gas and oxygen (O ₂ )
HD using mixed gas of gas and argon (Ar) gas
An insulating film (second insulating film) 6 made of a silicon oxide film is deposited by a P-CVD method or the like. By adopting the HDP-CVD method, the embedding property of the insulating film 6 in the isolation trench 4 can be improved. As a reaction gas, for example, T
A mixed gas of EOS (Tetraethoxysilane) gas, oxygen (O ₂ ) gas and argon gas, or a mixed gas of disilane gas, oxygen (O ₂ ) and argon gas may be used.
Further, a helium (He) gas may be mixed instead of the argon gas.

In the present embodiment, the thickness of the insulating film 6 is set to be not less than the step D + (minimum device region width W / 2) (see FIG. 6). If the insulating film 6 is deposited thinner than this, a projection having a triangular cross section is formed on the upper surface thereof. (So-called micro-scratch). Micro-scratch is increased by etching or cleaning after the CMP process, and causes a problem of short circuit between elements or short circuit between gates. This is to prevent this.

In the insulating film 6, the portion of the insulating film 6 deposited on the relatively wide active region has its upper surface protruding relatively higher than the upper surface of the insulating film 6 in the other region. (Protrusions). The thickness (distance from the upper surface of the insulating film 3 to the upper surface of the insulating film 6) D2 of the highest protruding portion 6a of the protruding portion is not particularly limited, but is, for example, about 900 to 1200 nm. .
The inclination angle θ of the side surface of the protrusion 6a (the angle between the upper surface of the insulating film 6 and the side surface of the protrusion 6a) is, for example, 4
It is about 5 °.

Thereafter, as shown in FIG. 7, a photoresist pattern (masking pattern) PR2 is formed on the insulating film 6 by photolithography. The photoresist pattern PR2 is formed such that the protrusion 6a of the insulating film 6 is exposed to a certain degree or more, and the other part is covered. Such a photoresist pattern PR2 may be formed by removing the photoresist film where the width of the active region is larger than a predetermined value.

Here, the end portion (opening end portion) of the photoresist pattern PR2 does not end in the middle of the inclined side surface of the protrusion 6a, and the upper surface of the insulating film 6 does not cover the side surface of the protrusion 6a. It is designed to terminate at a part. This is for the following reason. That is, in the subsequent etching process of the insulating film 6, if the photoresist pattern PR2 is applied to the inclined side surface of the protrusion 6a, the insulating film 6 where the photoresist pattern PR2 is applied is left, As a result of the etching removal of the projection 6a that is not covered with the photoresist pattern PR2, an etching residue having a square cross section is generated on the inclined side surface of the projection 6a that is covered with the photoresist pattern PR2. Such an etching residue is removed by a CMP (Chemical Mechanical Po
lish) During processing, chipping causes micro-scratch. As described above, the photoresist pattern PR
The reason why the termination is set to 2 is to prevent such a problem caused by the residual etching.

Next, as shown in FIG. 8, using the photoresist pattern PR2 as an etching mask, the upper portion of the insulating film 6 exposed from the photoresist pattern PR2 is removed by etching. Thereby, the height of the upper surface of the protrusion 6a is made substantially the same as the height of the upper surface of the insulating film 6 other than the protrusion 6a. In this etching process, the etching rate ratio between the insulating film 3 and the insulating film 6 is increased. This is for the following reason, for example. Photoresist pattern PR2
In the portion of the insulating film 6 exposed from the bottom, the foot portion of the protrusion 6a is almost flat because of the termination of the photoresist pattern PR2, and the thickness of the insulating film 6 is smaller than that of the protrusion 6a. And relatively thin. For this reason, as shown by the broken line in FIG. 8, the bottom portion of the projection 6a is etched deeper than the other exposed portions, and the upper portion of the substrate 1 may be etched away.
On the other hand, by increasing the etching rate ratio between the insulating film 3 and the insulating film 6, even if the etching progresses greatly at the foot of the protrusion 6a, the etching is performed on the insulating film 3 This can prevent the problem that the upper portion of the substrate 1 is removed by etching.

Subsequently, the upper part of the insulating film 6 on the wafer 1 is
As shown in FIG. 9, the entire surface is etched back by, for example, anisotropic dry etching. By performing this process, the polishing amount in the subsequent CMP process can be reduced, so that the variation in the polishing amount of the insulating film 6 in the main surface of the wafer can be reduced. In some cases, this processing need not be performed.

Thereafter, the main surface of the wafer 1 is
P treatment is performed until the upper surface of the insulating film 3 is exposed.
Is polished, as shown in FIG.
The main surface of is flattened. In this CMP process, conditions are set such that the polishing selectivity between the silicon oxide film and the silicon nitride film is increased. That is, the condition is such that the silicon oxide film is more easily polished than the silicon nitride film.
Thus, the insulating film 6 can be almost selectively polished with the insulating film 3 made of the silicon nitride film as a stopper. Thus, the insulating film 6 is formed in the separation groove 4.
To form a field insulating portion 7. In this case, the field insulating portion 7 is made of SGI (Shallow Groove Isola).
This is a groove-shaped separation part called an option).

Thereafter, the insulating film 3 is selectively removed by etching, and a predetermined element such as a MIS, a bipolar transistor or a diode is formed in the active region by a usual method. For example, in the case of MIS, after a gate insulating film is formed on the active region of the substrate 1 by a thermal oxidation method or the like, a conductor film for forming a gate electrode is deposited on the main surface of the substrate 1, and this is subjected to photolithography technology and A gate electrode is formed by patterning using a dry etching technique. Subsequently, a predetermined impurity (phosphorus (P), arsenic (As), or boron (B)) is introduced into the substrate 1 by an ion implantation method or the like, so that MIS source and drain semiconductor regions are formed on the substrate 1. Form.

Next, FIG. 11 shows an example of a CMP apparatus used in the above-mentioned CMP processing. The polishing processing unit of the CMP apparatus 8 includes:
A housing 8a having an open top is provided.
A polishing plate (platen) 8d, which is rotationally driven by a motor 8c, is attached to the upper end of a rotating shaft 8b rotatably attached to the rotating shaft 8b. A polishing pad 8e formed by uniformly applying a synthetic resin having a large number of pores is attached to the surface of the polishing plate 8d.

The polishing section has a wafer carrier 8f for holding the substrate 1. The drive shaft 8g to which the wafer carrier 8f is attached is
f, and is rotatably driven by a motor (not shown), and is moved up and down above the polishing plate 8d.

The substrate 1 is held on the wafer carrier 8f by a vacuum suction mechanism (not shown) provided on the wafer carrier 8f with its main surface, that is, the surface to be polished facing downward. A concave portion 8f1 for accommodating the substrate 1 is formed at a lower end portion of the wafer carrier 8f. When the substrate 1 is accommodated in the concave portion 8f1, the surface to be polished is
f is substantially the same as or slightly protrudes from the lower end surface.

A slurry supply pipe 8h for supplying a polishing slurry S is provided above the polishing plate 8d between the surface of the polishing pad 8e and the surface to be polished of the substrate 1, and is supplied from the lower end thereof. The polished surface of the substrate 1 is chemically and mechanically polished by the polishing slurry S. The polishing slurry S is
For example, silicon oxide (SiO ₂ ) such as famed silica or colloidal silica, or cerium oxide (Ce)
A strong alkaline liquid containing O) -based abrasive grains is used.
In the case of using the latter, the polishing rate can be improved as compared with the former, and the selectivity between the silicon oxide film and the silicon nitride film is sufficiently high because cerium oxide has a property of causing a chemical reaction with the silicon oxide film. Thus, sufficient flatness can be obtained on the upper surface of the polished silicon oxide film. To make it alkaline, a method using ammonia (NH ₄ OH), an organic amine, or the like, and a method using potassium hydroxide (KOH)
Is used. When the latter is used, the dispersibility of the abrasive grains is excellent. That is, aggregation is unlikely to occur,
It is possible to obtain a slurry that hardly causes micro scratches.

Further, the polishing processing section is provided with a polishing pad 8e.
Is provided with a dresser 8i, which is a tool for shaping (dressing) the surface of. The dresser 8i is attached to the lower end of a drive shaft 8j that moves up and down above the polishing plate 8d, and is driven to rotate by a motor (not shown).

As described above, according to the present embodiment, the following effects can be obtained. (1) By embedding the isolation groove 4 with the insulating film 6 by the HDP-CVD method, it is possible to improve the embedding property of the insulating film 6 in the isolation groove 4. (2) When the insulating film 6 is deposited by the HDP-CVD method, the thickness is set to (D + W / 2) or more, so that the
Since micro-scratching can be suppressed or prevented during the P process, short-circuiting between elements and short-circuiting between gates due to microscratching can be suppressed or prevented. Thus, the yield of the semiconductor device can be improved. (3) After depositing the insulating film 6 by the HDP-CVD method, only the most protruding protrusion 6a on the upper surface is etched, and the height is made equal to the height of the surrounding insulating film 6. In addition, it is possible to improve the film thickness uniformity of the insulating film 6 before the CMP process. (4) By the above (3), it is possible to improve the flatness in the main surface of the wafer 1 after the CMP processing. (5) According to the above (3), it is possible to suppress or prevent such a problem that the main surface (active region) of the wafer 1 is cut off during the CMP process. For this reason, it is possible to improve the electrical characteristics of the element formed in the active region. (6). The insulating film 6 in the main surface of the wafer 1 prior to the CMP process
It is not necessary to dispose a dummy pattern for suppressing the variation in the thickness of the semiconductor device, so that the manufacturing process of the semiconductor device can be simplified. (7) According to the above (2) and (6), the cost of the semiconductor device can be reduced.

(Second Embodiment) A method of manufacturing a semiconductor device according to a second embodiment will be described with reference to FIGS.

First, after going through the steps shown in FIGS. 1 to 4 used in the first embodiment, in the second embodiment, FIG.
As shown in FIG. 13, an insulating film 6 made of a silicon oxide film is deposited on the main surface of the substrate 1 by the same HDP-CVD method as in the first embodiment. However, in the second embodiment, the thickness of the insulating film 6 (the thickness from the bottom of the isolation groove 5 to the flat upper surface of the insulating film 6 above it) is
The height is set to be equal to or less than the step D + (minimum device area width W / 2) (see FIG. 13). In this case, a projection 6b having a triangular cross section or a trapezoidal cross section is formed on the upper surface of the insulating film 6. In the second embodiment, the protrusion 6b
Are dispersed and left in the main surface of the wafer 1. In this case, an insulating film such as an SOG (Spin On Glass) film is deposited on the upper surface of the insulating film 6 in a subsequent step, but there is a portion where the protrusion 6b is not left. Then, the thickness of the insulating film deposited on the portion where the protrusion 6b is left and the thickness of the insulating film deposited on the portion where the protrusion 6b is left are changed, and this is to prevent the thickness.

Subsequently, as shown in FIG. 14, a sacrificial film 9 such as an SOG film or a photoresist film is deposited on the insulating film 6 by a spin coating method or the like. Since the projections 6b are dispersed on the upper surface of the insulating film 6 as described above, the sacrificial film 9 is deposited such that the upper surface is substantially flat. Thereafter, the sacrificial film 9 and the insulating film 6 are etched back by an anisotropic dry etching method under the condition that there is no etching selectivity between the sacrificial film 9 and the insulating film 6.
Thereby, as shown in FIG. 15, the upper surface of the insulating film 6 is flattened. At this stage, the insulating film 6 is left on the insulating film 3.

Thereafter, the insulating film 6 remaining on the main surface of the substrate 1 is polished by the CMP method in the same manner as in the first embodiment, thereby flattening the main surface of the wafer 1 as shown in FIG. Then, an insulating film 6 is buried in the isolation trench 4 to form a field insulating portion 7. Hereinafter, the first embodiment will be described.
Therefore, the description is omitted.

As described above, according to the second embodiment, the following effect can be obtained in addition to the effect (1) obtained in the first embodiment. (1) After depositing an insulating film 6 by HDP-CVD so that the thickness is not more than (D + W / 2), a sacrificial film 9 is deposited thereon, By performing the etch-back process, it is possible to improve the film thickness uniformity of the insulating film 6 before the CMP process. (2) According to the above (1), it is possible to improve the flatness in the main surface of the wafer 1 after the CMP processing. (3) According to the above (1), it is possible to suppress or prevent inconveniences such as cutting the main surface (active region) of the wafer 1 during the CMP process. For this reason, it is possible to improve the electrical characteristics of the element formed in the active region. (4) Prior to the CMP process, the insulating film 6 in the main surface of the wafer 1
The arrangement of the dummy pattern for suppressing the variation in the thickness of the semiconductor device and the arrangement of the inversion pattern of the active region (the steps of FIGS. 7 to 9 in the first embodiment) can be eliminated, thereby simplifying the manufacturing process of the semiconductor device. Is possible. (5) According to the above (1), the protrusion 6b is removed by etch-back, so that the occurrence of micro-scratch can be suppressed or prevented during the CMP process. A short circuit between gates can be suppressed or prevented. This allows
It is possible to improve the yield of semiconductor devices. (6) According to the above (4) and (5), the cost of the semiconductor device can be reduced.

Third Embodiment In the third embodiment, for example, a DRAM (Dynamic Random Access Memory)
The case where the technical idea of the present invention is applied to the embodiment will be described.

FIG. 17 is a plan view of a main part of a memory cell array in the DRAM of the third embodiment. In this memory cell array, a plurality of short band-shaped active regions L extending in the left-right direction of FIG.
And are arranged regularly along the left-right direction (direction X). The minimum device region width W is the minimum width of the active region L. In this case, the minimum device area width substantially corresponds to the gate width of MISQs for memory cell selection. The periphery of the active region L is surrounded by the above-mentioned trench type field insulating portion 7 for isolation. This field insulating part 7 is formed by the method of the first or second embodiment.

FIG. 18 is a plan view of a main part of a memory cell array in which word lines 10, data lines 11 and the like are arranged in the memory cell array of FIG. FIG.
9 is a sectional view of a portion corresponding to the line AA in FIG.

In the substrate 1, MISQs for selecting a memory cell are provided in an active region L surrounded by a trench type field insulating portion 7 for isolation. This MISQs
For example, it is made of nMIS, and has a pair of source and drain semiconductor regions 12, a gate insulating film 13, and a gate electrode 14. The semiconductor region 12 contains, for example, phosphorus (P) or arsenic (As). The gate insulating film 13 is made of, for example, a silicon oxide film. The gate electrode 14 constitutes a part of the word line 10, and is formed by providing a metal film such as tungsten on a low-resistance polysilicon film via a barrier metal such as tungsten nitride. It has a polymetal gate structure. The gate electrode structure is not limited to poly-metal gate structure, for example, by providing a tungsten silicide on a low resistance polysilicon film (WSi _x) or cobalt silicide (CoSi _x), also as a so-called polycide gate structure Alternatively, a single film of a low-resistance polysilicon film may be used. When a polymetal gate structure is used, the resistance of the word line 10 can be reduced. Therefore, the signal transmission speed can be improved, and the number of memory cells that can be connected to one word line 10 can be increased. A plug 15 is provided in one semiconductor region 12 of the MISQs.
The data line 11 is electrically connected through A. A capacitor 16 is electrically connected to the other semiconductor region 12 of the MIS Qs through plugs 15B and 15C. The capacitor 16 is an element for storing a charge for storing information, and is configured between the lower electrode 16A and the upper electrode 16B via a capacitance insulating film 16C.

According to the third embodiment, the following effects can be obtained for the reasons described in the first and second embodiments.

First, the electrical characteristics of the MISQs for selecting a memory cell can be improved. For example, since the leakage of the charge of the capacitor 16 can be suppressed, the refresh characteristics can be improved. Further, since the setting accuracy of the threshold voltage of MISQs can be improved, D
The operation reliability of the RAM can be improved.

Further, since the burying property in the field insulating portion 7 can be improved, short-circuit failure between memory cells adjacent to each other can be suppressed or prevented. For this reason, the interval between adjacent memory cells can be narrowed, and the possible increase in the memory capacity in one chip can be promoted.

(Embodiment 4) In Embodiment 4, for example, a flash memory (EEPROM; Electric)
A case where the technical idea of the present invention is applied to an erasable programmable read only memory (Erasable Programmable Read Only Memory) will be described.

FIG. 20 is a plan view of a main part of a memory cell array in an AND type flash memory (EEPROM) according to the fourth embodiment. In this memory cell array, a plurality of band-shaped active regions L extending in the vertical direction in FIG. 20 are arranged along the horizontal direction in FIG. The above minimum device area width W
Is the minimum width of the active region L. This field insulating part 7 is formed by the method of the first or second embodiment.

FIG. 21 is a plan view of a main part of a memory cell array in which word lines 17, data lines 18, source lines 19 and the like are arranged in the memory cell array of FIG. FIG. 22 is a cross-sectional view of a portion corresponding to line CC in FIG. Flash memory (EEP
ROM) has a 1MIS structure, and has source and drain semiconductor regions 20s, 20s.
d, a tunnel insulating film 21, a floating gate electrode 22, an inter-gate insulating film 23, and a control gate electrode 24. The source and drain semiconductor regions 20s and 20d contain, for example, phosphorus or arsenic. The source semiconductor region 20s forms a part of the source line 19. The drain semiconductor region 20 d forms a part of the data line 18. That is, the source line 19 and the data line 18 are formed in a semiconductor region formed on the substrate 1. The tunnel insulating film 21 is made of, for example, a silicon oxide film. The floating gate electrode 22 is made of, for example, low-resistance polysilicon. The inter-gate insulating film 23 is made of, for example, a silicon oxide film. The control gate electrode 24 is formed by providing a silicide layer such as tungsten silicide on low-resistance polysilicon, for example. The control gate electrode 24 is constituted by a part of the word line 17.

According to the fourth embodiment, the following effects can be obtained for the reasons described in the first and second embodiments.

First, the stability of the writing, erasing and data reading operations of the memory cell can be improved.
Further, since the burying property in the field insulating portion 7 can be improved, short-circuit failure between memory cells adjacent to each other can be suppressed or prevented. Therefore, also in a flash memory (EEPROM), the interval between adjacent memory cells can be narrowed, and the memory capacity that can be formed in one chip can be promoted.

(Fifth Embodiment) In the fifth embodiment, for example, an SRAM (Static Random Access Memory)
The case where the technical idea of the present invention is applied to the embodiment will be described.

FIG. 23 is a plan view of a main part of a memory cell array in an SRAM according to the fifth embodiment. FIG. 24 is a sectional view of a portion corresponding to line EE in FIG. In this memory cell array, a planar L-shaped and inverted L-shaped active region L1 and a short rectangular active region L2 extending in the left-right direction of FIG. 23 are arranged. The minimum device region width W is the minimum width of the active region L1 where the word lines 25 intersect. The periphery of each of the active regions L1 and L2 is surrounded by a field insulating portion 7. This field insulating part 7 is formed by the method of the first or second embodiment. Wiring 26A,
26B is arranged to cross active regions L1 and L2.

In FIG. 23, a region surrounded by a broken line shows one memory cell MC. The memory cell MC has 2
MISQd1 and Qd2 for two drivers, MISQt1 and Qt2 for two transfers, and MISQ for two loads
L1 and QL2. Each MIS Qd1, Qd
2, Qt1, Qt2, QL1, and QL2 are, for example, nMI
S. Each MIS Qd1, Qd2, Qt
1, Qt2, QL1, and QL2 have substantially the same basic structure. Here, as shown in FIG.
The basic structure will be described using SQd1 and Qd2 as an example.

Each of the driver MISs Qd1 and Qd2 has a semiconductor region 27 for source and drain, a gate insulating film 28, and a gate electrode 29. The semiconductor region 27 contains, for example, phosphorus or arsenic. The gate insulating film 28 is made of, for example, a silicon oxide film or a silicon oxynitride film. The silicon oxynitride film has a structure in which nitrogen is deposited at the interface between the gate insulating film 28 and the substrate 1, and by using this, it is possible to improve hot carrier resistance. The gate electrode 29 is formed by forming tungsten silicide or cobalt silicide on a low-resistance polysilicon film, for example, and is formed by a part of the wirings 26A and 26B. MI for transfer
The gate electrodes of SQt1 and Qt2 are formed by a part of the word line 25 (a part overlapping the active region L1). The gate electrodes of the load MISs QL1 and QL2 are part of the wirings 26A and 26B (the part overlapping the active region L2).
It is composed of

According to the fifth embodiment, the following effects can be obtained for the reasons described in the first and second embodiments.

First, the operational reliability of the SRAM can be improved. Further, since the burying property in the field insulating portion 7 can be improved, short-circuit failure between memory cells adjacent to each other can be suppressed or prevented. Therefore, also in the SRAM, the interval between adjacent memory cells can be narrowed, and the increase in the memory capacity that can be formed in one chip can be promoted.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment and can be variously modified without departing from the gist of the invention. Needless to say,

For example, it can be adopted as a method for filling a groove formed between adjacent wirings on a semiconductor substrate with an insulating film.

In the above description, the case where the invention made by the present inventor is mainly applied to the method of manufacturing a semiconductor device having a memory circuit, which is the field of application, has been described. However, the present invention is not limited to this. For example, the present invention can be applied to a method of manufacturing a semiconductor device having a logic circuit such as a microprocessor or the like, and a method of manufacturing a hybrid semiconductor device in which the memory circuit and the logic circuit are formed on the same substrate.

[0069]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

That is, after a groove is formed on the main surface of the semiconductor substrate, when the groove is filled with an insulating film deposited by high-density plasma enhanced chemical vapor deposition, the thickness depends on the thickness of the insulating film at the time of deposition. By performing the process for improving the flatness of the insulating film before the polishing process, it is possible to improve the flatness in the main surface of the semiconductor substrate by the polishing process.

[Brief description of the drawings]

FIG. 1 is a fragmentary cross-sectional view of a semiconductor device according to an embodiment of the present invention during a manufacturing step thereof;

FIG. 2 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 1;

3 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 2;

4A is a cross-sectional view of a main part of the semiconductor device during a manufacturing step following that of FIG. 3, and FIG. 4B is an enlarged cross-sectional view of the main part of FIG.

5 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 4;

FIG. 6 is an enlarged sectional view of a main part of FIG. 5;

FIG. 7 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIGS. 5 and 6;

8 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 7;

9 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 8;

10 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 9;

FIG. 11 is an explanatory diagram of an example of a CMP apparatus used in a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 12 is an essential part cross sectional view of the semiconductor device of another embodiment of the present invention during a manufacturing step;

FIG. 13 is an enlarged cross-sectional view of a main part of the semiconductor device in the same step as in FIG. 12;

FIG. 14 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIGS. 12 and 13;

15 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 14;

16 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 15;

FIG. 17 is a plan view of relevant parts of a semiconductor device according to another embodiment of the present invention;

18 is a main part plan view of the semiconductor device in which another member is arranged in FIG.

FIG. 19 is a sectional view of a portion corresponding to line AA in FIG. 18;

FIG. 20 is a plan view of a main part of a semiconductor according to another embodiment of the present invention;

FIG. 21 is a plan view of a principal part of the semiconductor device in which another member is arranged in FIG. 20;

FIG. 22 is a cross-sectional view of a portion corresponding to line CC in FIG. 21;

FIG. 23 is a plan view of a main part of a semiconductor according to another embodiment of the present invention;

24 is a sectional view of a portion corresponding to line EE in FIG. 23;

[Explanation of symbols]

Reference Signs List 1 wafer 1S semiconductor substrate 2 insulating film 3 insulating film (first insulating film) 4 separation groove 5 insulating film 6 insulating film (second insulating film) 6a protrusion 6b protrusion 7 field insulating portion (groove-type separation portion) 8 CMP device 8a Housing 8b Rotary shaft 8c Motor 8d Polishing machine 8e Polishing pad 8f Wafer carrier 8f1 Depression 8g Drive shaft 8h Slurry supply tube 8i Dresser 8j Drive shaft 9 Sacrificial film 10 Word line 11 Data line 12 Semiconductor region 13 Gate insulating film 14 Gate electrode 15A to 15C Plug 16 Capacitor 16A Lower electrode 16B Upper electrode 16C Capacitive insulating film 17 Word line 18 Data line 19 Source line 20s, 20d Semiconductor region 21 Tunnel insulating film 22 Floating gate electrode 23 Intergate insulating film 24 Control gate electrode 25 Word line 26A, 2 B wiring 27 semiconductor region 28 gate insulating film 29 gate electrode PR1 photoresist pattern PR2 photoresist pattern (masking pattern) L active region L1, L2 active region Qs MIS • FET for memory cell selection Qd1, Qd2 MIS • FET for driver MIS • FET for transfer Qt1, Qt2 MIS • FET for load QL1, QL2

────────────────────────────────────────────────── ─── of the front page continued (51) Int.Cl. ⁷ identification mark FI theme Court Bu (reference) H01L 27/108 H01L 29/78 371 27/11 27/115 29/788 29/792 F -term (reference) 5F032 AA37 AA44 AA45 BA02 CA14 CA17 DA02 DA04 DA10 DA22 DA25 DA28 DA33 DA53 5F083 AD10 AD42 AD48 BS27 EP02 EP05 EP22 EP79 ER22 GA02 GA09 GA27 GA30 JA03 JA05 JA32 JA38 JA39 JA40 JA53 KA13 MA06 MA17 MA20 NA01 PR12 PR21 PR40 BA0712 BE07 BF09 BH02 BH30

Claims (18)

[Claims] 1. A method of manufacturing a semiconductor device, comprising: (a) forming a groove in a main surface of a semiconductor substrate; (b) setting the depth of the groove to D, Assuming that the minimum width of the enclosed active region is W, an insulating film having a thickness of D + W / 2 or more is deposited on the main surface of the semiconductor substrate by high-density plasma chemical vapor deposition. Process,
(C) forming a masking pattern on the insulating film so that a relatively large protrusion formed on the upper surface of the insulating film is exposed and the other is covered, and (d) masking the masking pattern. (E) removing the masking pattern by etching the upper portion of the insulating film exposed therefrom; (f) removing the masking pattern;
A step of forming a groove-type isolation portion in the main surface of the semiconductor substrate by polishing the insulating film so that the insulating film after the step is left in the groove. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the opening end of the masking pattern does not end at an inclined portion of the protrusion, but ends at a substantially flat portion of the upper surface of the insulating film at the foot thereof. Forming the masking pattern. 3. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of etching back the entire upper surface of said insulating film after said step (e) and before said step (f). Manufacturing method of a semiconductor device. 4. A method of manufacturing a semiconductor device, comprising: (a) patterning a first insulating film on a main surface of a semiconductor substrate; and (b) forming a pattern on the first insulating film. Forming a groove in the main surface of the semiconductor substrate by etching and removing the semiconductor substrate exposed therefrom as a mask, (c) setting the depth of the groove to D, and setting the depth of the active region surrounded by the groove to the maximum. Depositing a second insulating film having a thickness of D + W / 2 or more when the small width is W on the main surface of the semiconductor substrate by high-density plasma chemical vapor deposition; A) forming a masking pattern on the second insulating film such that a relatively large protrusion formed on the upper surface of the second insulating film is exposed and the other is covered; and (e) the masking pattern. The mask Etching the upper portion of the second insulating film exposed therefrom, (f) removing the masking pattern, and (g) placing the second insulating film after the (f) process in the trench. Forming a groove-shaped separation portion on the main surface of the semiconductor substrate by polishing the second insulating film so as to be left in the step. 5. The method of manufacturing a semiconductor device according to claim 4, wherein an opening end of the masking pattern does not end at an inclined portion of the protrusion, but ends at a substantially flat portion of the insulating film at a foot thereof. A method of manufacturing a semiconductor device, comprising forming the masking pattern as described above. 6. The method for manufacturing a semiconductor device according to claim 4, wherein in the step (e), the etching process is performed under a condition that an etching selectivity between the second insulating film and the first insulating film is increased. A method for manufacturing a semiconductor device. 7. The method for manufacturing a semiconductor device according to claim 4, further comprising a step of etching back the entire upper surface of the insulating film after the step (f) and before the step (g). A method for manufacturing a semiconductor device, comprising: 8. The method of manufacturing a semiconductor device according to claim 4, wherein, in the step (g), a polishing selectivity between the second insulating film and the first insulating film is reduced. A method for manufacturing a semiconductor device, comprising: performing a polishing process under conditions that increase the size. 9. The method for manufacturing a semiconductor device according to claim 4, wherein said first insulating film is made of a silicon nitride film, and said second insulating film is made of a silicon oxide film. A method for manufacturing a semiconductor device. 10. The method for manufacturing a semiconductor device according to claim 4, wherein after the step (g), a gate insulating film is formed in an active region of the semiconductor substrate surrounded by the trench-shaped isolation portion. Forming a semiconductor device, forming a gate electrode on the gate insulating film, and forming source and drain semiconductor regions on the semiconductor substrate. 11. A method of manufacturing a semiconductor device, comprising: (a) forming a groove in a main surface of a semiconductor substrate; (b) setting the depth of the groove to D; Depositing an insulating film having a thickness smaller than D + W / 2 on the main surface of the semiconductor substrate by high-density plasma chemical vapor deposition, where W is the minimum width of the enclosed active region; (c) A) a step of depositing a sacrificial film on the insulating film, (d) a step of etching back the sacrificial film and the insulating film, and (e) a step of leaving the insulating film after the step (d) in the groove. A step of forming a groove-type separation portion on the main surface of the semiconductor substrate by polishing the insulating film. 12. The method of manufacturing a semiconductor device according to claim 11, wherein, in the process of forming the insulating film in the step (b), the protrusions are dispersedly arranged on the upper surface of the insulating film. A method for manufacturing a semiconductor device. 13. A method for manufacturing a semiconductor device, comprising: (a) patterning a first insulating film on a main surface of a semiconductor substrate; and (b) forming a pattern on the first insulating film. Forming a groove in the main surface of the semiconductor substrate by etching and removing the semiconductor substrate exposed therefrom as a mask, (c) setting the depth of the groove to D, and setting the depth of the active region surrounded by the groove to the maximum. Depositing a second insulating film having a thickness smaller than D + W / 2 on the main surface of the semiconductor substrate by a high-density plasma chemical vapor deposition method, where the small width is W;
(D) depositing a sacrificial film on the second insulating film;
(E) a step of etching back the sacrificial film and the second insulating film, and (f) polishing the second insulating film so that the second insulating film after the step (e) remains in the groove. Forming a groove-shaped separation portion on the main surface of the semiconductor substrate. 14. The method of manufacturing a semiconductor device according to claim 13, wherein, in the process of forming the insulating film in the step (c), the protrusions are dispersed on the upper surface of the insulating film. A method for manufacturing a semiconductor device. 15. The method of manufacturing a semiconductor device according to claim 13, wherein in the step (f), conditions are set such that a polishing selectivity between the second insulating film and the first insulating film is increased. A method for manufacturing a semiconductor device, comprising performing a polishing process. 16. The method of manufacturing a semiconductor device according to claim 13, wherein said first insulating film is made of a silicon nitride film, and said second insulating film is made of a silicon oxide film. Device manufacturing method. 17. The method of manufacturing a semiconductor device according to claim 13, wherein after the step (f), a gate insulating film is formed in an active region of the semiconductor substrate surrounded by the trench-shaped isolation portion. Forming a semiconductor device, forming a gate electrode on the gate insulating film, and forming source and drain semiconductor regions on the semiconductor substrate. 18. A method of manufacturing a semiconductor device, comprising the following steps: (a) forming a groove in a main surface of a semiconductor substrate; and (b) high-density plasma on the main surface of the semiconductor substrate. Depositing an insulating film by chemical vapor deposition, (c) forming an insulating film on the insulating film;
Forming a masking pattern such that the relatively large protrusions formed on the upper surface of the insulating film are exposed and the other portions are covered, (d) the insulating film exposed therefrom using the masking pattern as a mask (E) removing the masking pattern, (f) polishing the insulating film so that the insulating film after the (e) step is left in the groove, Forming a groove-shaped separation portion on the main surface of the semiconductor substrate.