JP2002359549A - Signal transmission circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To effectively suppress a jamming means from jamming other circuit in a system for transmitting/receiving transmission signals through a signal transfer means, between a master and slave transmission signal transmitting/ receiving means and set the answer signal level from the child transmission signal transmitting/receiving means to levels L, H sufficiently for from the input dead zone of the parent transmission signal transmitting/receiving means. SOLUTION: Upon the generation of a answer signal from the slave transmission signal transmitting/receiving means an output transistor of the master transmission signal transmitting/receiving means is operated to always accurately transmit a transmission signal, irrespective of the value of jamming suppression resistance inserted in the associated transmission lines. The circuit allows the value of the jamming suppression resistance to be selected, so as to accurately transmit the transmission signal and avoid input dead zones of other input ports.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parent transmission signal transmitting / receiving means such as a circuit or device for actively transmitting and receiving a transmission signal, and a child transmission of a circuit or device for passively receiving and transmitting a transmission signal. It relates to a signal transmission circuit that transmits a transmission signal to and from the signal transmission / reception means, and is particularly necessary for the response signal from the child transmission signal transmission / reception means while suppressing the transmission signal from interfering with other circuits. The present invention relates to a signal transmission circuit improved to ensure a proper level.

[0002]

2. Description of the Related Art FIG. 7 shows an example of a conventional signal transmission circuit, and FIG. 8 is an operation waveform diagram showing the level and timing of a signal transmitted by the signal transmission circuit.

[0003] This conventional signal transmission circuit will be described. First, normally, the parent transmission signal transmission / reception means (sending IC)
1 is off, and the input / output port 4 on the sending side is open.
The A input / output port 10 of the (receiving IC (A)) 11 and the B input / output port 14 of the child transmission signal transmitting / receiving means B (receiving IC (B)) 15 are connected to the pull-up resistor 7 to the power supply Vcc 6.
As a result, as shown in FIG. 7, the power supply voltage is Vcc16. Here, the sending IC 1 sends the transmission signal (L signal) 1 of FIG. 7 to the receiving IC (A) 11 and the receiving IC (B) 15.
When the signal 7 is transmitted, the output transistor 3 of the transmission-side IC 1 is turned on, so that the transmission-side input / output port 4 becomes L level.
Therefore, the transmission signal (L signal) 17 is transmitted to the A input / output port 10 of the receiving IC (A) 11 and the B input / output port 14 of the receiving IC (B) 15. Next, the receiving IC
(A) When the response signal (Lm signal) 18 shown in FIG.
When the output transistor 3 of C1 is turned off, the input wait state is set, the A output transistor 13 of the receiving IC (A) 11 is turned on, and the response signal (Lm signal) 18 is transmitted to the sending input / output port 4. Also, this signal is output to the receiving IC
(B) It is also transmitted to the B input port 14 of 15. At this time, as shown in FIG. 7, the response signal (Lm signal) 18 is caused by the influence of the interference suppression resistor 9 inserted into this transmission line in consideration of other disturbed signals affected by these transmitted signals. Level rises without completely dropping to 0V. Depending on the level of interference, it is necessary to insert a considerably large resistance value.
The L level must be prevented from floating up to the input insensitive area 19 of the input / output port such as the B input / output port 14 of the receiver IC (B) 15. In any case, the resistance of the interference suppression resistor 9 must be reduced to some extent.

[0004]

The conventional signal transmission circuit is designed to secure the level of the response signal transmitted from the child transmission signal transmission / reception means 11 to other disturbed signals affected by the transmitted signal. In consideration of the above, the value of the interference suppression resistor inserted into the transmission line must be reduced to some extent, and there are cases where the interference cannot be sufficiently suppressed.

[0005]

In the signal transmission circuit of the present invention, the resistance value of the interference suppression means is made larger to sufficiently suppress interference with other circuits, and furthermore, the signal transmitted from the child transmission signal transmission / reception means. It is an object of the present invention to provide an improved signal transmission circuit that can provide a reliable L level, a reliable H level, or a high level close to the response signal.

[0006]

SUMMARY OF THE INVENTION A signal transmission circuit according to the present invention has a parent transmission signal transmitting / receiving means having an output transistor for actively transmitting or receiving a signal, and transmitting a transmission signal from the parent transmission signal transmitting / receiving means. Transmission signal transmitting means for transmitting, transmitting and receiving a transmission signal from the parent transmission signal transmitting and receiving means through the transmission signal transmitting means, and a child transmission signal transmitting and receiving means for passively receiving or transmitting the transmission signal. A transmission signal disturbance suppression means provided in the signal transmission means; and a transmission signal control means for controlling the parent transmission signal transmission / reception means, wherein the transmission signal control means controls an output transistor of the parent transmission signal transmission / reception means. Thus, a reliable low level is ensured in the response signal from the child transmission signal transmitting / receiving means.

In the signal transmission circuit according to the present invention, when a response signal is generated from the child transmission signal transmission / reception means, the transmission signal control means turns on a low-level output transistor of the parent transmission signal transmission / reception means. , And the response signal is given a reliable low level.

The signal transmission circuit according to the present invention has a parent transmission signal transmitting / receiving means having an output transistor for actively transmitting or receiving a signal, and a transmission signal transmitting means for transmitting a transmission signal from the parent transmission signal transmitting / receiving means. Means, a child transmission signal transmitting / receiving means for passively receiving or transmitting a transmission signal from the parent transmission signal transmitting / receiving means through the transmission signal transmitting means, and a transmission signal transmitting means for suppressing interference by the transmission signal. The transmission signal interference suppression means provided, and transmission signal control means for controlling the parent transmission signal transmission / reception means, wherein the transmission signal control means controls an output transistor of the parent transmission signal transmission / reception means, A characteristic feature is to ensure a high level in the response signal from the transmission signal transmitting / receiving means.

In the signal transmission circuit according to the present invention, when a response signal is generated from the child transmission signal transmitting / receiving means, the transmission signal control means turns on a high-level output transistor of the parent transmission signal transmitting / receiving means. , And the response signal is given a reliable high level.

In addition, a signal transmission circuit according to the present invention has a parent transmission signal transmitting / receiving means having an output transistor for actively transmitting or receiving a signal, and a transmission signal transmitting means for transmitting a transmission signal from the parent transmission signal transmitting / receiving means. Means, a child transmission signal transmitting / receiving means for passively receiving or transmitting a transmission signal from the parent transmission signal transmitting / receiving means through the transmission signal transmitting means, and a transmission signal transmitting means for suppressing interference by the transmission signal. Provided transmission signal disturbance suppression means, and transmission signal control means for controlling the master transmission signal transmission / reception means, and for a response signal from the child transmission signal transmission / reception means, the suppression value of the transmission signal disturbance suppression means. By selection, a high level higher than the input dead area of the parent transmission signal transmitting / receiving means is secured.

Further, the signal transmission circuit according to the present invention reduces the suppression value of the transmission signal interference suppression means when a response signal is generated from the slave transmission signal transmission / reception means, thereby reducing the response signal to the response signal. A high level higher than the input dead area of the parent transmission signal transmitting / receiving means is provided.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 Hereinafter, embodiments of a signal transmission circuit according to the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing Embodiment 1 of a signal transmission circuit according to the present invention. Also, FIG.
FIG. 2 is an operation waveform diagram showing a transmission signal level and operation timing by the signal transmission circuit of FIG. 1.

First, the signal transmission circuit shown in FIG. 1 includes one parent transmission signal transmitting / receiving means (sending IC) 20, two child transmission signal transmitting / receiving means (receiving ICs) 30, 40, and a A bidirectional transmission signal transmitting means 50 is included.

The sending side IC 20 has an input circuit 21 and a pair of output transistors 22 and 23, and the input circuit 21 is connected to an input / output port 24. The high-level output transistor 22 is, for example, a PNP-type bipolar transistor having an emitter connected to the power supply terminal 25. The low output transistor 23 is, for example, an NPN type bipolar transistor whose emitter is connected to the ground. The collectors of the output transistors 22 and 23 are both input / output ports 21
It is connected to the.

The transmission signal control means 27
Is provided to control the The transmission signal control means 27 controls generation of a transmission signal in the transmission side IC 20 and also controls output transistors 22 and 23.

The receiving IC (A) 30 has an input circuit 31 and an output transistor 33 on the low level side.
1 is connected to the A input / output port 34. The output transistor 33 is, for example, an NPN bipolar transistor, and has a collector connected to the A input / output port 34 and an emitter connected to the ground. Receiving IC (B) 40
Has an input circuit 41, which is connected to a B input / output port 42.

The bidirectional transmission signal transmission means 50 is a bidirectional signal transmission line 5 connecting the input / output ports 24, 34, 42.
1, the signal transmission line 51 is provided with an interference suppression resistor 53 constituting an interference suppression means.
The disturbance suppression resistor 53 is commonly inserted between the input / output ports 24 and 34 and between the input / output ports 34 and 42. The interference suppression resistor 53 is provided to suppress a signal transmitted through the signal transmission line 51 from interfering with other circuits. The power supply Vcc55
Are connected to the signal transmission line 51 via the pull-up resistor 56 and are also connected to the power supply terminal 25 of the sending side IC 20.

Next, this operation will be described. First,
In the bidirectional signal transmission circuit as shown in FIG. 1, the output transistors 22 and 23 of the transmission side IC 20 are normally off and the transmission side input / output port 24 is also in an open state. Output port 34 and receiving IC
(B) The B input / output port 42 is connected to the power supply voltage Vc shown in FIG.
c60. Here, the sending side IC 20 is the receiving side I
When transmitting the transmission signal (L signal) 61 of FIG. 2 to the C (A) 30 and the receiving IC (B) 40, the output transistor 23 of the transmitting IC 20 is turned on, so that the transmitting input / output port 24
Becomes L level, and a transmission signal (L signal) 61 is generated. Therefore, the A input / output port 34 of the receiving IC (A) 30
The transmission signal 61 is transmitted to the B input / output port 42 of the receiving IC (B) 40. The interference suppression resistor 53 acts on the transmission signal 61 to suppress the interference so that the transmission signal 61 does not interfere with other circuits.

Next, the receiving-side IC (A) 30 sends, for example, to the sending-side input / output port 24 from the previously input transmission signal (L signal) 61 of FIG.
When the response signal (Lm signal) 62 is sent back after elapse, the output transistor 33 is turned on. At the same time, the output transistor 23 of the sending IC 20 is turned on by the transmission signal control means 27 and the output transistor 22 is turned on.
Is controlled to be turned off. That is, in the first embodiment of the present invention, the receiving IC (A) 30
From the transmission signal 61 of FIG. 2 previously transmitted to the input / output port 24 of C20, it is understood that the response signal 62 is always returned after a predetermined delay time t has elapsed. Using the transmission signal 61, the delay time t
After the time elapses, the transmission signal control circuit 27 controls the output transistor 23 to be turned on and the output transistor 22 to be turned off.

Based on the operation of the output transistors 22 and 23, the response signal which should float at the halfway level 63 shown by the dotted line in FIG. The B input / output port 42 of B) is transmitted as a complete L level signal 62 of 0 volt, and the response signal 62
It is possible to reliably avoid a situation in which the input IC 20 and the receiving IC (B) float up to the input insensitive area range 64. In this case, it is assumed that a bidirectional transmission path is used, but it is assumed that the transmission timing of the transmission-side input / output port 24 is designed so that a response to the complete L level 62 can be ignored without any problem.

In the first embodiment of the present invention, the IC
Although they are used for transmission between each other, they may be used between circuits or between devices. In addition, the output transistors 22 and 23 are not limited to bipolar transistors that control on / off, and the output transistors 22 and 23 may be used as FETs. Of course, it may be turned on and off. Further, in such a bidirectional transmission path, a larger number of circuits and ICs may be connected.

Embodiment 2 FIG. FIG. 3 is a block diagram showing a circuit configuration of a signal transmission circuit according to a second embodiment of the present invention, and FIG. 4 is an operation waveform diagram showing a transmission signal level and operation timing according to the second embodiment.
In the third embodiment, the receiving-side IC (A) 30 is provided with the high-level PNP output transistor 32 and the power supply terminal 35 connected to the Vcc power supply 55, and the emitter of the output transistor 32 is connected to the power supply terminal. At 35, the collectors are connected to input / output ports 34, respectively. Other circuit configurations are the same as those in FIG.

The operation of the second embodiment will be described. First, in the bidirectional transmission circuit of FIG. 1, since the output transistors 22 and 23 of the sending side IC 20 are normally off and the sending side input / output port 24 is open, the A / O input / output of the receiving side IC (A) 30 Port 34 and receiving IC
(B) The B input / output port 42 is connected to the power supply voltage Vcc shown in FIG.
It is 60. Here, the sending IC 20 is the receiving IC.
When transmitting the transmission signal (L signal) 61 shown in FIG. 4 to the (A) 30 and the receiving IC (B) 40, the output transistor 23 of the transmitting IC 20 is turned on, so that the transmitting output port 24
Becomes L level. Therefore, this transmission signal (L signal) 61 is transmitted to the A input / output port 34 of the receiving IC (A) 30 and the B input / output port 42 of the receiving IC (B) 40. In response to the transmission signal 61, the interference suppression resistance 53 is connected to the transmission signal 6
1 acts to suppress interference so as not to interfere with other circuits.

Next, the receiving-side IC (A) 30 receives a predetermined delay time t from the transmission signal (L signal) 61 of FIG.
, When the response signal (Hm signal) 65 is sent back, the high-level output transistor 32 is turned on,
The low-level output transistor 33 is turned off, and at the same time, the transmission signal control means 27 turns on the output transistor 22 of the sending-side IC 20 and the output transistor 23
Is controlled to be turned off. That is, in the second embodiment of the present invention, the receiving IC (A) 30 transmits a predetermined delay to the input / output port 24 of the sending IC 20 from the previously transmitted transmission signal 61 of FIG. It is known that the response signal 65 is always sent back after the time t has elapsed, and the transmission signal control circuit 27 turns on the output transistor 22 by the transmission signal control circuit 27 after the delay time t has elapsed from the transmission signal 61. 23 is turned off.

On the basis of the operation of the output transistors 22 and 23, there is a danger of the danger of entering the input insensitive area 64 of the sending side IC (A) 20 and the receiving side IC (B) 40 indicated by a dotted line in FIG. A certain response signal 65 is Vc
The signal is transmitted as the c-level complete H-level signal 65, so that it is possible to reliably prevent the response signal 65 from floating up to the input insensitive area range 64 for the sending IC 20 and the receiving IC (B). be able to. In addition,
In this case, it is assumed that a bidirectional transmission path is used, but it is assumed that the transmission timing of the transmission-side input / output port 24 is designed so that a response to the complete L level 65 can be ignored even if it is ignored.

In the second embodiment of the present invention, the IC
Although they are used for transmission between each other, they may be used between circuits or devices, and the output transistors 22, 23, 32,
33 is not limited to a bipolar transistor whose on / off is controlled.
Needless to say, FETs 2 and 33 may be turned on and off. Further, in such a bidirectional transmission path, a larger number of circuits and ICs may be connected.

Embodiment 3 FIG. 5 is a block diagram showing a circuit configuration of a third embodiment according to the present invention, and FIG. 6 is an operation waveform diagram showing a transmission signal level and operation timing according to the third embodiment.

In the third embodiment, the short-circuit switch 53a is connected in parallel with a part of the resistance to the interference suppression resistance 53.
The short-circuit switch 53a is controlled by, for example, the transmission signal control means 27.
(B) The short circuit switch 53a can be turned on and off by control means for controlling the output transistors 32 and 33 of 30. This short-circuit switch 53a is constituted by a bipolar transistor and an FET. The other circuit configuration is the same as the circuit configuration of FIG.

The operation of the third embodiment will be described. First, in the bidirectional transmission circuit of FIG. 4, the output transistors 22 and 23 of the sending side IC 20 are normally off and the sending side input / output port 24 is also in the open state. Port 34 and receiving IC
(B) The B input / output port 42 is connected to the power supply voltage Vcc shown in FIG.
It is 60. Here, the sending IC 20 is the receiving IC.
When transmitting the transmission signal (L signal) 61 shown in FIG. 6 to the (A) 30 and the receiving IC (B) 40, the output transistor 23 of the transmitting IC 20 is turned on, so that the transmitting input / output port 24 is set to the L level. Level. Therefore, the transmission signal (L signal) 61 is transmitted to the A input / output port 34 of the receiving IC (A) 30 and the B input / output port 42 of the receiving IC (B) 40.
The interference suppression resistor 53 acts on the transmission signal 61 to suppress the interference so that the transmission signal 61 does not interfere with other circuits. At the time of transmitting the transmission signal, the short-circuit switch 53a is turned off, and the suppression resistance value of the interference suppression resistor 53 maintains a large value.

Next, the receiving-side IC (A) 30 sends a predetermined delay time t to the sending-side input / output port 24 from the transmission signal (L signal) 61 of FIG.
When the response signal (Hm signal) 66 is sent back after elapse of the time, the output transistor 32 of the receiving IC (A) is turned on and the output transistor 33 is turned off. 53a is turned on. That is, in Embodiment 3 of the present invention,
The receiver IC (A) 30 sends the response signal 66 to the input / output port 24 of the transmitter IC 20 after a predetermined delay time t has elapsed from the previously transmitted transmission signal 61 of FIG. Taking advantage of the fact that the transmission signal is always returned, the short-circuit switch 53a is turned on by the transmission signal control circuit 27 after the elapse of the delay time t from the transmission signal 61, and the resistance value of the interference suppression resistor 53 is reduced.

Based on the ON operation of the short-circuit switch 53a, the response signal 66 is changed by the disturbance suppression resistor 53 to the state shown in FIG.
The sending side IC 20 and the receiving side IC (B) 4 indicated by dotted lines in FIG.
0, the input / output port 24 and the receiving-side IC have an approximate H level exceeding the input dead area 64 and closer to the Vcc level 60 as shown by the solid line in FIG. The response signal 66 is transmitted to the B input / output port 42 of FIG.
And input insensitive area range 64 for receiving IC (B)
It is possible to reliably avoid the situation that the object floats on the surface. In this case, it is assumed that a bidirectional transmission path is used. However, it is assumed that the transmission timing of the transmission-side input / output port 24 is set such that a response to the complete L level 65 can be ignored without any problem.

In the third embodiment of the present invention, the IC
Although they are used for transmission between each other, they may be used between circuits or devices, and the output transistors 22, 23, 32,
33 is not limited to a bipolar transistor whose on / off is controlled.
Needless to say, FETs 2 and 33 may be turned on and off. Further, in such a bidirectional transmission path, a larger number of circuits and ICs may be connected.

[0033]

As described above, according to the present invention, the transmission signal control means controls the output transistor of the parent transmission signal transmission / reception means so that the response signal from the child transmission signal transmission / reception means can be reliably output at a low level, a high level or a low level. A high level exceeding the input dead area of the parent transmission signal transmission / reception means is ensured, the interference is small, and the response signal does not enter the input dead area of the parent transmission signal transmission / reception means, and the parent transmission is ensured. It can be transmitted to the signal transmitting / receiving means.

Further, the transmission signal control means turns on the low-level or high-level output transistor of the parent transmission signal transmission / reception means when a response signal is generated from the child transmission signal transmission / reception means, so that the response signal can be reliably output. In the case of providing a low level or a high level, it is possible to easily and surely provide a low level or a high level to the response signal by controlling the output transistor of the parent transmission signal transmitting / receiving means.

Further, when the response signal from the child transmission signal transmitting / receiving means is generated, the suppression value of the transmission signal interference suppressing means is reduced, so that the response signal can be set to a high level exceeding the input insensitive area of the parent transmission signal transmitting / receiving means. In what gives
The transmission signal from the master transmission signal transmission / reception means can be reliably provided with a high level exceeding the dead zone while reliably suppressing the interference.

[Brief description of the drawings]

FIG. 1 is a first embodiment of a signal transmission circuit according to the present invention;
2 is a block diagram showing the circuit configuration of FIG.

FIG. 2 is a first embodiment of a signal transmission circuit according to the present invention;
3 is an operation waveform diagram of FIG.

FIG. 3 is a second embodiment of a signal transmission circuit according to the present invention;
2 is a block diagram showing the circuit configuration of FIG.

FIG. 4 is a second embodiment of a signal transmission circuit according to the present invention;
3 is an operation waveform diagram of FIG.

FIG. 5 is a third embodiment of a signal transmission circuit according to the present invention;
2 is a block diagram showing the circuit configuration of FIG.

FIG. 6 is a third embodiment of a signal transmission circuit according to the present invention;
3 is an operation waveform diagram of FIG.

FIG. 7 is a block diagram of a conventional signal transmission circuit.

FIG. 8 is an operation waveform diagram of a conventional signal transmission circuit.

[Explanation of symbols]

Reference Signs List 20 parent transmission signal transmission / reception means 22 high level side output transistor 23 low level side output transistor 24 input / output port 27 transmission signal control means 30, 40 child transmission signal transmission / reception means 32, 33 output transistor 34, 42 input / output port 50 transmission signal transmission Means 51 Signal transmission line 53 Transmission signal disturbance suppression means 53a Short-circuit switch 61 Transmission signal 62, 65, 66 Response signal 64 Input dead zone

Claims (6)

[Claims] 1. A parent transmission signal transmitting / receiving means having an output transistor for actively transmitting or receiving a signal, a transmission signal transmitting means for transmitting a transmission signal from the parent transmission signal transmitting / receiving means, and the transmission signal transmitting means A child transmission signal transmitting / receiving means for passively receiving or transmitting a transmission signal from the parent transmission signal transmitting / receiving means, and a transmission signal interference suppressing means provided in the transmission signal transmitting means for suppressing interference by the transmission signal And a transmission signal control means for controlling the parent transmission signal transmission / reception means, wherein the transmission signal control means controls an output transistor of the parent transmission signal transmission / reception means, whereby a response signal from the child transmission signal transmission / reception means is provided. A signal transmission circuit characterized by ensuring a reliable low level. 2. When a response signal is generated from said child transmission signal transmitting / receiving means, said transmission signal control means turns on an output transistor on a low level side of said parent transmission signal transmitting / receiving means, so that said response signal can be sent to a low level reliably. 2. The signal transmission circuit according to claim 1, wherein a level is given. 3. A parent transmission signal transmission / reception unit having an output transistor for actively transmitting or receiving a signal, a transmission signal transmission unit for transmitting a transmission signal from the parent transmission signal transmission / reception unit, and the transmission signal transmission unit A child transmission signal transmitting / receiving means for passively receiving or transmitting a transmission signal from the parent transmission signal transmitting / receiving means, and a transmission signal interference suppressing means provided in the transmission signal transmitting means for suppressing interference by the transmission signal And a transmission signal control means for controlling the parent transmission signal transmission / reception means, wherein the transmission signal control means controls an output transistor of the parent transmission signal transmission / reception means, whereby a response signal from the child transmission signal transmission / reception means is provided. A signal transmission circuit characterized by ensuring a reliable high level. 4. When a response signal is generated from said child transmission signal transmission / reception means, said transmission signal control means turns on an output transistor on a high level side of said parent transmission signal transmission / reception means, so that said response signal has a high level. 4. The signal transmission circuit according to claim 3, wherein a level is given. 5. A transmission signal transmitting / receiving means having an output transistor for actively transmitting or receiving a signal, a transmission signal transmitting means for transmitting a transmission signal from the parent transmission signal transmitting / receiving means, and the transmission signal transmitting means. A child transmission signal transmitting / receiving means for passively receiving or transmitting a transmission signal from the parent transmission signal transmitting / receiving means, and a transmission signal interference suppressing means provided in the transmission signal transmitting means for suppressing interference by the transmission signal And transmission signal control means for controlling the parent transmission signal transmission / reception means, and selecting a suppression value of transmission signal disturbance suppression means for a response signal from the child transmission signal transmission / reception means, A signal transmission circuit characterized by securing a high level higher than an input dead area of a signal transmission / reception means. 6. An input insensitive area of said parent transmission signal transmitting / receiving means with respect to said response signal by reducing a suppression value of said transmission signal disturbance suppressing means when a response signal is generated from said child transmission signal transmitting / receiving means. 6. The signal transmission circuit according to claim 5, wherein said high level is provided.