JP2002358793A - Sample-and-hold circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a sample-and-hold circuit in which clock field through can be reduced with simple constitution and which can be operated normally even if power source voltage is raised more than gate break down strength. SOLUTION: A sample-and-hold circuit 1 is inserted between an input terminal 2 and an output terminal 3 through buffers 4, 5. first and second switching elements 6, 7 comprising of N channel MOSFET are connected in series, a source of the switching element 6 is connected to a node N1 of a capacitor 8 for holding, a drain is connected to a drain of the switching element 7. sources and drains of the switching elements 6, 7 are connected respectively a body diode DB, the node N1 is connected to a well W1 of the switching element 6. Gates of the switching elements 6, 7 are connected to voltage Vg1 at the time of sampling and connected to voltage sources 10, 12 in which voltage Vg0 is generated at the time of holding. But, Vth is threshold voltage of the MOSFET and Vg1 >Vth >Vg0 .

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a sample and hold circuit, and more particularly to a sample and hold circuit using a MOS transistor as a switching element and having a holding capacitor connected between an output terminal and a ground terminal. .

[0002]

2. Description of the Related Art In a sample and hold circuit of this type, ideally, the voltage of the hold capacitor becomes equal to the input voltage when the switching element is on, and the voltage of the hold capacitor is switched when the switching element is off. The value before the element is turned off is maintained.

FIG. 10 is a schematic diagram of a sample-and-hold circuit using an N-channel MOS transistor as a switching element when the switching element is on. The switching element 51 is configured to switch a gate signal by a signal of V _DD (power supply voltage) and a signal of V _SS (GND: ground). When the switching element 51 is in the ON state, FIG.
As shown in (1), a negative charge (shown by a white circle) exists in the inversion channel layer immediately below the gate G. Then, when the switching element 51 is turned off, the charge flows out from the terminals of the source S and the drain D, and charge injection occurs. Therefore, the amount of charge stored in the hold capacitor 52 changes, and an error occurs in the hold voltage. The voltage ΔV _A of the error (fluctuation) is expressed by the following equation.

ΔV _A = C _OX W (L−2L _D ) (V _GS −V _TH ) / (2C _HOLD ) (1) where C _OX : oxide film capacity per unit area (fF / μm)
² ) W: Gate width (μm), L: Gate length (μm) L _D : Overlap length between gate, drain and source V _GS : Gate-source voltage (V), V _TH : MOSFE
T threshold voltage C _HOLD : hold capacitor capacity (fF) In this circuit, the gate voltage becomes D _DD at the time of sampling. Therefore, the gate-source voltage V _GS is V _GS = −V _IN
The fluctuation voltage ΔV _A of the hold terminal due to charge injection increases as V _IN decreases. Here, V _IN indicates the voltage of the sample signal.

In a MOS transistor, a capacitance exists between a gate and a source and between a gate and a drain due to an overlap between a gate and a source and a drain. Then, when the change in the gate voltage of the switching element is turned off due to the capacitance coupling between the gate and the source and between the gate and the drain, the voltage of the input terminal and the output terminal changes. This phenomenon is called capacitive field-through. The voltage ΔV _B that appears as an error at the hold terminal due to this capacitive field-through becomes a value obtained by dividing the amount of change in the gate signal by the overlap capacitance C _OL and the hold capacitor capacitance C _HOLD . In the above circuit, the gate signal has the potential of D _DD at the time of sampling and the potential of V _SS at the time of holding, so that the voltage Δ
V _B is represented by the following equation.

ΔV _B = −C _OL (D _DD −V _SS ) / (C _OL + C _HOLD ) (2) Since the ΔV _A and ΔV _B appear as errors in the hold terminal, the error voltage appearing in the hold terminal ΔV _HOLD
Becomes ΔV _HOLD = ΔV _A + ΔV _B.

[0007] The charge injection and the capacitive field-through are performed by the switching element 5.
The clock field through causes the amount of charge stored in the hold capacitor to fluctuate in accordance with the on / off of 1.

Japanese Patent Application Laid-Open No. 6-349294 proposes a sample-hold circuit provided with a compensation transistor in order to prevent a change in the holding voltage of a holding capacitor due to capacitive field-through. As shown in FIG. 11, this circuit includes MOS transistors 55, 56, 57, between input terminal 53 and output terminal 54.
An analog switch Sa having a parallel connection of the 58 and a compensation transistor Tc having a source and a drain short-circuited while connecting the MOS transistors 59 and 60 in parallel. MOS transistors 55, 56 and 59 have N
A P-type MOS transistor is used for the MOS transistors 57, 58, and 60. The input side of the compensation transistor Tc is connected to the output side of the analog switch Sa, and the compensation transistor Tc
Is connected to a hold capacitor 61. Each of the MOS transistors 55 to 60 has the same size.

In this circuit, the capacitance (stray capacitance) between the gate and source and between the gate and drain of the analog switch Sa is equal to the capacitance (stray capacitance) between the gate and source and between the gate and drain of the compensation transistor Tc. . As a result, when the analog switch Sa is turned off from on, the potential difference between the two stray capacitances acts so as to cancel each other out, thereby preventing the occurrence of capacitive field-through.

[0010]

In the conventional sample and hold circuit, since the power supply voltage is applied to the gate of the MOS transistor, the power supply voltage increases, and the MO
If the voltage exceeds the gate breakdown voltage of the S transistor, the sample and hold circuit cannot be realized. If a MOS transistor having a thick gate oxide film is used to increase the gate breakdown voltage, the manufacturing cost increases.

Further, as the range of the input signal becomes wider, the amplitude of the gate drive signal of the MOS transistor becomes larger, and the error voltage ΔV _HOLD (= ΔV _A + ΔV _B ) becomes larger.

In order to improve the accuracy of the sample-and-hold circuit, it is necessary to reduce the error voltage ΔV _HOLD (= ΔV _A + ΔV _B ) and to improve the droop rate. JP-A-6-3
In the sample and hold circuit disclosed in Japanese Patent No. 49294, occurrence of capacitive field-through, that is, Δ
It is possible to make V _B zero, but the structure becomes complicated. Further, at a higher gate breakdown voltage after the supply voltage is high, it is not considered to reduce the problems and [Delta] V _A of the sample-and-hold circuit can not be realized.
Also, no consideration has been given to improving the droop plate.

The present invention has been made in view of the above-mentioned problems, and a first object of the present invention is to reduce a clock field through with a simple configuration and to provide a first MOS transistor connected to a holding capacitor. To provide a sample-and-hold circuit that can reduce the amplitude of the gate signal. A second object is to provide a sample-and-hold circuit that can be used in a circuit whose power supply voltage is equal to or higher than the gate breakdown voltage of a switching element. A third object is to provide a sample and hold circuit capable of further improving the droop rate.

[0014]

In order to achieve the first object, according to the first aspect of the present invention, a MOS transistor is used as a switching element between an input terminal and an output terminal, and an output terminal is provided. And a holding capacitor connected between the terminal and a ground terminal, wherein the first capacitor is connected to the potential of the holding capacitor.
A well potential of the S transistor is adjusted, and a voltage higher than the threshold of the first MOS transistor is generated at the gate of the MOS transistor at the time of sampling and the threshold of the first MOS transistor at the time of holding, based on the well potential. A second MOS transistor connected to a voltage source for generating a lower voltage and preventing a current from flowing through the body diode of the first MOS transistor during a hold;
A transistor is provided on the input terminal side of the first MOS transistor, generates a voltage higher than the threshold value of the second MOS transistor during sampling, and generates a voltage lower than the threshold value of the second MOS transistor during holding. A source is connected to the gate of the second MOS transistor.

According to the present invention, the well potential of the first MOS transistor is adjusted to the potential of the hold capacitor, and a voltage source for driving the MOS transistor based on the potential is provided. Therefore, the first M
The amplitude of the gate signal of the OS transistor can be reduced, and the power supply voltage is not directly applied to the gate of the first MOS transistor. Therefore, charge injection and capacitive field-through that occur when the first MOS transistor that is a switching element is turned off can be reduced.

According to a second aspect of the present invention, in the first aspect of the present invention, the well potential of the second MOS transistor for preventing a current from flowing through the body diode of the first MOS transistor during a hold is set. At the time of sampling, the second M
A voltage source that generates a voltage higher than the threshold value of the OS transistor and generates a voltage lower than the threshold value of the second MOS transistor during holding is connected to the gate of the second MOS transistor.

According to the present invention, the first MOS transistor is held at the time of holding.
The well potential of the second MOS transistor for preventing a current from flowing through the body diode of the transistor is adjusted to the voltage on the input terminal side, and the MOS transistor is driven based on this potential.

In order to achieve the second object, according to the invention described in claim 3, in the invention described in claim 1 or claim 2, each of the voltage sources is a system different from a power supply voltage, and
It is configured so that a voltage lower than the gate breakdown voltage of the S transistor can be applied. According to the present invention, the power supply voltage D _DD is not applied to the gate of each MOS transistor, a voltage higher than the threshold value of each MOS transistor is supplied from another voltage source at the time of sampling, and a voltage lower than the threshold value of each MOS transistor is held at the time of holding. Supplied. Therefore, even if the power supply voltage becomes higher than the gate breakdown voltage, an appropriate voltage less than the gate breakdown voltage is supplied to the gate of each MOS transistor, and the switching element is driven without any trouble.

According to a fourth aspect of the present invention, in order to achieve the third object, in the invention according to any one of the first to third aspects, a plurality of the switching elements are connected in series. One MOS transistor is connected to the node of the holding capacitor at the source or drain, and holds the well potential of the MOS transistor closer to the potential of the holding capacitor on the input side than the first MOS transistor. And a capacitor connected to the first M capacitor at a node of the capacitor.
The well of the OS transistor is connected.

According to the present invention, the well potential of the MOS transistor is maintained at a value close to the potential of the hold capacitor by a capacitor different from the hold capacitor provided on the input terminal side of the first MOS transistor. Therefore, the node of the hold capacitor is MO
Since the well of the S transistor is not connected and only the source or the drain is connected, the leak current from the node of the holding capacitor can be reduced, and the droop rate can be reduced.

According to a fifth aspect of the present invention, in the fourth aspect of the invention, the first MOS transistor is provided on the input side, and the well potential of the MOS transistor is set to a value close to the potential of the holding capacitor. The capacitance between the well of the MOS transistor and the substrate is used as a capacitor for holding the capacitor.

In the present invention, since the capacity between the well of the MOS transistor and the substrate is used as a capacitor for holding the well potential of the first MOS transistor at a value close to the potential of the holding capacitor, the capacitor is used. There is no need to separately provide such a structure, and the structure is simplified.

According to the present invention, the switching element is inserted between the input terminal and the output terminal, and
A sample and hold circuit using an S transistor and having a holding capacitor connected between an output terminal and a ground terminal, wherein two MOS transistors are provided in series between the holding capacitor and the input terminal. A voltage higher than a threshold value of the first MOS transistor is generated at the time of sampling, based on a well potential, at a gate of the first MOS transistor connected to the holding capacitor side, and the first MOS transistor is connected at the time of holding. A voltage source for generating a voltage lower than the threshold value of the MOS transistor is connected;
The gate of a second MOS transistor provided on the input side for preventing a current from flowing through the body diode of the first MOS transistor at the time of holding,
Based on the well potential, the second MO
A well driving amplifier for generating a voltage higher than the threshold value of the S transistor and generating a voltage lower than the threshold value of the second MOS transistor during a hold, and supplying a well potential of the first MOS transistor; At least one of a well driving amplifier for supplying a well potential of the second MOS transistor is provided.

According to the present invention, the amplitudes of the gate signals of the first and second MOS transistors can be reduced,
It can be used without difficulty in a circuit whose power supply voltage is higher than the gate breakdown voltage of the switching element. Further, the well potential can be used lower than the inventions of claims 1 to 4. The well potential of at least one of the two MOS transistors provided in series between the holding capacitor and the input terminal is supplied by a well driving amplifier. Since the well of the MOS transistor is not connected to the node of the hold capacitor but only the source or drain is connected, the leak current from the node of the hold capacitor can be reduced, and the droop rate can be reduced.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) A first embodiment of the present invention will be described below with reference to FIGS.

As shown in FIG. 1, the sample-and-hold circuit 1 includes a buffer 4 and a buffer 4 between an input terminal 2 and an output terminal 3.
5 is inserted. Sample hold circuit 1
Has first and second switching elements 6 and 7 connected in series, and MOS transistors are used as both switching elements. In this embodiment, an N-channel MOSFET formed on an n-type silicon substrate
Is used. The holding capacitor 8 has a node (one end) N1 connected to the non-inverting input terminal of the output buffer 5, and the other end connected to the ground terminal 9. FIG. 2 is a schematic sectional view of both switching elements 6 and 7.

The first switching element 6 has a source connected to the node N1 of the holding capacitor 8, and a drain connected to the drain of the second switching element 7. The source and the drain of the first switching element 6 are connected via a body diode Db (shown in FIG. 1) whose cathode is on the drain side. The node N1 of the hold capacitor 8 is connected to the well W1 of the first switching element 6. A voltage source 10 is connected between the gate of the first switching element 6 and the output side of the buffer 5. The voltage source 10 is configured to generate a voltage V _g1 during sampling and a voltage V _g0 during holding. However, when V _th is the threshold voltage of the MOSFET, the relationship is set as V _g1 > V _th > V _g0 .

The well W2 of the second switching element 7 is connected to the ground terminal 9. A voltage source 11 is connected between the gate of the second switching element 7 and the ground terminal 9. The voltage source 11 is configured to generate a power supply voltage Vcc during sampling and a voltage of 0 V during holding.

Next, the operation of the sample and hold circuit 1 configured as described above will be described. At the time of sampling, both switching elements 6 and 7 are turned on, and the input terminal 2
Is output from the buffer 5 and the hold capacitor 8
Is charged to have a voltage equal to the input voltage Vi.
When both the switching elements 6 and 7 are turned off during the hold, the holding capacitor 8 becomes the switching elements 6 and 7
Hold a voltage equal to the input voltage Vi immediately before turning off.

The well potential of the switching element 6 is adjusted to the potential of the hold capacitor 8, the source is connected to the node N1 of the hold capacitor 8, and the gate voltage is generated based on the potential of the hold capacitor. Because of this, the voltage amplitude of the gate signal can be reduced. Therefore, when the switching element 6 is turned off, in the on state of the switching element 6, the negative charge existing in the inversion channel layer immediately below the gate does not easily flow out of the source terminal to the holding capacitor 8 side. Further, when the potential of the input signal side becomes lower than the potential of the hold capacitor 8 during the hold, current tends to flow from the hold capacitor 8 to the input side via the body diode Db. When this current occurs, the potential of the hold capacitor 8 changes. However, since the second switching element 7 is connected to the first switching element 6 and the second switching element 7 is kept in the off state, a current flows from the holding capacitor 8 via the body diode Db. Is prevented.

This embodiment has the following effects. (1) Since the well potential of the MOS transistor serving as the switching element 6 is adjusted to the potential of the hold capacitor 8, when the switching element 6 is turned off, charge injection hardly occurs, and the fluctuation of the hold potential is suppressed. it can. A voltage is supplied to the gate of the first switching element 6 from a voltage source 10 that drives the MOS transistor with reference to the well potential of the MOS transistor. Therefore, the amplitude of the gate signal of the MOS transistor can be reduced, and the charge injection and the capacitive field-through that occur when the first MOS transistor serving as the switching element is turned off can be reduced.

(2) Since the first switching element 6 is connected to the node N1 of the holding capacitor 8 at the source and the node N1 is connected to the well W1, the well potential of the MOS transistor as the switching element 6 is reduced. The configuration adapted to the potential of the hold capacitor 8 is simplified.

(3) A second switching element 7 is connected in series from the first switching element 6 to the input terminal 2 side, and is turned on and off simultaneously with the first switching element 6. Therefore, it is possible to prevent a current from flowing from the holding capacitor 8 through the body diode Db of the first switching element 6 at the time of holding, and it is possible to suppress a change in the hold potential.

(4) Buffers 4 on the input and output sides
5, the influence on the input signal source is reduced, and discharge due to the load resistance is prevented. (Second Embodiment) Next, a second embodiment will be described with reference to FIG. This embodiment is different from the above embodiment in the configuration relating to the second switching element 7, and the other configuration is the same. The same parts as those of the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

N channel as second switching element 7
The source of the MOSFET on the output side of the buffer 4
Connected and the source is connected to the well W2
I have. The source and drain of the second switching element 7
Is a body diode Db whose cathode is on the drain side.
Connected through. Of the second switching element 7
Between the gate and the output of buffer 4
Voltage V_g1, Voltage V during hold_g0Each voltage
Voltage source 12 is connected. Where V _thMO
Assuming that the threshold voltage of the SFET is V_g1> V_th> V_g0Noseki
Is set to

In this embodiment, the gate of the second switching element 7 is connected to a voltage source 12 for driving the MOS transistor with reference to the well potential of the MOS transistor.
Is supplied with voltage.

This embodiment has the following effects in addition to the same effects as (1) to (4) of the above embodiment. (5) to the gate of the first and second switching elements 6 and 7, and generates a threshold voltage V _th higher than the voltage of the MOS transistor when the sample, the threshold voltage V _th during holding
Voltage sources 10, 12 for generating a lower voltage are connected. That is, since the power supply voltage Vcc is not directly applied to each gate, an appropriate voltage equal to or lower than the gate withstand voltage is supplied to the gates of the switching elements 6 and 7 even if the power supply voltage Vcc is equal to or higher than the gate withstand voltage. Switching element 6,7
Is driven without hindrance.

(Third Embodiment) Next, a third embodiment will be described with reference to FIG. This embodiment differs from the above embodiments in that the clock field through can be reduced and the droop rate can be improved. The same parts as those of the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

The first switching element 6 has a drain connected to the node N1 of the holding capacitor 8, and a source connected to the drain of the second switching element 7. The source of the first switching element 6 is connected to the well W1. The source and the drain of the first switching element 6 are connected via a body diode Db whose cathode is on the drain side. A capacitor 13 for maintaining the well potential of the first switching element 6 at a value close to the potential of the holding capacitor 8 is provided on the input terminal 2 side of the first switching element 6.
The well W1 of the first switching element 6 is connected to the node N2 of the capacitor 13, and the other end of the capacitor 13 is connected to the ground terminal 9. First switching element 6
A voltage source 10 is connected between the gate of the buffer 5 and the output side of the buffer 5.

The second switching element 7 has a drain connected to the node N 2 of the capacitor 13 and a well connected to the ground terminal 9. A voltage source 11 is connected between the gate of the second switching element 7 and the ground terminal 9.

According to the present invention, the first switching element 6
By the capacitor 13 further provided on the input terminal 2 side,
The well potential of the first switching element 6 is maintained at a value close to the potential of the hold capacitor 8. Therefore, charge injection is unlikely to occur as in the above embodiments. The body diode Db prevents a current from flowing from the hold capacitor 8 to the input side.

The well N1 of the switching element 6 is not connected to the node N1 of the holding capacitor 8, but only the drain is connected. Therefore, the leakage current from the node N1 of the holding capacitor 8 is reduced.

This embodiment has the following effects in addition to the effects (1) and (4) of the above embodiment. (6) The well N1 of the switching element 6 is not connected to the node N1 of the holding capacitor 8, and only the drain is connected. Therefore, the leakage current from the node N1 of the holding capacitor 8 is reduced, and the droop rate can be reduced. As a result, the change in the hold potential of the hold capacitor 8 can be reduced as compared with the first and second embodiments.

(Fourth Embodiment) Next, a fourth embodiment will be described with reference to FIG. This embodiment is the same as the second embodiment in that it can be applied to a circuit whose power supply voltage exceeds the gate breakdown voltage of each of the switching elements 6 and 7. The node N1 of the holding capacitor 8 is not connected to the well W1 of the switching element 6 and only the drain is connected, and the well potential of the first switching element 6 is held at a value close to the potential of the holding capacitor 8. The third embodiment is the same as the third embodiment in that a capacitor 13 is provided. And N-channel MOSFET
This embodiment is greatly different from the above embodiments in that three switching elements are connected in series. The same parts as those of the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

The third switching element 14 has a source connected to the source of the first switching element 6 and a drain connected to the drain of the second switching element 7. The source of the third switching element 14 is a well W
3 and the node N2 of the capacitor 13
It is connected to the. The source and the drain of the third switching element 14 are connected via a body diode Db whose cathode is on the drain side.

First and third switching elements 6, 14
Gate is the voltage V _g1 at the time of sampling, and the voltage V
It is connected to a voltage source 15 that generates a voltage of _g0 . However, when V _th is the threshold voltage of the MOSFET, the relationship is set as V _g1 > V _th > V _g0 . The voltage source 15 is connected to the output side of the buffer 16 in which the node N2 of the capacitor 13 is connected to the non-inverting input terminal.

The second switching element 7 has the same configuration as in the second embodiment. That is, the gate of the second switching element 7 is connected to the voltage source 11, and the source is connected to the well W2. Second switching element 7
Are connected via a body diode Db whose cathode is on the drain side.

This embodiment has the same effects as (1), (4) to (6) of the above embodiment. (Fifth Embodiment) Next, a fifth embodiment will be described with reference to FIG. This embodiment is significantly different from the above embodiments in that a well driving amplifier 17 of the first switching element 6 and a well driving amplifier 18 of the second switching element 7 are provided. Further, the voltage V _g1 + V _OFF samples during the gates of the first and second switching elements 6 and 7, the voltage V _g1 + V _OFF during the hold
Are different from each other in that voltage sources 19 and 20 that generate respective voltages are connected. However, Vth is MOSFET
When the threshold voltage is set to the relationship of _{V g1> V th> V g0} . The same parts as those of the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

The output terminal of the well driving amplifier 17 of the first switching element 6 is connected to the well W 1 of the first switching element 6 and the voltage source 19. One end of the non-inverting input terminal of the well driving amplifier 17 is connected to a connection point between the other end of the resistor R whose one end is connected to the output side of the buffer 5 and the current source 21.

The output terminal of the well driving amplifier 18 of the second switching element 7 is connected to the well W 2 of the second switching element 7 and the voltage source 20. One end of the non-inverting input terminal of the well driving amplifier 18 is connected to a connection point between the other end of the resistor R whose one end is connected to the output side of the buffer 4 and the current source 22.

In this embodiment, the well potentials of the switching elements 6 and 7 are lower than those of the above embodiments. In this embodiment, (4) of the above embodiment is used.
The following effects are obtained in addition to the same effects as (6).

(7) The well potentials of the switching elements 6 and 7 are supplied by the well driving amplifiers 17 and 18. Therefore, the load on the buffers 4 and 5 is reduced. (8) Since the well potential of the first switching element 6 decreases, the flow of current from the well W1 to the source and drain due to the parasitic diode is suppressed.

(Sixth Embodiment) Next, a sixth embodiment will be described with reference to FIG. This embodiment has a configuration in which a generally known clock field-through compensation circuit is applied to the configuration of the first embodiment. The same parts as those in the first embodiment are denoted by the same reference numerals, and detailed description is omitted.

Between the first switching element 6 and the buffer 5, there is connected a compensating transistor 23 comprising an N-channel MOSFET, whose source and drain are short-circuited and connected to the well W4. The gate of the compensation transistor 23 is connected to a voltage source 24 that generates a voltage V _g0 during sampling and a voltage V _g1 during holding.

In this embodiment, when the first switching element 6 changes from on to off, the compensation transistor 2
3 changes from off to on. Then, the stray capacitance of the first switching element 6 and the stray capacitance of the compensation transistor 23 act so as to cancel each other out of the change in the potential difference therebetween, and clock field through is reduced.

Therefore, in this embodiment, the first
The following effects are obtained in addition to the effects (1) to (4) of the embodiment. (9) Since the clock field through in the state before the compensation is small, the clock field through after the compensation by the compensation transistor 23 becomes smaller, and the fluctuation of the hold potential can be further suppressed as compared with the first embodiment.

The embodiment is not limited to the above, and may be embodied as follows, for example. The configuration to which the generally known clock field-through compensation circuit is applied is not limited to the one applied to the first embodiment, but may be applied to other embodiments. For example, as shown in FIG. 8, the present invention may be applied to the configuration of the second embodiment. That is, the compensation transistor 23 composed of an N-channel MOSFET is connected in series between the first switching element 6 and the buffer 5 with its source and drain short-circuited. The drain of the compensation transistor 23 is connected to the drain of the first switching element 6, and the well W4 is connected to the node N2 of the capacitor 13. The gate of the compensation transistor 23 is connected to a voltage source 24 that generates a voltage V _g0 during sampling and a voltage V _g1 during holding. In this embodiment, the clock field through is smaller than in the second embodiment, and the fluctuation of the hold potential can be further suppressed.

In the fourth embodiment, instead of providing the buffer 16, as shown in FIG.
May be connected between the gates of the first switching element 6 and the third switching element 14 and the output side of the buffer 5. In this case, the same effects as those of the fourth embodiment can be obtained, and the structure can be simplified.

The switching elements 6, 7, and 14 are replaced with N-channel MOSFETs and P-channel MOs.
A configuration using an SFET may be used. A configuration using N-channel MOSFETs as the switching elements 6, 7, 14 is suitable when the input voltage Vi is low, and a configuration using P-channel MOSFETs when the input voltage Vi is high is preferable.

In each of the above embodiments, an N-channel MOSFET is used as each switching element.
A switching element formed of a set of transistors in which a P-channel MOSFET and a P-channel MOSFET are connected in parallel may be used. In this case, the range of the input voltage to be sampled can be widened.

As in the fifth embodiment, well-driving amplifiers 17, 1 are connected to both switching elements 6, 7, respectively.
Instead of the configuration in which 8 is provided, only a well driving amplifier for one of the switching elements may be provided.

In each of the above embodiments, instead of connecting the source of the first switching element 6 to the node N1 of the holding capacitor 8, the drain is connected and the source is connected to the input side (the second switching element side). It may be configured to be connected.

In each of the above embodiments, the source of the second switching element 7 may be connected to the drain instead of connecting to the buffer 4 and the source may be connected to the output side (the first switching element side). Good.

The buffers 4 and 5 are not essential and may be omitted. The invention (technical idea) that can be grasped from the embodiment will be described below.

(1) In the invention according to any one of claims 1 to 3, a source and a drain are short-circuited between the first MOS transistor and an output terminal, and the first MOS transistor is electrically connected to the first MOS transistor. MOSFE of the same type
A compensation transistor made of T is connected, and a voltage having a phase opposite to the voltage supplied to the gate of the first MOS transistor is supplied to the gate of the compensation transistor.

(2) In the invention according to any one of claims 1 to 5, each switching element is N
It is composed of a set in which a channel MOSFET and a P-channel MOSFET are connected in parallel.

(3) Claims 1 to 5 and (1),
In the invention according to any one of (2), the sample-hold circuit is connected to the input terminal and the output terminal via a buffer.

(4) In the invention according to claim 5,
A buffer is connected to each of the input terminal and the output terminal, and each of the voltage sources is connected to an output terminal of the buffer on the input terminal side or the output terminal side.

[0069]

As described in detail above, claims 1 to 6 are provided.
According to the invention described in (1), clock field through can be reduced with a simple configuration, and the amplitude of the gate signal of the first MOS transistor connected to the holding capacitor can be reduced. According to the invention described in claim 3,
It can be used in a circuit whose power supply voltage is higher than the gate breakdown voltage of the switching element. According to the fourth to sixth aspects of the present invention, the droop plate can be improved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a first embodiment.

FIG. 2 is a schematic sectional view of the same.

FIG. 3 is a circuit diagram according to a second embodiment;

FIG. 4 is a circuit diagram of a third embodiment.

FIG. 5 is a circuit diagram of a fourth embodiment.

FIG. 6 is a circuit diagram of a fifth embodiment.

FIG. 7 is a circuit diagram of a sixth embodiment.

FIG. 8 is a circuit diagram of another embodiment.

FIG. 9 is a circuit diagram of another embodiment.

FIG. 10 is a schematic view of a conventional technique.

FIG. 11 is another prior art circuit diagram.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Sample hold circuit, 2 ... Input terminal, 3 ... Output terminal, 6 ... First switching element, 7 ... Second switching element, 8 ... Holding capacitor, 9 ... Ground terminal,
10, 12, 15 ... voltage source, 13 ... capacitor, 17,
18: Well driving amplifier, Db: Body diode,
D: drain, G: gate, S: source, W1, W2 ...
Well.

Claims (6)

[Claims] 1. An electronic device comprising: an input terminal inserted between an input terminal and an output terminal;
Using MOS transistors as switching elements,
A sample and hold circuit in which a holding capacitor is connected between an output terminal and a ground terminal, wherein the well potential of a first MOS transistor is adjusted to the potential of the holding capacitor, and the well of the MOS transistor is connected to a well. A voltage source for generating a voltage higher than the threshold value of the first MOS transistor at the time of sampling with reference to the potential and generating a voltage lower than the threshold value of the first MOS transistor at the time of holding is connected. A second MOS transistor for preventing a current from flowing through the body diode of the MOS transistor is provided on the input terminal side of the first MOS transistor, and generates a voltage higher than a threshold value of the second MOS transistor at the time of sampling. , The second M
A sample and hold circuit, wherein a voltage source for generating a voltage lower than a threshold value of the OS transistor is connected to a gate of the second MOS transistor. 2. A well potential of said second MOS transistor, which prevents a current from flowing through a body diode of said first MOS transistor during a hold, to a voltage on an input terminal side, and said second MOS transistor at a time of sampling.
2. The sample and hold circuit according to claim 1, wherein a voltage source that generates a voltage higher than the threshold value of the transistor and generates a voltage lower than the threshold value of the second MOS transistor during holding is connected. 3. Each of said voltage sources is separate from the power supply voltage,
3. The sample and hold circuit according to claim 1, wherein a voltage lower than a gate withstand voltage of the MOS transistor can be applied. 4. A plurality of the switching elements are connected in series, a first MOS transistor is connected to a node of the holding capacitor at a source or a drain, and the MOS transistor is connected to an input side of the first MOS transistor. For holding the well potential of the first MOS transistor at a value close to the potential of the holding capacitor, and the first MOS transistor is connected to the node of the capacitor.
The sample and hold circuit according to claim 1, wherein a well of the transistor is connected. 5. A capacitor provided on the input side of the first MOS transistor for holding the well potential of the MOS transistor at a value close to the potential of the holding capacitor, between the well of the MOS transistor and the substrate. 5. The sample and hold circuit according to claim 4, wherein a capacitor is used. 6. A sample-and-hold circuit inserted between an input terminal and an output terminal, wherein a MOS transistor is used as a switching element, and a hold capacitor is connected between the output terminal and a ground terminal. Two MOS transistors are provided in series between the holding capacitor and the input terminal, and the gate of the first MOS transistor connected to the holding capacitor is connected to the well potential with reference to the well potential during sampling. A voltage source that generates a voltage higher than the threshold value of the first MOS transistor and generates a voltage lower than the threshold value of the first MOS transistor during holding is connected, and a current flows through the body diode of the first MOS transistor during holding. The gate of the second MOS transistor provided on the input side to prevent A voltage source that generates a voltage higher than the threshold value of the second MOS transistor at the time of sampling and generates a voltage lower than the threshold value of the second MOS transistor at the time of holding, with reference to the well potential; A well driving amplifier for supplying a well potential of the first MOS transistor;
A sample and hold circuit provided with at least one of a well driving amplifier for supplying a well potential of an S transistor.