JP2002354061A - Intermediate frequency/baseband conversion for flexible frequency planning function. - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable to enhance the frequency planning function option of a RF(Radio Frequency) receiver device. SOLUTION: A digital IF/baseband converter with excellent design is integrated with the RF receiver device in a RF receiver device (31) physically separated from a baseband processor (32) operating with harmony.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to conversion of an intermediate frequency (IF) signal to a baseband signal in a communication receiver device, and more particularly to conversion of an analog intermediate frequency signal to a digital baseband (BB) signal.

[0002]

2. Description of the Related Art FIG. 1 shows a baseband processor 13 (eg, implemented as a digital signal processing integrated circuit).
(E.g., implemented as an integrated circuit)
1 schematically illustrates relevant parts of a conventional communication receiver device including an F receiver 11. Some parts of the communication device shown in FIG. 1 perform a cooperative operation to convert an analog IF signal 17 generated by the RF receiver 11 into a digital baseband signal 18, whereby the digital communication processing unit 16 Perform a predetermined digital communication processing operation. The A / D converter 12 of the RF receiver 11 converts the analog IF signal 17 into a digital signal 19. This digital IF signal 19 is input to the digital IF / BB converter 14, where the digital IF signal 19
Is converted to a digital baseband signal 10. Further, the digital baseband signal 10 is passed through a filter 15 that is matched to filter the signal 10, where a predetermined digital baseband signal 18 is generated.

One example of the digital IF / BB converter 14 is a so-called CORDIC, which receives a digital IF signal 19 in a sign amplitude format from the A / D converter 12 and multiplies the digital signal by a digital sine and cosine function.
(Cordinate Rotation Digit
al Computer) circuit. These operations convert the digital IF signal 19 into a digital baseband signal 10 divided into I (in-phase) and Q (quadrature) components that are independently filtered by a matched filter 15.

One example of a matched filter 15 is a so-called "integration and dump" filter, which basically adds a predetermined number of samples and averages this sum. This type of digital filtering is also well known as decimation.

FIG. 2 illustrates a more detailed example of the conventional IF / BB conversion configuration of FIG. In the example of FIG.
The RF receiver 11 is a GPS (Global Positioning System) receiver, and illustrates an example of a defect related to the configuration of FIG. As shown in FIG. 2, the design of the digital IF / BB converter 14 (the CORDIC circuit in this example) and the matching filter 15 in the baseband processor 13 is as follows.
The frequency planning option in the RF receiver 11 is particularly limited. CORDI in FIG.
The design of the C circuit 14 and matched filter 15, the frequency f _c of the analog IF signal 17, (28/3) × f ₀ becomes (where, f ₀ is the bandwidth of the received RF signal, for example, 1 a .023MHz), also a sampling rate f _s to be used in the a / D converter 12, (1
12/3) × f ₀ . Relationship between the IF frequency f _c and the sampling rate f _s is f _s = 4 × f _c, this relationship, many conventional CORDIC circuit has become a standard.

[0006] IF frequency f _c and the requirements for the sampling rate f _s becomes shall impose unfavorable restrictions on frequency planning options in the RF receiver 11. In particular,
In order to generate the IF signal 17 where f _c = (28/3 × f ₀ ), a mixer circuit (not shown) for generating the IF signal 17 from the input RF signal (not shown) is required, and the A / D converter Reference numeral 12 denotes an IF signal 17 for sampling frequency f _s
= (112/3) × f ₀ . In order to provide a digital baseband signal 18 at the sampling rate that is expected by the digital communication processing unit _{16 (f s = 2 × f} 0), these frequencies f _c
And f _s must have the above values. Therefore, the design of the CORDIC 14 and the matched filter 15 is R
Obviously, this will particularly limit the frequency planning options of the F receiver 11.

[0007] The flexibility of frequency planning is important because today's communication systems integrate more complex functions into smaller ones. Also, more and more communication systems are being integrated into a single consumer device. For example, early 3G mobile phones have dual-band GSM
Wireless, WCDMA wireless, Bluetooth wireless and GPS receivers would be included. As a result, signals of various frequencies are generated excessively inside a single device. Also, these signals interfere with each other,
This will produce a desired signal and an undesired signal at harmonic multiples of each signal. In addition, these signals interfere with each other due to the non-linearity of the device, resulting in a new signal that is the sum or difference of some of these signals.

[0008] Therefore, the frequency plan of each wireless device must take into account all other signals present in a single device (and the signals entering the device's antenna). Careful selection of each local oscillator (LO) and intermediate frequency (IF) source or information channel is a complex task. By selecting these signal frequencies with consideration for each other, the designer of the communication system can ensure that these signal sources interfere with each other without sacrificing any of the radios in the equipment. You can confirm that there is no.

[0009]

SUMMARY OF THE INVENTION It is, therefore, an object of the invention to provide a communication radio of the type shown in FIGS. 1 and 2 with more flexibility in the frequency planning of the RF receiver. .

[0010]

SUMMARY OF THE INVENTION In accordance with the present invention, a digital IF / BB converter and a matched filter are integrated into an RF receiver, thereby imposing on conventional architecture baseband processor designs. The advantage is that restrictions on the IF frequency and the sampling frequency can be avoided.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings.

FIG. 3 is a diagram schematically showing a relevant part of an embodiment of a communication receiver (or a receiver of a transceiver) according to the present invention. The communication receiver of FIG. 3 can be provided to devices such as mobile phones, laptop computers and personal digital assistants. In the example of FIG. 3, the analog IF / digital BB conversion is performed by the converter 34 integrated in the RF receiver 31. In the embodiment shown in FIG. 3, the converter 34 can generate a digital baseband signal 38. The signal 38 is input to the baseband processor 32 (eg, a digital signal processor integrated circuit), where it is input to a digital communication processor 36 of the type shown at 16 in FIGS. The RF receiver 31 also includes a conventional mixer 33 that mixes the incoming RF signal and drops it into an IF signal 37. The analog IF / digital BB conversion is performed by the RF receiver 31 (for example,
RF receiver integrated circuit), thereby eliminating the frequency planning constraints imposed by the prior art architecture as shown in FIGS. The 31 frequency planning options can be particularly enhanced.

FIG. 4 shows the analog IF / digital B of FIG.
FIG. 3 is a diagram schematically illustrating an embodiment of a B converter.
In FIG. 4, the IF signal 37 is digitized by the A / D converter 42 and a digital IF signal 49 generated.
Is input to the digital IF / BB converter 44.
The converter 44 converts the first digital baseband signal 4
0 and this signal is input to a matched filter 45, which further converts the second digital baseband signal 4
8 is generated. In some embodiments, converter 4
4 can be implemented by a conventional CORDIC circuit, for example. Also, in some embodiments, matched filter 45 can be implemented as a pair of decimators of the same type as described in FIG.

In some embodiments, the digital baseband signal 38 generated by the analog IF / digital BB converter 34 of FIGS. 3 and 4 is the same as the digital baseband signal illustrated at 18 in FIGS. Things. However, the converter 34 is connected to the RF receiver 31
, The frequency planning options of the RF receiver 31 are advantageously enhanced. For example, according to FIG. 2, to make the digital baseband signal 38 the same as the signal 18 having the sampling frequency f _s = 2 × f ₀ ,
The RF receiver 31 shown in FIGS. 3 and 4 performs the desired frequency planning as long as the digital baseband signal 38 input to the digital communication processing unit 36 of the baseband processor 32 has a sampling frequency of 2 × f _0. Can be used. Therefore, by adjusting the digital IF / BB converter 44 design of the matched filter 45 to a desired one, with respect to the frequency f _c and the sampling frequency f _s of the IF signal 37 used to operate the A / D converter 42, A desired frequency plan can be obtained. This arrangement allows the manufacturer or user of the RF receiver (typically configured physically separate from the baseband processor) to better manage the frequency plan.

In the above example, the sampling frequency of signal 38 is 2 × f ₀ , but the embodiments of FIGS. 3 and 4 can support any sampling rate of at least 2 × f ₀ for signal 38. Yes, it is clear that this is also advantageous from the viewpoint of signal processing.

[0016] For example, in the example using the CORDIC circuit converter 44, the necessary _{requirements, f s = 4 × f c} , i.e., the sampling frequency of the A / D converter 42, I
This is four times the frequency of the F signal 37. Therefore, by appropriately designing the matched filter 45 and the converter 44 enables any desired combination of f _c and f _s, it hereinafter, is to enhance the flexibility of the frequency plan of the RF receiver 31 There is an advantage that you can. Further, since the clocks of the A / D converter 42 and the matched filter 45 are obtained from the reference clock (for example, PLL or DDFS) of the RF receiver, the complexity of the clock generation can be reduced.

FIG. 5 shows the analog IF /
A more detailed embodiment of the digital BB converter 34 is shown, particularly in a GPS receiver. In the example of FIG. 5, the A / D converter 42 is a 4-bit A / D converter, and the digital IF / BB converter 44 is
It is a DIC circuit. In the embodiment of FIG.
5 is implemented as a combination of a decimator and a quantizer. Therefore, the output of the CORDIC circuit 44 is first reduced to one-tenth, for example, in the usual manner described above, and then reduced to one-tenth, from 4 bits per sample to 4 bits per sample. It is equalized to 2 bits.

Further, in the embodiment shown in FIG.
The four parallel signals provided at 5 to 38, i.e., the I amplitude and sign signals and the Q amplitude and sign signals, are input to a multiplexer and parallel / serial converter unit 53, where the four parallel signals are It is converted to a serial format for transmission to the baseband processor 52. The baseband processor 52 includes a complementary serial / parallel converter 54 that converts the serial data back into parallel form, thereby providing the signal 38 to the digital communication processor 36. The serial transmission of the signal 38 has an advantage that the number of connections (and the number of pins) between the RF receiver 51 and the baseband processor 52 can be reduced. In some embodiments, the reduced number of connections favors the remaining connections as differential connections such as low voltage differential signaling (LVDS) or differential PECL instead of the CMOS, TTL or single-terminated PECL connections shown in FIG. Therefore, noise immunity is improved and erroneous signals are suppressed. In addition, COR
Since the DIC circuit 44 and the matched filter 45 are integrated in the RF receiver 51, the receiver 51 does not need to provide a sampling (acquisition) clock to the baseband processor 52, which can be used, for example, in the conventional system shown in FIG. As compared with the configuration of the technology, an extra connection between the RF receiver 51 and the baseband processor 52 can be eliminated.
The clock to the 53 parallel / serial converter is
It is obtained from the same reference clock as the clock of the A / D converter 42 and the matched filter 45. The reference clock is supplied from the RF receiver to the baseband processor (G in FIG. 5).
(See PS clock) and used for signal processing (eg, after appropriate frequency division) and serial / parallel conversion.

In some embodiments, 38 four parallel signals can be transmitted to the baseband processor in parallel in a manner similar to the transmission of the 19 parallel signals of FIG.

Comparing FIGS. 2 and 5, the sampling rate (ie, data rate) of the digital signaling between the RF receiver and the baseband processor is:
It has the advantage of being much lower and reducing power consumption at the communication receiver. The low data rate in FIG.
Use of a serial data link is also possible. Furthermore, the low data rate allows for high resolution sampling, such as, for example, the 4-bit A / D converter 42 of FIG.

In some embodiments, for example, twelve parallel signals from a matched filter are split into three serial data streams of four bits, each of which is transmitted to a baseband processor. ,
They are reproduced by a suitable serial / parallel conversion.

FIG. 6 shows an example of processing performed by the RF receiver shown in FIGS. In step 61, the IF signal is digitized. Step 6
At 2, the digitized IF signal is converted to a digital baseband signal. In step 63, the digital baseband signal is passed through a matched filter. Step 64
Then, the digital baseband signal passed through the filter is
Transfer to baseband processor.

As described above, the embodiments of the present invention have been described in detail. However, the present embodiments do not limit the scope of the present invention, and can be realized by various embodiments. This application is pending US Provisional Application No. Claims priority of 60 / 204,301 (filed May 15, 2000) under 35use119 (e) (1).

[Brief description of the drawings]

FIG. 1 shows an IF / B used in a conventional communication system.
The figure which showed the outline of B conversion architecture.

FIG. 2 is a diagram schematically illustrating a detailed example of the conventional architecture of FIG. 1;

FIG. 3 is a diagram schematically showing a relevant part of the embodiment of the communication receiver according to the present invention.

FIG. 4 is a diagram schematically illustrating an embodiment of the analog IF / digital BB converter in FIG. 3;

FIG. 5 is a more detailed schematic diagram of one embodiment of the analog IF / digital BB converter of FIGS. 3 and 4;

FIG. 6 is a diagram showing an embodiment of an operation performed by the embodiment of the communication receiver in FIGS. 3 to 5;

[Explanation of symbols]

 31 RF receiver 32 Baseband processor

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Sheriff Mbaviy United States Texas, Plano, E Besham Drive 3220 (72) Inventor Alan Holden United States of America Texas, McKinney, Arbor Hollow Drive 5013 (72) Inventor Francisco D'Antony United States of America Texas, Richardson, Buckingham 430, apartment number 1625 F-term (reference) 5K004 AA01 BD00

Claims (21)

[Claims] A mixing circuit for mixing an analog RF signal into an analog IF signal; an analog IF / digital baseband converter connected to the mixer for converting the analog IF signal into a digital baseband signal; And an output connected to a digital baseband converter for sending the digital baseband signal to a baseband processing device that is physically independent of the RF receiving device. 2. The device of claim 1, provided as an integrated circuit. 3. The apparatus according to claim 1, wherein said analog IF / digital baseband converter is adapted to generate a digital IF signal.
An A / D converter for digitizing a signal;
A digital IF / baseband converter connected to the converter for converting the digital IF signal into a further digital baseband signal. 4. The apparatus according to claim 3, wherein the analog IF / digital baseband converter is connected to the digital IF / baseband converter, and filters the further digital baseband signal to make the first mention. A filter for generating a digital baseband signal. 5. The apparatus according to claim 4, wherein said filter includes a decimator. 6. The apparatus according to claim 4, wherein said filter comprises a quantizer. 7. The apparatus according to claim 3, wherein the digital IF / baseband converter comprises a COR.
A device comprising a DIC circuit. 8. The apparatus according to claim 1, wherein the analog IF / digital baseband converter generates the digital baseband signal in a parallel format, the analog IF / digital baseband converter and the digital baseband signal. And a parallel / serial converter connected between the output and the output for converting the serial format from a parallel format to a serial format and providing the serial format digital baseband signal to the output. 9. An input for receiving a digital baseband signal from an RF receiver physically independent of the baseband processor, and a digital processing operation on the digital baseband signal connected to the input. And a digital communication processing unit for performing the processing. 10. The apparatus according to claim 9, wherein the input is for receiving the digital baseband signal in a serial format, and is connected between the input and the digital communication processing unit.
An apparatus, comprising: a serial / parallel converter that converts the digital baseband signal from a serial format to a parallel format and sends the parallel digital baseband signal to the digital communication processing unit. 11. The apparatus of claim 10, wherein said serial / parallel converter includes an input for receiving a clock signal from an RF receiver. 12. The apparatus of claim 9, provided as an integrated circuit. 13. A mixing circuit for mixing an analog RF signal into an analog IF signal, an analog IF / digital baseband converter connected to the mixer for converting the analog IF signal into a digital baseband signal, and An RF receiver device connected to an IF / digital baseband converter and an output for outputting the digital baseband; and an RF receiver device connected to the RF receiver device and transmitting the digital baseband signal from the RF receiver device. An input for receiving, a digital communication processor connected to the input for performing digital processing operations on the digital baseband signal, and a baseband processing device physically independent of the RF receiving device; Including a communication receiver. 14. The communication receiver according to claim 13, wherein the baseband processing device is provided as an integrated circuit. 15. The communication receiver according to claim 14, wherein the RF receiver device is provided as an integrated circuit. 16. The communication receiver according to claim 14, wherein said baseband processing device is a digital signal processor. 17. The communication receiver according to claim 13, wherein said RF receiver device is provided as an integrated circuit. 18. A method for mixing an analog RF signal into an analog IF signal in an RF receiver device, a method for converting the analog IF signal into a digital baseband signal in the RF receiver device, Transferring the digital baseband signal to a baseband processing device that is physically separate from the RF receiver device. 19. The method according to claim 18, wherein said transferring comprises transferring the digital baseband signal in a serial format. 20. A baseband processing device receiving a digital baseband signal from an RF receiver device physically separated from the baseband processing device, wherein the baseband processing device converts the digital baseband signal into a digital baseband signal within the baseband processing device. Performing a digital processing operation on the baseband processing apparatus. 21. The method of claim 19, wherein said receiving comprises receiving a digital baseband signal in a serial format, further comprising converting the serial digital baseband signal to a parallel format. And performing the digital processing operation on the digital baseband signal in a parallel format.