JP2002354058A - Phase correction circuit of common mode and quadrature signals - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a phase correction circuit for common mode and quadra ture signals whose phase shifting range is not affected by changes in ambient environment or aging when a phase shifting range of a transmission clock signal is set by adjusting the phase. SOLUTION: This circuit consists of the following devices: a digital-to-analog converter 4 for common mode signals which converts common mode signals from digital to analog signals using a leading part of a transmission clock signal (TXC.I); a digital-to-analog converter 5 for quadrature signals which converts quadrature signals from digital to analog signals using a leading part of the TXC.Q; a pulse width modulator 13 which changes the position of a trailing part of the TXC.Q; high-frequency converters 8 and 9 which convert common mode and quadrature signals which have been converted from digital to analog signals to high-frequency common mode and quadrature signals. The pulse width modulator 13 adjusts the position of the trailing part of the TXC.Q so that phase errors of the high-frequency common mode and quadrature signals are eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase correction circuit for in-phase and quadrature signals. The present invention relates to an in-phase and quadrature signal phase correction circuit that corrects a phase error between a high-frequency in-phase signal and a high-frequency quadrature signal during digital-analog conversion when a phase signal and a high-frequency quadrature signal are formed.

[0002]

2. Description of the Related Art Conventionally, four-phase phase shift keying (QP
SK) In a transmitter / receiver adopting a modulation method, for example, a mobile phone, a high frequency (RF) signal is transmitted in a signal transmitting unit.
An in-phase signal (I) and a high frequency (RF) quadrature signal (Q) are formed. In this case, the high-frequency in-phase signal and the high-frequency quadrature signal originally have a phase difference of 90 °. When a signal is formed, variations in characteristics in a high-frequency modulation unit that forms a high-frequency in-phase signal and a high-frequency quadrature signal, variations in characteristics in an amplification unit that amplifies the high-frequency in-phase signal and the high-frequency quadrature signal, a high-frequency in-phase signal and A phase error occurs in which the phase relationship between the high-frequency in-phase signal and the high-frequency quadrature signal deviates from the 90 ° difference due to a variation in characteristics of the filter unit that removes unnecessary frequency components from the high-frequency quadrature signal. And when such a phase error occurs,
The bit error rate (BER) in the transceiver is degraded, and data and information cannot be transmitted accurately.

In order to solve such a problem, a baseband in-phase signal and a baseband quadrature signal are converted into an in-phase digital-to-analog converter and a quadrature digital-to-analog converter, respectively.
When digital-to-analog conversion is performed by an analog converter, the position of a rising portion or a falling portion of a clock signal supplied to one of the digital-to-analog converters is adjusted, whereby the baseband in-phase signal and the baseband quadrature signal are adjusted. A phase correction circuit for in-phase and quadrature signals that eliminates a phase error between a high-frequency in-phase signal and a high-frequency quadrature signal obtained by modulating a carrier wave has already been proposed.
One example is a baseband signal processing circuit disclosed in JP-A-2000-124963, that is, a phase correction circuit for in-phase and quadrature signals.

Here, FIG.
FIG. 1 is a block diagram illustrating a main configuration of a phase correction circuit for in-phase and quadrature signals disclosed in Japanese Patent No. 4963.

As shown in FIG. 5, the phase correction circuit for the in-phase and quadrature signals includes a transmission data generation section (TX generation).
51, an in-phase transmission data forming unit (TX-I) 52, a quadrature transmission data forming unit (TX-Q) 53, an in-phase digital-analog converting unit (D / A-I) 54, and a quadrature digital- An analog converter (D / A · Q) 55, an in-phase low-pass filter (LF · I) 56, a quadrature-side low-pass filter (LF · Q) 57, and an in-phase frequency converter (MI
X · I) 58 and the orthogonal frequency converter (MIX · Q) 5
9, a local oscillator (OSC) 60, and a signal adder (AD
D) 61, system pulse signal generator (SC generation) 6
2 and transmission clock signal generator (TX / C generation) 63
, A phase adjustment unit 64, a control unit (CPU) 65, and a transmission antenna 66.

Then, a transmission data generation unit (TX generation) 5
1 is connected to the in-phase transmission data forming unit 52 and the quadrature transmission data forming unit 53, respectively. The in-phase side digital-analog conversion unit 54 is connected to the in-phase transmission data forming unit 52, the in-phase low-pass filter 56, and the transmission clock generator 63, respectively. Quadrature digital-analog converter 55
Are connected to the orthogonal transmission data forming unit 53, the orthogonal low-pass filter 57, and the phase adjusting unit 64, respectively. The in-phase side frequency converter 58 is connected to the in-phase side low-pass filter 56, the local oscillator 60, and the signal adder 61, respectively.
The quadrature-side frequency conversion unit 59 includes a quadrature-side low-pass filter 5
7, the local oscillator 60 and the signal adder 61. The signal adding unit 61 is connected to the transmission antenna 66, and the system pulse signal generator 62 is connected to the transmission clock signal generator 63 and the control unit 65, respectively. The transmission clock signal generator 63 is connected to the phase adjustment unit 64.

FIG. 6 is a signal waveform diagram showing the state of the operation signal of each section of the in-phase and quadrature signal phase correction circuit shown in FIG.

In FIG. 6, the uppermost waveform shows the transmission data (TX) waveform generated by the transmission data generator 51.
The second waveform shows the transmission clock signal (TXC · I) waveform supplied to the in-phase digital-analog converter 54, and the third waveform shows the quadrature digital-analog converter 5
5 shows the waveform of the transmission clock signal (TXC · Q) supplied to the reference numeral 5, and the waveform at the fourth stage shows the in-phase analog signal (TXC · I) obtained by sampling with the transmission clock signal (TXC · I) in the in-phase digital-analog converter 54. AS
I) shows the waveform, and the fifth stage waveform shows the transmission clock signal (TXC ·
Q) shows a quadrature analog signal (AS · Q) waveform obtained by sampling, and the sixth waveform shows a high-frequency in-phase signal (RF · Q) obtained by high-frequency modulation of the in-phase analog signal (AS · I). I) shows a waveform, and the lowermost waveform shows a high-frequency quadrature signal (RF · Q) waveform obtained by high-frequency modulation of the quadrature analog signal (AS · Q). The horizontal axis of each row indicates time.

The operation of the in-phase and quadrature signal phase correction circuit having the above-described configuration will be described with reference to a signal waveform diagram shown in FIG.

[0010] The system pulse signal generator 62 generates a system pulse signal (SC) whose frequency is stabilized by the control of the control unit 65 and supplies the system pulse signal (SC) to the transmission clock signal generator 63. The transmission clock signal generator 63 frequency-divides the supplied system pulse signal (SC) to form a transmission clock signal (TXC · I), and generates a transmission clock signal as shown in the second waveform in FIG. (TXC · I) is supplied to the in-phase side digital-analog conversion unit 54, and the transmission clock signal (TXC · I) as shown in the third waveform of FIG.
Q) is supplied to the quadrature digital-analog converter 55. At this time, the transmission clock signal (TXC · Q), as shown in the range of the dotted line in FIG. The falling point of (TXC · Q) is supplied to the quadrature-side digital-analog converter 55 in a state where the time of arrival of the falling part of the transmission clock signal (TXC · I) is made earlier than the time of arrival.

The transmission data generator 51 processes information and data to be transmitted, and forms transmission data (TX) consisting of an in-phase signal (I) and a quadrature signal (Q) as shown in the uppermost part of FIG. I do. The in-phase transmission data forming unit 52 supplies the in-phase signal (I) in the transmission data (TX) formed by the transmission data generating unit 51 to the in-phase digital-analog conversion unit 54, and the quadrature transmission data forming unit 53 Similarly, the orthogonal signal (Q) in the transmission data (TX) formed by the transmission data generation unit 51 is supplied to the orthogonal-side digital-analog conversion unit 55. The in-phase side digital-analog conversion unit 54 converts the in-phase signal (I) supplied from the in-phase transmission data forming unit 52 into a rising part of the transmission clock signal (TXC · I) supplied from the transmission clock signal generator 63. Sampling is performed at the timing shown by the arrow of the fourth waveform in FIG. 6 and the in-phase analog signal (A
SI). The quadrature-side digital-analog conversion unit 55 converts the quadrature signal (Q) supplied from the quadrature transmission data forming unit 53 using the falling part of the transmission clock signal (TXC · Q) supplied from the phase adjuster 64. Sampling is performed at the timing indicated by the arrow of the fifth waveform in FIG. 6, and instead of forming a quadrature analog signal as indicated by a dotted envelope of the same waveform, as indicated by a solid envelope of the same waveform A quadrature analog signal (AS · Q) is formed.

[0013] The in-phase analog signal (AS · I) is supplied to an in-phase frequency converter 58 after unnecessary frequency components are removed by an in-phase low-pass filter 56. Similarly,
The quadrature analog signal (AS · Q) is supplied to a quadrature-side frequency converter 59 after unnecessary frequency components are removed by a quadrature-side low-pass filter 57. In-phase side frequency converter 5
8 mixes the supplied in-phase analog signal (AS.I) with the carrier signal supplied from the local oscillator 60 and mixes the same into a high-frequency in-phase signal (RF.I) as shown in the sixth waveform in FIG. I). Orthogonal frequency converter 59
6 mixes the supplied quadrature analog signal (AS · Q) with the 90 ° phase-shifted carrier signal supplied from the local oscillator 60, and generates a high-frequency quadrature signal as shown in the lowermost waveform in FIG. (RF · Q) is generated. The high-frequency in-phase signal (RF · I) and the high-frequency quadrature signal (RF · Q) are added by the signal adding unit 61, and the added signals are transmitted through the transmitting antenna 66.

At this time, the phase shift amount of the transmission clock signal (TXC · I) passing through the phase adjuster 64 is adjusted, and the transmission clock signal (TXC · Q) supplied to the quadrature digital-to-analog converter 55 is set up. If the arrival time of the descending part is adjusted to be a suitable time, for example, if the falling part arrives at the time as shown in the third waveform of FIG.
The signal delay of the in-phase signal-side high-frequency circuit unit and the signal delay of the quadrature-signal-side high-frequency circuit unit cancel each other out, and the added high-frequency in-phase signal (RF · I) and high-frequency quadrature signal (RF ·
Q) can be prevented from occurring, and deterioration of the bit error rate (BER) can be prevented.

[0014]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
The in-phase and quadrature signal phase correction circuit disclosed in Japanese Patent No. 24963 adjusts the amount of phase shift of the phase adjuster 64 when the falling edge of the transmission clock signal (TXC · Q) passing through the phase adjuster 64 arrives. , The occurrence of a phase error between the high-frequency in-phase signal (RF · I) and the high-frequency quadrature signal (RF · Q) can be eliminated. Since the adjustment of the falling part of (TXC · Q) at the time of arrival is performed by analog means, the arrival of the falling part of the transmission clock signal (TXC · Q) at the time of the falling of the transmission clock signal (TXC · Q) may change due to changes in the surrounding environment or aging. The transmission clock signal (TXC
When the arrival time of the falling portion of Q) is slightly shifted, it is necessary to readjust the phase shift amount of the phase adjuster 64.

The present invention has been made in view of such a technical background, and an object of the present invention is to set a phase shift amount of a transmission clock signal by a phase adjuster in accordance with a change in the surrounding environment, aging, and the like. An object of the present invention is to provide a phase correction circuit for in-phase and quadrature signals in which a set phase shift amount does not change.

[0016]

In order to achieve the above object, according to the present invention, a phase correction circuit for in-phase and quadrature signals converts a phase signal into a digital signal by using a rising or falling portion of a transmission clock signal. A first digital-to-analog converter for performing an analog conversion, a second digital-to-analog converter for performing a digital-to-analog conversion of a quadrature signal using a falling portion or a rising portion of the transmission clock signal, and one of the transmission clock signals A pulse width modulator that changes the arrival time of a rising portion or a falling portion with a system clock signal,
A high-frequency conversion unit that converts the digital-analog converted in-phase signal and quadrature signal to a high-frequency in-phase signal and a high-frequency quadrature signal, respectively, and the pulse width modulator detects a phase error between the high-frequency in-phase signal and the high-frequency quadrature signal. There is provided a means for adjusting the arrival time of the rising or falling part of any of the transmission clock signals so as to eliminate them.

According to the above means, the phase shift amount of the transmission clock signal is set by using the pulse width modulator, and the pulse width modulator sets the rising edge or the falling edge of one of the transmission clock signals. The arrival time of the unit is changed by digital means in accordance with the cycle of the system clock signal having a frequency considerably higher than the frequency of the transmission clock signal, and it is not necessary to perform adjustment by analog means. The set phase shift amount does not change due to aging or the like, and as a result, it is possible to prevent the bit error rate (BER) from deteriorating, and it is possible to transmit data and information accurately.

[0018]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of a phase correcting circuit for in-phase and quadrature signals according to the present invention, and is a block diagram showing a main part of the circuit.

As shown in FIG. 1, a phase correction circuit for in-phase and quadrature signals according to this embodiment includes a transmission data generation unit (TX generation) 1 and an in-phase transmission data formation unit (TX ·
I) 2, a quadrature transmission data forming section (TX · Q) 3, and an in-phase (first) digital-analog converting section (D / A · I)
4 and a quadrature-side (second) digital-analog conversion unit (D /
A · Q) 5 and in-phase low-pass filter (LF · I) 6
, A quadrature-side low-pass filter (LF · Q) 7, an in-phase frequency converter (MIX · I) 8, a quadrature-side frequency converter (MIX · Q) 9, a local oscillator (OSC) 10, Section (ADD) 11, a system pulse signal generator (SC generation) 12, and a pulse width modulator (PWM) 13
And a control unit (CPU) 14 and a transmission antenna 15.

Then, a transmission data generation unit (TX generation) 1
Are the in-phase transmission data forming unit 2 and the quadrature transmission data forming unit 3
Connected to each other. The in-phase side digital-analog conversion unit 4 is connected to the in-phase transmission data forming unit 2, the in-phase side low-pass filter 6, and the pulse width modulator 13, respectively. The quadrature-side digital-analog converter 5 includes a quadrature transmission data generator 3, a quadrature low-pass filter 7, and a pulse width modulator 1.
3 respectively. The in-phase side frequency converter 8 is connected to the in-phase side low-pass filter 6, the local oscillator 10, and the signal adder 11, respectively. The orthogonal frequency converter 9
The low-pass filter 7 is connected to the local oscillator 10 and the signal adder 11. The signal adding section 11 is connected to the transmitting antenna 15. The system pulse signal generator 12 is connected to the pulse width modulator 13 and the control unit 14, respectively.

FIG. 2 is a block diagram showing an example of the internal configuration of the pulse width modulator 13 shown in FIG.
2 also shows a connection relationship between the system pulse signal generator 12 and the control unit 14. In FIG. 2, the same reference numerals are given to the same components as those shown in FIG.

As shown in FIG. 2, the pulse width modulator 1
3 is a frequency divider 13₁And the counting unit 13 _TwoAnd the determination unit 13_Three
And the signal combining unit 13_FourAnd system pulse signal input terminal
13 _FiveAnd the clock signal output terminal 13₆, 13₇age
Threshold input terminal 13₈Is provided.

The frequency divider 13 ₁ includes a counter 13 ₂ , a signal synthesizer 13 _4, and a system pulse signal input terminal 13 ₅
It is connected to the system pulse signal generator 12 and a clock signal output terminal 13 ₆ through. Counting unit 13
₂ is a judgment unit 13 ₃ and a system pulse signal input terminal 13
₅ are connected to the system pulse signal generator 12 respectively. Determining unit 13 ₃ is connected to the control unit 14 through the signal synthesizing unit 13 ₄ and a threshold input terminal 13 _8. Signal combining unit 13 _4, a clock signal output terminal 13
Connected to ₇ .

FIG. 3 is a signal waveform diagram showing the state of the operation signal of each part of the phase correction circuit for the in-phase and quadrature signals shown in FIG.

In FIG. 3, the uppermost waveform shows the transmission data (TX) waveform generated by the transmission data generator 1.
The waveform at the second stage shows the waveform of the transmission clock signal (TXC · I) supplied to the in-phase digital-analog conversion unit 4.
The waveform in the second row shows the transmission clock signal (TXC · Q) waveform supplied to the second digital-analog conversion section 5, and the waveform in the fourth row shows the transmission clock signal (TXC · Q) in the in-phase digital-analog conversion section 4. I) shows an in-phase analog signal (AS · I) waveform obtained by sampling according to I), and the fifth waveform is a quadrature digital-analog converter 5
Shows the waveform of the quadrature analog signal (AS · Q) obtained by sampling with the transmission clock signal (TXC · Q) in FIG.
I) shows a high-frequency in-phase signal (RF · I) waveform obtained by high-frequency modulation of I), and the lowermost waveform shows a high-frequency quadrature signal (RF · I) obtained by high-frequency modulation of the quadrature analog signal (AS · Q). RF / Q) waveforms are shown. The horizontal axis of each stage indicates time.

FIG. 4 is a signal waveform diagram showing the state of the operation signal of each part of the pulse width modulator 13 shown in FIG.

In FIG. 4, the uppermost waveform is the system pulse signal input terminal 1 from the system pulse signal generator 12.
3 ₅ shows the supplied system pulse signal (SC) waveform through the second stage of the waveform is output from the frequency divider 13 _1,
First digital - is supplied to the analog converter unit 4 shows the transmit clock signal (TXC · I) waveform, the waveform of the third stage shows the counter reading at the time of counting the system pulse signal (SC) by the counting unit 13 ₂ , the waveform of the fourth stage shown threshold information supplied through the threshold input terminal 13 ₈ from the control unit 14, shows the determination pulse waveform output from the determination unit 13 ₃ 5 stage, sixth stage waveforms are output from the signal synthesizer 13 _4, orthogonal side digital - indicating a transmission clock signal supplied to the analog converter unit 5 (TXC · Q) waveforms. The horizontal axis of each stage indicates time.

The operation of the phase correction circuit for in-phase and quadrature signals according to this embodiment will now be described with reference to the block diagrams of FIGS. 1 and 2 and the signal waveform diagrams of FIGS. 3 and 4.

The system pulse signal generator 12 controls the system pulse signal (S) whose frequency is stabilized as shown by the uppermost waveform in FIG.
C) is generated and supplied to the pulse width modulator 13. In the pulse width modulator 13, the frequency dividing section 13 _1, the transmit clock signal as shown the supplied system pulse signal (SC) frequency division, for example, divided by 256 to 2 stage of the waveform of FIG. 4 ( TXC.I), and this transmission clock signal (T
XC · I) an in-phase side digital over the clock signal output terminal 13 ₆ - supplies the signal combining unit 13 ₄ is supplied to the analog converter unit 4. The counting unit 13 ₂ includes the frequency dividing unit 13
Upon receiving a count start pulse from ₁ counts the supplied system pulse signal (SC), carried out the counting as indicated by the third stage of the waveform of FIG. 4, and supplies the count result to the determination unit 13 ₃ . Determining unit 13 _3, the threshold information as shown in the fourth stage of the waveform of FIG. 4 from the control unit 14, when supplied with 125 in the illustrated example, in FIG. 4 at the time the threshold is supplied A determination pulse is generated as shown by the fifth waveform. Signal combining unit 13 ₄ of FIG. 4 at the time of arrival of the rising portion of the transmission clock signal supplied from the frequency divider 13 ₁ (TXC · I) rising, also falls upon the arrival of the rising portion of the supplied determination pulse top forming a transmit clock signal as shown in the lower waveform (TXC · Q), orthogonal side digital this transmission clock signal (TXC · Q) through the clock signal output terminal 13 ₇ - supplied to the analog converter unit 5.

[0031] In this case, threshold information supplied from the control unit 14 sets the threshold of the count value of the system pulse signal in the counting unit 13 _2, namely the judgment unit 13 ₃
When the threshold value is changed, the generation time of the determination pulse is changed according to the cycle of the system pulse signal (SC). For example, when the threshold value is changed from 125 to 124, the generation time of the determination pulse is determined by the system pulse signal (S
C), the transmission clock signal (T
XC · Q) arrives at the falling portion by one cycle of the system pulse signal (SC), while the threshold value is 1
In the case of changing from 25 to 126, the generation time of the determination pulse is delayed by one cycle of the system pulse signal (SC), and the arrival time of the falling part of the transmission clock signal (TXC · Q) is changed to the system pulse signal (SC). ) Is delayed by one cycle. The transmission clock signal (TX
C · Q), as indicated by the range of the dotted line in FIG. 3, the arrival time of the falling portion is slightly earlier than the arrival time of the falling portion of the transmission clock signal (TXC · I).

The transmission data generator 1 processes information and data to be transmitted, and as shown by the uppermost waveform in FIG. 3, transmits data (I) and quadrature signal (Q) consisting of an in-phase signal (I) and a quadrature signal (Q). TX). The in-phase transmission data forming unit 2 supplies the in-phase signal (I) in the transmission data (TX) formed by the transmission data generating unit 1 to the in-phase digital-analog conversion unit 4, and the quadrature transmission data forming unit 3 Similarly, the orthogonal signal (Q) in the transmission data (TX) formed by the transmission data generator 1 is supplied to the orthogonal digital-analog converter 5. The in-phase side digital-analog conversion unit 4 converts the in-phase signal (I) supplied from the in-phase transmission data forming unit 2 into a transmission clock signal (TXC) supplied from the pulse width modulator 13.
3) Sampling is performed at the timing indicated by the arrow of the fourth waveform in FIG. 3 using the rising portion of I) to form an in-phase analog signal (AS · I) as indicated by the envelope of the same waveform. The quadrature-side digital-analog converter 5 converts the quadrature signal (Q) supplied from the quadrature transmission data generator 3 into a transmission clock signal (TXC) supplied from the pulse width modulator 13.
Instead of sampling at the timing shown by the arrow of the fifth waveform in FIG. 3 using the falling portion of Q) and forming a quadrature analog signal as shown by the dotted envelope of the same waveform, A quadrature analog signal (AS · Q) is formed as shown by the solid-line envelope of the waveform.

The in-phase analog signal (AS · I) output from the in-phase side digital-analog converter 4 is subjected to an in-phase side low-pass filter 6 to remove unnecessary frequency components.
The signal is supplied to the in-phase side frequency converter 8. Similarly, the quadrature analog signal (AS · Q) output from the quadrature digital-to-analog converter 5 is filtered by the quadrature low-pass filter 7 to remove unnecessary frequency components.
Supplied to The in-phase side frequency converter 8 mixes the frequency of the supplied in-phase analog signal (AS · I) and the carrier signal supplied from the local oscillator 10 to obtain a high-frequency signal as shown in the sixth waveform in FIG. A phase signal (RF.I) is generated. The quadrature-side frequency converter 9 receives the supplied quadrature analog signal (AS · Q) and the supplied 9
A 0 ° phase-shifted carrier signal is frequency-mixed, and a high-frequency quadrature signal (RF · Q) as shown in the waveform at the bottom of FIG.
Occurs. The high-frequency in-phase signal (RF · I) and the high-frequency quadrature signal (RF · Q) are added by the signal adding unit 11, and the added signals are transmitted through the transmitting antenna 15.

In this case, the threshold value supplied to the pulse width modulator 13 is adjusted to a suitable value, that is, the rising of the transmission clock signal (TXC · Q) supplied to the quadrature-side digital-analog conversion unit 5. If the arrival time of the downstream part is adjusted so as to be, for example, the time shown by the third waveform in FIG. 3, the signal delay of the in-phase signal side high-frequency circuit unit and the signal of the quadrature signal side high-frequency circuit unit Delays with each other, and the occurrence of a phase error between the added high-frequency in-phase signal (RF.I) and the high-frequency quadrature signal (RF.Q) can be eliminated, thereby reducing the bit error rate (BER). Can be prevented.

In the above-described embodiment, the transmission clock signal for adjusting the arrival position by the system clock signal is supplied to the orthogonal frequency converter 9 at the falling edge of the transmission clock signal (RFQ). Although the present invention has been described with an example, the present invention relates to a transmission clock signal (RF / Q).
The present invention is not limited to the method of adjusting the falling part of the transmission clock signal (RF.I). The rising part of the transmission clock signal (RF.I) may be adjusted.
If the falling part of I) and the rising part of the transmission clock signal (RF / Q) are selected, either one of the rising part and the falling part may be adjusted.

Also, in the above embodiment, an example has been described in which the frequency of the system clock signal is 256 times the frequency of the transmission clock signal. However, the frequency of the system clock signal and the transmission clock signal in the present invention are described. Is not limited to such an example, and may be any multiple as long as it is 30 times or more.

Further, the pulse width modulator 13 used in the present invention is not limited to the configuration shown in FIG. 2, but may have another configuration as long as it can achieve substantially the same function. Good.

[0038]

As described above, according to the present invention, the phase shift amount of one of the transmission clock signals is set by using the pulse width modulator. The change of the position of the rising portion or the falling portion of the transmission clock signal is changed by digital means according to the cycle of the system clock signal having a frequency considerably higher than the frequency of the transmission clock signal. Is not necessary, the set phase shift amount does not change due to a change in the surrounding environment or aging, and as a result, the bit error rate (BE)
R) can be prevented from deteriorating, and data and information can be transmitted accurately.
By using the adjustment by the digital means, there is an effect that the power consumption can be reduced as compared with the case of using the adjustment by the analog means.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a phase correction circuit for in-phase and quadrature signals according to the present invention, and showing a main part configuration thereof.

FIG. 2 is a block diagram showing an example of an internal configuration of the pulse width modulator shown in FIG.

FIG. 3 is a signal waveform diagram showing states of operation signals of respective parts of the in-phase and quadrature signal phase correction circuits shown in FIG. 1;

FIG. 4 is a signal waveform diagram showing states of operation signals of respective parts of the pulse width modulator shown in FIG.

FIG. 5 is a block diagram showing a main configuration of a phase correction circuit for in-phase and quadrature signals disclosed in Japanese Patent Application Laid-Open No. 2000-124963.

FIG. 6 is a signal waveform diagram showing states of operation signals of respective parts of the in-phase and quadrature signal phase correction circuits shown in FIG. 5;

[Explanation of symbols]

Reference Signs List 1 transmission data generation section (TX generation) 2 in-phase transmission data formation section (TX · I) 3 quadrature transmission data formation section (TX / Q) 4 in-phase side digital-analog conversion section (D / A · I) 5 quadrature side digital -Analog converter (D / A / Q) 6 In-phase low-pass filter (LF-I) 7 Quadrature-side low-pass filter (LF-Q) 8 In-phase frequency converter (MIX-I) 9 Quadrature-side frequency converter (MIX)・ Q) 10 Local oscillator (OSC) 11 Signal adder (ADD) 12 System pulse signal generator (SC generation) 13 Pulse width modulator (PWM) 13 ₁ frequency divider 13 ₂ counting unit 13 ₃ decision unit 13 ₄ signal Synthesizing unit 13 ₅ System pulse signal input terminal 13 ₆ , 13 ₇ Clock signal output terminal 13 ₈ Threshold value input terminal 14 Control unit (CPU) 15 Transmission antenna

Claims (4)

[Claims] 1. A first digital-to-analog converter for performing digital-to-analog conversion of an in-phase signal using a rising portion or a falling portion of a transmission clock signal, and a falling portion or a rising edge of a quadrature signal of the transmission clock signal. A second digital-analog converter that performs digital-analog conversion using the unit;
A pulse width modulator for changing the arrival time of a rising or falling part of any of the transmission clock signals by a system clock signal, and a high-frequency in-phase signal and a high-frequency A high-frequency conversion unit that converts the signal into a quadrature signal, wherein the pulse width modulator eliminates a phase error between the high-frequency in-phase signal and the high-frequency quadrature signal, and sets a rising portion or a rising edge of any of the transmission clock signals. A phase correction circuit for in-phase and quadrature signals, which adjusts the arrival position of a downlink. 2. A rising part or a falling part of one of the transmission clock signals is a falling part or a rising part of a transmission clock signal supplied to the second digital-analog converter. 2. The phase correction circuit for in-phase and quadrature signals according to claim 1, wherein 3. The phase correction of an in-phase signal and a quadrature signal according to claim 1, wherein the system clock signal has a frequency that is 30 times or more the frequency of the transmission clock signal. circuit. 4. A pulse width modulator that divides a system clock signal to generate a transmission clock signal, and counts the system clock signal by supplying a count start signal from the frequency divider. Counter, a count value discriminator that outputs a discrimination signal when the count value of the counter reaches a set count value, the transmission clock signal and the discrimination signal are supplied, and the transmission clock The signal in-phase according to any one of claims 1 to 3, further comprising: a signal combiner that generates a transmission clock signal in which a rising portion or a falling portion of the signal matches the supply timing of the determination signal. And a quadrature signal phase correction circuit.