JP2002353378A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress thermal stress occurring in a semiconductor element and a die bonding material without adjusting the physical characteristic values of constituent members in a semiconductor device for joining the semiconductor element to a lead frame through the die bonding material and sealing it in a mold resin. SOLUTION: Thickness of the die bonding material 13 joining the lead frame 11 and the semiconductor element 12 is 40 μm or more, preferably 70 μm or more. In other words, the thickness of the semiconductor element 12 is 200 μm or less. The thickness of the die bonding material 13 is 40 μm or more, preferably 70 μm or more, and the thickness of the semiconductor element 12 is 200 μm or less. The thermal stress occurring in the semiconductor element 12 and the die bonding material 13 is suppressed by thickening the die bonding material 13 or by thinning the semiconductor element 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a semiconductor element is joined to a lead frame via a die bonding material, and the semiconductor element is sealed in a molding resin.

[0002]

2. Description of the Related Art In a semiconductor device sealed with a mold resin, an initial intrinsic stress, an external thermal stress, or a thermal stress such as an exothermic fatigue is generated. Intrinsic stress is generated due to resin shrinkage due to cooling after resin molding and curing. The external thermal stress is generated due to a thermal stress due to a change in a use environment temperature or a thermal stress due to a temperature change when a semiconductor device is mounted on a wiring board. Heat generation fatigue is caused by repetition of heat generation due to ON / OFF of a semiconductor element. Such thermal stress is caused by deterioration of the thermal resistance characteristic due to fatigue of the die bonding material, aluminum electrode slide on the surface of the semiconductor element (a stress is applied from a resin to a silicon chip by a resin due to external environment and thermal stress, and is a wiring material on the chip. This causes problems such as sliding (moving) of aluminum), cracking of the chip protective film, or chip cracking. Therefore, in order to prevent the occurrence of these problems, conventionally, the physical properties of the molding resin, the lead frame, the semiconductor element, the die bonding material, etc., such as the coefficient of thermal expansion and the elastic modulus, are appropriately adjusted, and thereby the thermal stress is reduced. Is made smaller.

[0003]

However, as described above, when the physical properties such as the thermal expansion coefficient and the elastic modulus of the mold resin, the lead frame, the semiconductor element, the die bonding material, and the like are adjusted, the heat resistance and the heat resistance are reduced. There is a problem in that other characteristics such as conductivity and mechanical strength are reduced.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and has been made in consideration of the above-described problems, and relates to a semiconductor device in which a semiconductor element is joined to a lead frame via a die bonding material and the semiconductor element is sealed in a mold resin. It is an object of the present invention to provide a semiconductor device having a structure capable of suppressing a thermal stress generated in a semiconductor element or a die bonding material without adjusting a physical property value of a member constituting the semiconductor device.

[0005]

In order to achieve the above object, a semiconductor device according to the present invention has a die bonding material for joining a lead frame and a semiconductor element having a thickness of 40 mm.
μm or more, preferably 70 μm or more, or the thickness of the semiconductor element is 200 μm or less, or a combination thereof.

As described above, by increasing the thickness of the die bonding material or reducing the thickness of the semiconductor element, the thermal stress generated in the semiconductor element and the die bonding material is reduced.
The reason will be described using the model shown in FIG. This model is based on the first substance 1 (longitudinal elastic constant: E1,
Thermal expansion coefficient: α1, length: L, thickness: t1) and second substance 2 (longitudinal elastic constant: E2, thermal expansion coefficient: α2, length:
L, thickness: t2) with the joining material 3 (thickness: h). In this model, when G is a transverse elastic constant, the strain γ due to the temperature T is generally expressed by the following equation (1).

Γ = (L / 2) × ((α2-α1) ΔT / (√A × h)) (1) where A = (G / h) × ((1 / (E2 × t2) )) +
(1 / (E1 × t1)))

[0008] Here, the first substance 1 is a lead frame,
Assuming that the second substance 2 is a semiconductor element and the bonding material 3 is a die bonding material, the thickness (h) of the die bonding material is increased or the thickness of the semiconductor element ( If t2) is made smaller, or the die bonding material is made thicker and the semiconductor element is made thinner, the distortion (γ) due to temperature of the object in which the semiconductor element is joined to the lead frame by the die bonding material becomes smaller. Therefore, thermal stress generated in the object is reduced.

According to the present invention, since the thickness of the die bonding material is 40 μm or more, preferably 70 μm or more, thermal distortion and thermal stress generated in the semiconductor element and the die bonding material are reduced. Further, when the thickness of the semiconductor element is 20
Similarly, when the thickness is 0 μm or less, thermal distortion and thermal stress generated in the semiconductor element and the die bonding material are reduced. The thickness of the die bonding material is 40 μm or more, preferably 7
0 μm or more and the thickness of the semiconductor element is 200 μm
If it is less than the above, thermal strain and thermal stress generated in the semiconductor element and the die bonding material are further reduced.

[0010]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 2 is a longitudinal sectional view schematically showing an example of the semiconductor device according to the present invention. In this semiconductor device, a semiconductor element 12 is joined to a lead frame 11 by a die bonding material 13, which is sealed in a mold resin 14.

The thickness t3 of the semiconductor element 12 is 200 μm or less. Regarding the lower limit of the thickness of the semiconductor element 12,
Although there is no particular limitation, the stress generated when the semiconductor device is actually used is determined according to the stress that causes the semiconductor element 12 to be cleaved. That is, the semiconductor element 12 only needs to have at least a thickness such that the semiconductor element 12 is not cleaved by stress generated during actual use.

Although not particularly limited, for example, the semiconductor device 1
2 only needs to have a thickness of about 30 μm to 200 μm. Although the specific grounds for this numerical limitation will be described later, since the semiconductor element 12 has such a thickness, the semiconductor element 12 or the die bonding material 13 may be used.
The thermal stress generated at the time is smaller than before. For example, when the semiconductor element 12 is formed of a power device having a vertical structure, the conventional thickness of 500 μm is reduced to 200 μm.
By increasing the thickness, the on-resistance of the power device is reduced by 8% as compared with the related art.

The thickness t4 of the die bonding material 13 is 40
μm or more, preferably 70 μm or more. The specific basis for this numerical limitation will be described later. The die bonding material 13 has, for example, a thermal expansion coefficient of 20 ppm /
C. or higher, preferably 20 to 90 ppm / ° C. Although not particularly limited, as an example, Pb solder having a thermal expansion coefficient of 29.1 ppm / ° C., and a thermal expansion coefficient of 26.6
ppm / ° C Sn solder with a coefficient of thermal expansion of 28.7 ppm /
93.5Pb-5Sn-1.5Ag solder at 37 ° C., Sn-Ag solder having a thermal expansion coefficient of 37 ppm / ° C., thermal expansion coefficient of 8
Ag paste at 5 ppm / ° C. may, for example, be mentioned.

In the manufacturing process of the semiconductor device, in order to precisely control the die bonding material 13 to the above-described thickness, for example, the supply amount of the die bonding material 13 is increased or the supply of the die bonding material 13 is increased. The supply amount of the die bonding material 13 is optimized by performing the process twice, and the scrub direction and the interval between the semiconductor element 12 and the lead frame 11 are optimized.

Next, the reason for limiting the numerical values of the thickness of the semiconductor element 12 and the thickness of the die bonding material 13 will be described. In determining the effective range of these thicknesses,
The present inventors have conducted the following studies. First, the present inventors have proposed a so-called intelligent device in which a switch element composed of a vertical MOSFET having a drain-source voltage V _DSS of 30 V or more and a drain current of 1 A or more and a control IC are integrated on the same Si semiconductor substrate. ·power·
Various types of semiconductor devices having a size of 3.4 mm × 2.5 mm called switches were prepared by changing the thickness.

An intelligent power switch is a device in which an IC detects and protects against an abnormal condition such as a load short circuit by using an IC. The application of the intelligent power switch is to take measures against the abnormal condition on the unit side of the protection switch element. desired. For example, control of a hydraulic solenoid valve, which is an electrical component of an automobile, control of a lamp, and the like are performed.

Then, these semiconductor elements are bonded to a lead frame by changing the thickness of the die bonding material in various ways,
An SOP-8 package (a typical surface mount package) obtained by resin molding them was prepared as a sample. The lead frame is made of nickel plated copper, and the size of the bonding portion is 3.8 mm × 2.
The thickness was 6 mm and the thickness was 0.15 mm. 93.5 Pb-5Sn-1.5Ag solder (thermal expansion coefficient: 28.7 ppm / ° C.) was used as a die bonding material.

For the prepared sample, ΔTc = 90
A power cycle test was performed under the conditions of 1 ° C., ON and OFF for 60 seconds and 1 W applied. Then, in order to evaluate the heat generation fatigue due to the repetitive plastic deformation of the die bonding material due to the repetition of internal heat generation during the power cycle test, the thermal resistance after a power cycle of 40,000 cycles was measured, and at the start of the power cycle test (power cycle 0).
Cycle), and the rate of change was determined. Note that there is no relationship between the switching characteristics of the MOSFET and the occurrence of thermal stress.

First, the thickness of the die bonding material is set to 40.
The reason for setting the thickness to μm or more will be described. Semiconductor device thickness 2
FIG. 3 shows the results of power cycle tests performed on a plurality of samples having a thickness of 00 μm and different thicknesses of the die bonding material. FIG. 3 shows the thickness of the die bonding material obtained by the power cycle test and the power cycle 4
FIG. 10 is a characteristic diagram showing a relationship with a thermal resistance change rate after 0000 cycles.

Here, as a failure criterion for the power cycle test, if a criterion that the thermal resistance increases by 20% or more after a power cycle of 40000 cycles is determined to be defective, the thickness of the die bonding material is clearly shown in FIG. It can be seen that a power cycle tolerance of 40,000 cycles can be achieved if the thickness is 40 μm or more. In addition, if the die bonding material becomes thicker, 40,000
It can be seen that a power cycle capability exceeding the cycle can be achieved.

For example, as shown in FIG. 3, if the thickness of the die bonding material is 70 μm or more, power cycle 4000
The rate of increase in thermal resistance after 0 cycles is about 11% or less. When the thickness of the die bonding material is 90 μm or more, the rate of increase in thermal resistance after 40000 power cycles is about 8% or less. If the thickness of the die bonding material is 100 μm or more, the rate of increase in thermal resistance after 40000 power cycles is approximately 6
% Or less. From this, it is understood that if the thickness of the die bonding material is 70 μm or more, it is possible to guarantee a power cycle resistance of 40000 cycles.

Another reason for setting the thickness of the die bonding material to 40 μm or more will be described. FIGS. 4 to 8 show that the thickness of the die bonding material is 20 μm (FIG. 4), and the thickness is 30 μm (FIG. 5), 40 μm (FIG. 6), and 50 μm which are the same as the conventional thickness.
(FIG. 7), 70 μm (FIG. 8) and 100 μm (FIG. 9)
Is a simulation result of the distribution of stress σyy at the interface between the semiconductor element and the die bonding material. From this result, the thickness of the conventional die bonding material is 30 μm, but the vertical stress at this thickness is 4.5 μm.
whereas a kgf / mm ^2, for example, when the thickness of the die bonding material and 100 [mu] m, the normal stress 3.
9 kgf / mm ² , indicating that the vertical stress is reduced by 13%. This increases the power cycle capability by two more.
This is equivalent to the effect of improving 0000 cycles.

In consideration of the process capability in actually manufacturing the semiconductor device, if 6 σ is set as an allowable range, if the design value of the thickness of the die bonding material is set to 100 μm, and if the die bonding material is manufactured, Even if the thickness varies in the direction in which the thickness becomes the smallest, a thickness of 40 μm can be secured. Therefore, the design value of the thickness of the die bonding material is set to 100 μm, and the thickness of the die bonding material in the semiconductor device actually manufactured is set to 40 μm.
It is appropriate that the thickness be at least μm.

The grounds for setting the thickness of the semiconductor element to 200 μm or less will be described. 100μm thickness of die bonding material
FIG. 10 shows the results of a power cycle test performed on a plurality of samples having different thicknesses of the semiconductor element, where m is a number. FIG. 10 is a characteristic diagram showing the relationship between the thickness of the semiconductor element obtained by the power cycle test and the rate of change in thermal resistance after 40000 power cycles. As is clear from FIG. 10, as the semiconductor element becomes thinner, the rate of change in thermal resistance becomes smaller, and the power cycle capability is improved.

FIGS. 11 to 13 show that the thickness of the semiconductor element is 180 μm (FIG. 11), 240 μm (FIG. 12) and 280 μm (FIG. 13) having the same thickness as that of the conventional semiconductor element. Σy at the interface of
It is a result of simulating the distribution of y. From this result, the thickness of the conventional semiconductor device is 280 μm,
While the vertical stress at this thickness is 4.4 kgf / mm ² , for example, the thickness of the semiconductor element is 180 μm
Then, the vertical stress is 4.1 kgf / mm ² , which indicates that the vertical stress is reduced by 6%. This is equivalent to the effect of further improving the power cycle capability by 10,000 cycles.

Incidentally, only one of the semiconductor element and the die bonding material may satisfy the above-described thickness range, or both may have a thickness within the above-described range. However, the thickness of the die bonding material is 70μ.
m or more, in order to ensure a power cycle capability of 40,000 cycles or more, the thickness of the semiconductor element must be 20 or more.
It needs to be 0 μm or less.

According to the above-described embodiment, the thickness of the die bonding material 13 is 40 μm or more, preferably 70 μm.
m or more, thermal distortion and thermal stress generated in the semiconductor element 12 and the die bonding material 13 are reduced. Also,
Even when the thickness of the semiconductor element 12 is 200 μm or less, thermal distortion and thermal stress generated in the semiconductor element 12 and the die bonding material 13 are reduced. Die bonding material 1
3 is 40 μm or more, preferably 70 μm or more, and the thickness of the semiconductor element 12 is 200 μm or less.
3, the thermal strain and thermal stress generated in the substrate 3 are reduced. Therefore, the heat generated in the semiconductor element 12 and the die bonding material 13 can be adjusted without adjusting the physical property values of the members constituting the semiconductor device, such as the die bonding material 13, the lead frame 11, the semiconductor element 12, and the mold resin 14. Stress can be suppressed.

In the above, according to the present invention, the semiconductor device is an SO
Not limited to surface mount devices using P-8 package,
The present invention can be widely applied to a semiconductor device having a structure in which a semiconductor element 12 and a lead frame 11 are joined by a die bonding material 13. Further, in the embodiment, the description has been given of the example of the heat generation fatigue. However, the present invention is effective not only for the heat generation fatigue but also for suppressing the internal stress and the external heat stress. The semiconductor element is effective not only for an intelligent power switch but also for a switching element such as a single MOSFET or a bipolar transistor or a diode.

[0029]

According to the present invention, since the thickness of the die bonding material is 40 μm or more, preferably 70 μm or more, or the thickness of the semiconductor element is 200 μm or less, the thickness of the semiconductor element or the die bonding material is reduced. Thermal strain and thermal stress are reduced. Die bonding material thickness is 4
When the thickness is 0 μm or more, preferably 70 μm or more, and the thickness of the semiconductor element is 200 μm or less, thermal distortion and thermal stress generated in the semiconductor element and the die bonding material are further reduced. Therefore, such as die bonding material, lead frame, semiconductor element and mold resin,
The thermal stress generated in the semiconductor element and the die bonding material can be suppressed without adjusting the physical property values of the members constituting the semiconductor device.

[Brief description of the drawings]

FIG. 1 is a schematic diagram showing a model of an object in which two substances are joined by a joining material.

FIG. 2 is a longitudinal sectional view schematically showing an example of a semiconductor device according to the present invention.

FIG. 3 is a characteristic diagram showing a relationship between a thickness of a die bonding material obtained by a power cycle test and a rate of change in thermal resistance.

FIG. 4 shows a stress σy at an interface between a semiconductor element and a die bonding material (the thickness of the die bonding material is 20 μm).
FIG. 9 is a characteristic diagram showing a result of simulating the distribution of y.

FIG. 5 shows a stress σy at an interface between a semiconductor element and a die bonding material (the thickness of the die bonding material is 30 μm).
FIG. 9 is a characteristic diagram showing a result of simulating the distribution of y.

FIG. 6 shows a stress σy at an interface between a semiconductor element and a die bonding material (the thickness of the die bonding material is 40 μm).
FIG. 9 is a characteristic diagram showing a result of simulating the distribution of y.

FIG. 7 shows a stress σy at an interface between a semiconductor element and a die bonding material (the thickness of the die bonding material is 50 μm).
FIG. 9 is a characteristic diagram showing a result of simulating the distribution of y.

FIG. 8 shows a stress σy at an interface between a semiconductor element and a die bonding material (the thickness of the die bonding material is 70 μm).
FIG. 9 is a characteristic diagram showing a result of simulating the distribution of y.

FIG. 9 shows a stress σ at an interface between a semiconductor element and a die bonding material (the thickness of the die bonding material is 100 μm).
It is a characteristic view showing the result of having simulated the distribution of yy.

FIG. 10 is a characteristic diagram showing a relationship between a thickness of a semiconductor element obtained by a power cycle test and a rate of change in thermal resistance.

FIG. 11 shows a semiconductor element (the thickness of the semiconductor element is set to 180 μm).
m) and the stress σyy at the interface between the die bonding material
FIG. 9 is a characteristic diagram showing a result of simulating the distribution of.

FIG. 12 shows a semiconductor element (the thickness of the semiconductor element is 240 μm).
m) and the stress σyy at the interface between the die bonding material
FIG. 9 is a characteristic diagram showing a result of simulating the distribution of.

FIG. 13 shows a semiconductor element (the thickness of the semiconductor element is 280 μm).
m) and the stress σyy at the interface between the die bonding material
FIG. 9 is a characteristic diagram showing a result of simulating the distribution of.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Lead frame 12 Semiconductor element 13 Die bonding material 14 Mold resin

Continuation of the front page (72) Inventor Yoshinari Ikeda 1-1, Tanabe-Nitta, Kawasaki-ku, Kawasaki-shi, Kanagawa Prefecture F-term in Fuji Electric Co., Ltd. 4M109 AA01 BA01 CA21 DB14 DB17

Claims (3)

[Claims] 1. A semiconductor device in which a semiconductor element is joined to a lead frame via a die bonding material and sealed in a mold resin, wherein the thickness of the die bonding material is 40 μm or more. Semiconductor device. 2. A semiconductor device in which a semiconductor element is bonded to a lead frame via a die bonding material, and the semiconductor element is sealed in a mold resin, wherein the thickness of the semiconductor element is 200 μm or less. Semiconductor device. 3. A semiconductor device in which a semiconductor element is joined to a lead frame via a die bonding material, and the semiconductor element is sealed in a mold resin, wherein the thickness of the die bonding material is 40 μm or more, A semiconductor device having a thickness of 200 μm or less.