JP2002353084A - Information processing system and information processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To create and provide information effective for both sides, by integrating the information about both fables and fab. SOLUTION: A computer unit (60) connectable with a network (18) receives the input of the element property information of a semiconductor element from fab (10-12) and also receives the input of design information of a semiconductor integrated circuit from fabless (13-16) via a network, and creates the response information requested by a request source concerned, based on the above input information, in response to the request from the supply source of the above design information, and returns the created response information to the requesting source. For example, the response information is the forecast yield information, at the time of having supposed that the semiconductor integrated circuit is constituted, making use of the element specified by the element property information. Hereby, the fables can know beforehand the yield of products at the time of having placed an order with the fab with products, and it enables easy for proper selection of the fab.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for integrating both information in a situation where a fabless for designing a semiconductor integrated circuit and a fab for manufacturing a semiconductor integrated circuit are operated as separate companies, and information effective for both is provided. TECHNICAL FIELD The present invention relates to an information processing system and an information processing method for generating and providing an application, and relates to a technology effective when applied to a network business or E-commerce via the Internet, for example.

[0002]

2. Description of the Related Art There is a situation in which fabs and fabless companies are operated as separate companies due to the division of operations in the semiconductor integrated circuit industry. The present inventor has disclosed, as an individual technique for improving the yield of semiconductor integrated circuit products, Japanese Patent Application Laid-open No.
000-322456 and Japanese Patent Application No. 2000-106695. The former proposes a method of generating intermediate data from measured device characteristics (such as IV characteristics) and extracting model parameters for circuit simulation from the data. The latter proposes a method of extracting model parameters for circuit simulation from the measured saturation current and threshold value of the MOS transistor.

[0003]

The inventor of the present invention pays attention to the situation in which fab and fabless are operated as separate companies. Before fabless requests fab to manufacture an LSI, one of the information is mutually exchanged. Found that there are cases where it is advantageous to know. For example, it would be convenient if the fabless could obtain the information necessary to determine which fab to order the product in terms of cost and time.
In addition, for fabless, cost reduction and Q
In order to achieve TAT (Quick Turn Around Time), it may be better to consider the relationship with the device characteristics, and it is preferable to obtain the device characteristics of the fab. In the case of fabless, if device characteristics necessary for determining device parameters for circuit simulation used in circuit design can be obtained from the fab, circuit simulation using a fab device that is a candidate for manufacturing request becomes possible. In some cases, it is better for the fab to consider a measure to increase the yield in consideration of the relationship with the circuit characteristics, and it is preferable that information on the benchmark circuit of the LSI to be ordered by the fabless can be obtained in advance.

Further, the present inventor has noted that it is not sufficient for a fab and a fabless to simply obtain one piece of information from each other as it is. That is, it takes time and cost to process or convert the obtained information, and necessary information cannot be obtained in a timely manner.

An object of the present invention is to provide an information processing system and an information processing method for integrating information of both fabless and fab to generate and provide effective information for both.

Another object of the present invention is to convert fabless or fab information into information that is valid for the other, or to add information that is valid for the other to the one information,
An object of the present invention is to provide an information processing system and an information processing method to be provided.

Still another object of the present invention is to convert information of one of fabless and fab into information effective for the one,
Another object of the present invention is to provide an information processing system and an information processing method for providing the one piece of information with added value.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0009]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

[1] (Fb, Fl → KMS → Fb) First
In the information processing system according to the aspect, a computer device (KMS) such as a knowledge management server inputs information from a fab (Fb) and a fabless (Fl), and returns response information generated based on the information to the fab (Fb). .

In short, the information processing system has a computer device (KMS) connectable to a transmission line, and the computer device transmits, via the transmission line, element characteristic information of a semiconductor element from, for example, a fab (Fb). At the same time, the design information of the semiconductor integrated circuit is input to the fabless (F
1), and in response to a request from a source (Fb) of the element characteristic information, generates response information required by the request source based on the input information, and generates the generated response information in the request. It is possible to execute the return process. A plurality of fabs and fabless may be connected to the transmission path and arranged.

In a more specific aspect, the computer device receives element characteristic information of a semiconductor element and design information of a semiconductor integrated circuit via the transmission path, and receives the element characteristic information from a supply source (Fb) of the element characteristic information. In response to the request, the response information to the request source, assuming the use of the element specified by the element characteristic information in the semiconductor integrated circuit is generated,
A process of returning the generated response information to the request source can be executed.

(Wafer unit price) The response information is provided by predicted yield information and a design information supply source of the semiconductor integrated circuit when it is assumed that the semiconductor integrated circuit is formed using the element specified by the element characteristic information. Wafer unit price information generated based on the chip unit price information to be processed. As a result, the fab can know the wafer unit price that matches the balance of the chip unit price desired by the fabless.

(Lot input timing) The response information includes time-series element characteristic information (device variation data, wiring variation data, foreign matter data) of the semiconductor element, and the necessity of the semiconductor integrated circuit given from the supply source of the design information. It may include information on the required amount of the semiconductor integrated circuit and the lot introduction time that satisfies the delivery date, which is formed based on the quantity and the production delivery date. As a result, the required number of fabs can be manufactured with a small number of wafers, which contributes to cost reduction.

[2] (Fb, Fl → KMS → Fl) Second
The information processing system according to the aspect is a computer device (KM
S) inputs information from the fab (Fb) and the fabless (Fl), and returns response information generated based on the information to the fabless (Fl). A plurality of fabs and fabless may be connected to the transmission path and arranged.

In short, the information processing system has a computer device connectable to a transmission line, and the computer device receives element characteristic information of a semiconductor element and design information of a semiconductor integrated circuit via the transmission line. Executing, in response to a request from the design information supply source (Fl), response information to the request source based on the received information, and returning the generated response information to the request source. It is possible.

In a more specific aspect, the computer device receives element characteristic information of a semiconductor element and design information of a semiconductor integrated circuit via the transmission path, and receives the design information from a supply source (Fl) of the design information. In response to the request, response information to the request source is generated on the assumption that the element specified by the element characteristic information is used in the semiconductor integrated circuit, and the generated response information is returned to the request source. Processing can be performed.

(Product Yield) The response information may include predicted yield information when it is assumed that the semiconductor integrated circuit is configured using the elements specified by the element characteristic information. As a result, the fabless can know in advance the product yield at the time of ordering the product to each fab, and can appropriately select the fab.

(Chip Unit Price) The response information may include chip unit price information generated based on the predicted yield information and wafer unit price information presented by the element characteristic information supplier. This allows the fabless to perform a circuit simulation using the device parameters to confirm the characteristics or performance when each fab is requested to manufacture a product, and to provide an appropriate fab that can manufacture a product that meets the performance specifications. Can be selected.

(Yield Improvement Measure: FIG. 10)
It may include information on a layout structure for a semiconductor integrated circuit for improving variation in circuit characteristics of a benchmark circuit provided from a supply source of the design information. This allows the fabless to review the layout design so that the yield can be improved with reference to the improved layout.

(Line placement: FIG. 12) The response information is
The chip unit price information obtained from the wafer unit price information provided from the source of the predicted yield information and the design information of the semiconductor integrated circuit, and the congestion state of the manufacturing line and the throughput of the manufacturing line provided from the source of the device characteristic information And the completion time of the required wafer obtained based on the information. As a result, the fabless can select a fab that can manufacture a product at an appropriate price and with a desired delivery date.

[3] (Fb → KMS → Fl) In the information processing system according to the third aspect, a computer device (KMS) inputs information from a fab (Fb) via a transmission path, and a response generated based on the information is input. Information (device parameters,
Fabless (F
Return to l). A plurality of fabs and fabless may be connected to the transmission path and arranged.

In short, the information processing system has a computer device that can be connected to a transmission line, and the computer device can receive element characteristic information of a semiconductor device via the transmission line. In response to a request via the device element, generates device parameters for simulating the element characteristics specified by the received element characteristic information, and returns the generated device parameters to the request source via the transmission path. It is possible. This allows the fabless to perform a circuit simulation using the device parameters to confirm the characteristics or performance when the fab is requested to manufacture a product, and to select an appropriate fab that can manufacture a product that meets the performance specifications. It becomes possible to choose.

Also, the computer device can receive element characteristic information of an existing semiconductor element and element conditions of an unknown semiconductor element via the transmission path, and can transmit the transmission path from a semiconductor integrated circuit design source. A pre-silicon device parameter for simulating the device characteristics of the unknown semiconductor device based on the input device characteristics information and the device conditions in response to a request through the transmission line. And a process of returning the request to the request source can be executed. This allows the fabless to simulate the circuit using device parameters before the fab develops the device, and to check the performance of the characteristics when the fab was ordered to manufacture the product at an early stage, It is possible to appropriately select a fab that can produce a product that meets performance specifications.

[4] (Fb → KMS → Fb) In the information processing system according to the fourth aspect, a computer device (KMS) receives information from a fab (Fb) via a transmission line and generates a response based on the information. Return information to fab (Fb). A plurality of fabs and fabless may be connected to the transmission path and arranged.

In short, the information processing system has a computer device connectable to a transmission line, and the computer device receives, via the transmission line, element characteristic information of a semiconductor element and benchmark circuit information using the element. , The source of the device characteristic information and the benchmark circuit information (F
In response to the request from b), a process of returning response information obtained assuming that a benchmark circuit is configured using the element specified by the element characteristic information to the requestor can be executed.

(Yield Improvement Measure: FIG. 9) The response information includes information on a process condition and a device structure for a semiconductor element for improving variation in circuit characteristics of the benchmark circuit. This allows fabs to increase yield and reduce rejects, leading to increased sales.

[5] (Ln (2nd), Dg → KMS (1st) →
Ln (2nd)) In the information processing system according to the fifth aspect, the fab has a first computer device (KMS (1st)) and a second computer device (Ln (2nd)), and the first computer device is the fab device. 2) Input information from the computer device and the fabless computer device (Dg), and return response information generated based on the information to the fab second computer device.

In short, the information processing system has a first computer device connectable to a transmission path and a second computer device connected to the first computer device, wherein the first computer device is connected to the second computer. Device characteristic information of a semiconductor element is input from the device, design information of the semiconductor integrated circuit is received via the transmission line, and in response to a request from the second computer (Ln (2nd)), It is possible to execute a process of generating response information based on the input information and returning the generated response information to the requesting second computer.

In a more specific aspect, the first computer device inputs device characteristic information of a semiconductor device from the second computer device, receives design information of a semiconductor integrated circuit via the transmission line, and 2 computers (L
n) in response to the request from n), generating response information to the requesting source assuming that the element specified by the element characteristic information is used in the semiconductor integrated circuit; A process of returning to the requesting second computer can be executed.

[0031] The transmission line may include a plurality of third computer devices capable of outputting the design information. The third computer device is owned by Fabless.

[6] (Ln (2nd), Dg → KMS (1st) →
Dg) In the information processing system according to the sixth aspect, the fab has a first computer device (KMS (1st)) and a second computer device (Ln (2nd)), and the first computer device is a second computer device of the fab. And information from the fabless computer device (Dg), and response information generated based on the information is input to the fabless computer device (Dg).
Return to g).

In short, the information processing system has a first computer device connectable to a transmission path and a second computer device connected to the first computer device, wherein the first computer device is connected to the second computer device. Device characteristic information of a semiconductor element is input from a device, design information of a semiconductor integrated circuit is received via the transmission path, and a response to a request from a supply source (Dg) of the design information is provided. It is possible to execute a process of generating information based on the input information and returning the generated response information to the request source.

In a more specific aspect, the first computer device inputs device characteristic information of a semiconductor device from the second computer device and receives design information of a semiconductor integrated circuit via the transmission line, In response to a request from a design information supply source (Dg), response information to the request source is generated on the assumption that an element specified by the element characteristic information is used in the semiconductor integrated circuit, and the generation is performed. A process of returning the response information to the request source can be executed.

[0035] The transmission line may include a plurality of third computer devices capable of outputting the design information. The third computer device is owned by Fabless.

(Product Yield) The response information may include predicted yield information assuming that the semiconductor integrated circuit is configured using the element specified by the element characteristic information.
As a result, the fabless can know in advance the product yield when the product is ordered from the fab, and can appropriately select the fab.

(Chip Unit Price) The response information may include chip unit price information generated based on the predicted yield information and wafer unit price information presented by the element characteristic information supplier. As a result, the fabless can know in advance the cost of ordering the product to the fab from the chip unit price, and can reduce the cost and increase the profit by selecting an appropriate fab from the fabs.

[7] (Ln (2nd) → KMS (1st) → Dg)
In the information processing system according to the seventh aspect, the fab has a first computer device (KMS (1st)) and a second computer device (Ln (2nd)), and the first computer device receives information from the second computer device of the fab. And returns response information (device parameters, pre-silicon device parameters) generated based on the input to the fabless computer apparatus (Dg).

In short, the information processing system has a first computer device connectable to a transmission path and a second computer device connected to the first computer device, wherein the first computer device is connected to the second computer device. Device characteristic information of a semiconductor element can be input from the apparatus, and in response to a request from a transmission line, device parameters for simulating the element characteristic specified by the input element characteristic information are generated, and the generated device is generated. A process of returning a parameter to the request source can be executed. This allows the fabless to perform a circuit simulation using the device parameters to confirm the characteristics or performance when the fab is requested to manufacture a product, and to select an appropriate fab that can manufacture a product that meets the performance specifications. It becomes possible to choose.

Further, the first computer device can input element characteristic information of the first semiconductor device and element conditions of the second semiconductor device from the second computer device, and respond to a request from a transmission line. A pre-silicon device parameter for simulating the device characteristics of the second semiconductor device is generated based on the input device characteristics information and the device condition, and the generated pre-silicon device parameter is transmitted through the transmission path to the request. It is possible to execute the return process. This allows the fabless to simulate the circuit using device parameters before the fab develops the device, and to check the performance of the characteristics when the fab was ordered to manufacture the product at an early stage, It is possible to appropriately select a fab that can produce a product that meets performance specifications.

[0041] The transmission line may include a plurality of third computer devices capable of outputting the request. The third computer device is owned by Fabless.

[8] (Ln, Dg (3rd) → KMS (1st) →
Ln) The information processing system according to the eighth aspect, wherein the fabless has a first computer device (KMS (1st)) and a third computer device (Dg (3rd)), and the first computer device is a fabless third computer device. (Dg (3rd))
And input information from the fab computer device (Ln), and return response information generated based on the information to the fab computer device (Ln).

In short, the information processing system has a first computer device connectable to a transmission line and a third computer device connected to the first computer device, wherein the first computer device connects to the transmission line. Receiving the element characteristic information of the semiconductor element via the third computer device, inputting the design information of the semiconductor integrated circuit from the third computer device, and responding to the request from the element characteristic information supply source (Ln), A process of generating response information based on the received information and the input information and returning the generated response information to the request source can be executed.

In a more specific aspect, the first computer device receives device characteristic information of a semiconductor device via the transmission line, inputs design information of a semiconductor integrated circuit from the third computer device, and In response to a request from a characteristic information supply source (Ln), response information to the request source is generated on the assumption that an element specified by the element characteristic information is used in the semiconductor integrated circuit. A process of returning the response information to the request source can be executed.

[0045] The transmission line may include a plurality of second computer devices capable of outputting the element characteristic information. The second computer device is owned by the fab.

(Wafer unit price) The response information is provided by predicted yield information and a design information supply source of the semiconductor integrated circuit when it is assumed that the semiconductor integrated circuit is manufactured according to a technology level represented by the element characteristic information. It may include wafer unit price information generated based on the chip unit price information. As a result, the fab can know the wafer unit price that matches the balance of the chip unit price desired by the fabless.

(Lot input timing) The response information includes time-series element characteristic information (device variation data, wiring variation data, foreign matter data) of the semiconductor element, and the necessity of the semiconductor integrated circuit given from the supply source of the design information. Based on the quantity and the production delivery date, the information may include information on a lot introduction time that satisfies the delivery date and the number of the semiconductor integrated circuits. As a result, the required number of fabs can be manufactured with a small number of wafers, which leads to cost reduction.

[0048]

[9] (Ln → KMS (1st) → Ln) 9th
In the information processing system according to the aspect, the fabless has a first computer device (KMS (1st)) and a third computer device (Dg (3rd)), and the first computer device receives information from the fab computer device (Ln). And responds to the fab computer device (Ln) with response information generated based on the input.

In short, the information processing system has a first computer device that can be connected to a transmission line and a third computer device that is connected to the first computer device. Device information and benchmark circuit information using the device via the element characteristic information, and specified by the element characteristic information in response to a request from a source (Ln) of the element characteristic information and the benchmark circuit information. A process of returning response information obtained assuming that a benchmark circuit is configured using elements to the request source can be executed.

[0050] The transmission path may include a plurality of second computer devices capable of outputting the element characteristic information and the benchmark circuit information. The second computer device is owned by the fab.

(Yield Improvement Measure: FIG. 9) The response information may include information on a process condition and a device structure for a semiconductor element for reducing variation in circuit characteristics of the benchmark circuit. As a result, the fab can increase the yield and reduce defective products.

[10] (Ln, Dg (3rd) → KMS (1st)
→ Dg) In the information processing system according to the tenth aspect, the fabless has a first computer device (KMS (1st)) and a third computer device (Dg (3rd)), and the first computer device is a fabless third computer. Equipment (Dg (3r
d)) and information is input from the fab computer device (Ln), and response information generated based on the information is returned to the fabless third computer device (Dg (3rd)).

In short, the information processing system has a first computer device connectable to a transmission line and a third computer device connected to the first computer device, and the first computer device is connected via the transmission line. Receiving the device characteristic information of the semiconductor device, inputting the design information of the semiconductor integrated circuit from the third computer device, and responding to the request from the third computer device, It is possible to execute a process of generating the response information based on the received information and the input information and returning the generated response information to the requesting third computer device.

In a more specific aspect, the first computer device receives device characteristic information of a semiconductor device via the transmission line, inputs design information of a semiconductor integrated circuit from the third computer device, and (3) Response information generated by responding to a request from a computer device, assuming that the element specified by the element characteristic information is used for the semiconductor integrated circuit, Is returned to the requesting third computer device.

[0055] The transmission line may include a plurality of second computer devices capable of outputting the element characteristic information. The second computer device is owned by the fab.

[11] (Estimated Yield Information) The information processing method according to the present invention comprises a process of inputting element characteristic information of a semiconductor element from a fab server having a semiconductor integrated circuit manufacturing line via a network; A process of inputting design information of a semiconductor integrated circuit from a fabless server for designing an integrated circuit through a network, and based on the input device characteristic information and design information, manufacturing a product required by the fabless in the fab. Generating predicted yield information of the product under the assumption.

(Wafer Unit Price Information) A process for generating wafer unit price information based on the predicted yield information and the chip unit price information presented from the fabless may be further included.

(Chip Unit Price) A process for generating chip unit price information based on the predicted yield information and wafer unit price information presented from the fab may be further included.

(Line Incorporation) A process for estimating the completion time of a required wafer based on the production line congestion state and the production line throughput input from the fab server, and sending the chip unit price information and the completion time information to a network. And supplying the information to a fabless server via the server.

(Lot input timing) Time-series element characteristic information (device variation data, wiring variation data, foreign matter data) of the semiconductor device input from the fab server,
The method may further include, based on the required amount of the semiconductor integrated circuit and the delivery date of the semiconductor integrated circuit input from the fabless server, generating information on a lot input time satisfying the delivery date and the number of the semiconductor integrated circuits.

(Device Parameter) In another information processing method according to the present invention, there is provided a process of inputting element characteristic information of a semiconductor element from a fab server having a semiconductor integrated circuit production line via a network; A process of generating device parameters required for a circuit simulation for performing a circuit design based on the characteristic information;
Supplying the generated device parameters to a fabless server for designing a semiconductor integrated circuit via a network.

(Pre-Silicon Device Parameter) Still another information processing method according to the present invention is directed to a method of manufacturing a semiconductor integrated circuit. Processing for inputting element conditions of a semiconductor element, processing for generating pre-silicon device parameters for simulating element characteristics of the second semiconductor element based on the input element characteristic information and the element conditions, Supplying the generated pre-silicon device parameters to a fabless server that designs a circuit via a network.

(Yield Improvement Measure: FIG. 10) Still another information processing method according to the present invention is a process of inputting element characteristic information of a semiconductor element from a fab server having a semiconductor integrated circuit manufacturing line via a network. And a process of inputting design information of the semiconductor integrated circuit from a fabless server that designs the semiconductor integrated circuit via a network, and based on the input device characteristic information and design information, a benchmark circuit included in the design information. The method includes a process of generating improvement measure information on a device structure for improving the variation in circuit characteristics, and a process of supplying the generated improvement measure information to the fabless server via a network.

(Yield Improvement Measure: FIG. 9) In still another information processing method according to the present invention, device characteristic information of a semiconductor device and its semiconductor device are transmitted from a fab server having a semiconductor integrated circuit manufacturing line via a network. Based on the input device characteristic information and the benchmark circuit information, and based on the input device characteristic information and the benchmark circuit information, improve process information and process condition information for a semiconductor device for improving circuit characteristic variation of the benchmark circuit. And a process of supplying the generated improvement measure information to a server of the fab via a network.

[0065]

DESCRIPTION OF THE PREFERRED EMBODIMENTS << System Configuration >> FIG. 1 illustrates an information processing system according to the present invention connected to a network. A network 18 such as the Internet includes a plurality of fabs (Fb) 10, 1
1,12, multiple fabless (Fl) 13,14,1
5, 16 and the service provider 17 are connected.

Fab (also referred to as foundry) 10
Reference numeral 12 denotes an organization that manufactures a semiconductor integrated circuit (LSI), for example, an LSI to be manufactured together with an LSI manufacturing request from another company.
Means the semiconductor integrated circuit manufacturing company that receives the circuit design data or the design data such as the layout pattern data, and manufactures the LSI and delivers it to the request source. FIG.
According to the above, each of the fabs 10 to 12 has LSI manufacturing lines 20 to 22, measuring instruments 30 to 32, and line data servers 40 to 42. The measuring instruments 30 to 32
Is a general term for means for measuring characteristics of devices (for example, MOS transistors) included in LSIs manufactured on the corresponding manufacturing lines 20 to 22. Line data server 30
The devices 32 to 32 hold and manage device characteristics and the like measured by the measuring devices 30 to 32 as line data.

The fabless circuits 13 to 16 mean an organization that designs LSIs, for example, a semiconductor integrated circuit design company that does not have an LSI manufacturing department. The fabless 13-16
Has design data servers 50 to 53 for storing and managing data of LSIs designed in the organization.

The service provider 17 is connected to the line data servers 40 to 42 and the design data servers 50 to 53 via the Internet 18, and is capable of exchanging information with both the knowledge management server (K).
MS) 60. Knowledge Management Server 60
Are the fabs 10-1 from the line data servers 40-42.
2 obtains information on devices to be manufactured, and obtains information on LSI chips designed by the fabless 13-16 from the design data servers 50-53. In order to obtain such information, service provider 17 must provide fab 1
Information necessary for providing a service is directly or indirectly obtained from the fabs 10 to 12 and the fabless 13 to 16 according to the agreement between the fabs 10 to 12 and the fabless 13 to 16.
Each of the servers 40 to 42, 50 to 53, and 60 is realized by a computer device such as a personal computer or an engineering workstation having an Internet connection function, an information processing function, and an information storage function.

Then, the knowledge management server 60
Manages information obtained from the fabs 10 to 12 and the fabless 13 to 16 and integrates information from both to generate or process information that is valid for both. The generated information and the processed information are 10-12 and fabless 1
A service provided in response to a request from 3 to 16 is performed.

This service is provided by processing one of the fabs 10 to 12 and the fabless 13 to 16 in a form effective for the other and providing the processed information to the other, and obtaining the information from both the fab 10 to 12 and the fabless 13 to 16 Integrated information and generate and provide effective information to the other in consideration of one situation. For example, in FIG. 1, the knowledge management server 60 performs a process of providing product yield information SV.
1. Providing process SV2 for providing a proper wafer and chip unit price, providing process SV3 for providing device parameters for circuit design, providing process SV4 for providing pre-silicon device parameters for circuit design, providing process SV5 for providing a measure for improving line yield, SV6 for providing a line, And lot input timing data provision processing SV
7 is performed.

The product yield information providing process SV1 is based on the device information obtained from the line data servers 40-43 of the fabs 10-12 and the design data obtained from the design data servers 50-53 of the fabless 13-16. , Fabless products required by 13-16 fab 10-12
This is a process of generating product yield information when it is assumed that the device is manufactured in the manner described above, and providing it to service request sources in the fabless 13 to 16 (design data servers 50 to 53).

Appropriate wafer / chip unit price providing process SV2
Is a process for generating and providing information on a wafer price or a chip price when an LSI is manufactured by the fabs 10 to 12.

The circuit design device parameter providing process SV3 generates device parameters for circuit simulation necessary for the fabless 13 to 16 to perform circuit design based on the data of the line data servers 40 to 42, and ~ 16 (data server 50 ~ 5
This is processing to be provided to the service request source in 3).

The process of providing pre-silicon device parameters for circuit design SV4 is performed by the line data servers 40 to 42.
Of the fabless 13 to 16 (design data servers 50 to 53) by generating pre-silicon device parameters for circuit simulation relating to next-generation devices and the like necessary for the fabless 13 to 16 to design circuits from the data of the fabless 13 to 16 (design data servers 50 to 53). This is the process provided to the original.

The process for providing line yield improvement measures SV5 is a process for generating and providing device improvement measures for increasing the yield of products required by the fabless devices 13 to 16.

The line recruitment process SV6 is executed by the fabless 13
Fab 10-12 or fab 10-1 that satisfies the required delivery conditions for the required processes and products
This is a process of retrieving the second line and providing it to the service request source in the design data servers 50 to 53.

Providing lot input timing data SV7
Are the line data servers 40 to 42 of the fabs 10 to 12
And fabless 13 to 16 with time series device variation data, wiring variation data, foreign matter data, etc.
From the required number of products and the delivery date, the data on the lot delivery time for satisfying the delivery date and the number of the products with a small number of wafers is generated, and the services in the fabs 10 to 12 (line data servers 40 to 43) are generated. This is the process provided to the request source.

In the recent semiconductor industry, the service provider 17 is divided into fabless companies 13-16 which design LSIs and fabs 10-16 which manufacture LSIs.
As the situation in which 12 is managed as a separate company is becoming apparent, information on fabs 10 to 12 and fabless 13 to 16 are integrated as described above to generate or process information that is effective for both parties. Service that does When fabs 10-12 and fabless 13-16 become available to such a service provider 17, fabless 13-16 decides on which fab 10-12 to order products costly and timely. QTAT (Qu
ick Turn Around Time). Fab 10
12 can obtain the information for increasing the yield, and the fabless 13 to 16 can be used to order products.
Since it is possible to receive information on which production line of which fab 10 to 12 is good as an SI production line, an effect of improving sales can be expected.

FIG. 4 illustrates the relationship between the service providing processes by the knowledge management server 60. That is, an example shows when or at what timing the knowledge management server 60 is used to provide a service.

Fabless 13 to 16
12 when weighing whether to request LSI manufacturing,
As one guideline, the service request source among the fabless 13 to 16 requests product yield information for each of the fabs 10 to 12 (S6). In response, the knowledge management server 60 executes a process of providing product yield data (SV
1). The service request source among the fabless 13 to 16 determines which fab 10 to 12 based on the obtained product yield data.
Is determined to be equal to or less than the target value (S
7), the service request source among the fabless 13 to 16 can request the knowledge management server 60 to provide the yield improvement measure of the line (SV5) and take measures. In this way, the yield improvement measures given to the fabless devices 13 to 16 are matters relating to device design process conditions, layouts, and the like that contribute to the yield improvement.

Fabs 10 to 12 are fabless 13 to 16
There is a case where it is desired to determine whether or not the wafer unit price is appropriate for the desired chip unit price. At this time, the service request source among the fabs 10 to 12 (line data servers 40 to 43) is the knowledge management server 6
0, request the wafer unit price data (S1). The knowledge management server 60 responds to the request (S1) from the service request source among the fabs 10 to 12,
A process is performed to determine an appropriate wafer unit price (unit price per wafer) from the product yield and the chip unit price (unit price desired by the fab) (SV2). The service requesting fabs 10 to 12 judge whether the wafer production cost is too high (the wafer unit price is higher than the budget) for the appropriate wafer unit price (S).
2) If it is too high, the Knowledge Management Server 6
A request can be made for the process of providing a line yield improvement measure (SV5) for 0 to take measures. The yield improvement measures given at this time are related to device manufacturing, such as device structure and process conditions. The process of providing the line yield improvement measure (SV5) is performed when the service request source among the fabs 10 to 12 independently requests the yield improvement measure (SV5).
3), may be performed in response thereto.

The fabless units 13 to 16 correspond to the fab units 10 to 12
There is a case where it is desired to determine whether or not the chip unit price matches the balance of the desired wafer unit price. At this time, the service request source in the fabless 13 to 16 (design data server 50 to 53) is the knowledge management server 6
Request the chip unit price data to 0 (S4). The knowledge management server 60 includes fabless 13 to 16
In response to the request (S4) from the service request source, a process for obtaining an appropriate chip unit price from the product yield and the wafer unit price is performed (SV2). If the chip unit price exceeds the budget (S5), the service request source fabless 13 to 16
Can request the knowledge management server 60 to provide processing (SV5) for a line yield improvement measure and take measures. The yield improvement measures given at this time are related to device design layout or the like that contributes to the yield improvement.

The circuit design device parameter providing process (SV3), the circuit design pre-silicon device parameter providing process (SV4), the line mediation process (SV6), and the lot input timing data providing process (SV7) ) Are fabless 13-
16 or the corresponding request from the fabs 10 to 12 (S10 to S13).

FIG. 5 exemplifies a billing method between a fab and a fabless and a service provider. The service provider 17 pays for the service by using only a method such as a subscription fee and an annual fee (or monthly fee), or in combination with another method, or by another method.
Any charging method may be adopted. As the other methods described above, a fixed amount of data provision amount specified for each service is paid, or a data provision amount specified for each service is paid on a pay-per-use basis of the provided data. Pay a commission according to the order quantity at the time of contract for manufacturing order,
Alternatively, there is a method of paying as a success reward, such as a rate at the time of improving the yield.

FIG. 6 shows an example of security measures between a fab and a fabless and a service provider. A service provision contract is individually signed between the fabs 10 to 12 and the fabless 13 to 16 and the service provider 17, and the fabs 10 to 12 and the fabless 13
16 pays a predetermined price, and the service provider 1
7 to provide services. At this time, as described above,
The service provider 17 accesses the line data servers 40 to 42 to obtain device information or device manufacturing information of the fabs 10 to 12, and accesses the design data servers 50 to 53 to access the fabless 13 to 16 It is permissible to obtain design information for At this time, in order to prevent unauthorized access, the fabless devices 13 to 16 issue a password required for access to the design data servers 50 to 53 to the service provider 17, and perform authentication for accessing the design data servers 50 to 53. , The user is required to input the issued password or the like. Similarly, the fabs 10 to 12 issue passwords required for accessing the line data servers 40 to 42 to the service provider 17 and input the issued passwords and the like for authentication for accessing the line data servers 40 to 43. Is required. In addition, information exchanged on the Internet is encrypted.

<< Service Contents and Information Input / Output >> FIG. 7 shows an example of information input / output relating to processing for providing product yield data, wafer unit price, and chip unit price.

The knowledge management server 60 has the line data servers 40 to 4 of the target fabs 10 to 12.
2 to access typical device characteristics, device variation data, wiring variation data, and foreign matter data. Typical device characteristics are characteristic measurement data of various average devices such as Vds-Ids characteristics and Vgs-Ids characteristics of MOS transistors. The device variation data includes various L
The variation may be variation due to test result data of a wafer probe test related to SI, and is variation data such as a threshold voltage and a saturation current of a MOS transistor obtained from such past results. The wiring variation data is the variation data of the wiring capacitance and the wiring resistance of various wiring layers of various materials such as tungsten and aluminum similarly obtained from past results. The foreign substance data is, for example, information on the defect density for each wiring layer. Device variation data and wiring variation data are information that affects device performance, and foreign matter data is information that affects the LSI failure rate.

Also, the knowledge management server 60
Accesses the target design data servers 50 to 53 of the fabless 13 to 16 and sets the target LSI
Information such as benchmark circuits, layout data, product specifications (product specifications), chip unit cost budget, wafer unit cost budget, and the number of chips per wafer. The benchmark circuit is a target LSI
3 is a circuit simulation netlist for a circuit portion that represents the performance of the present invention.

The knowledge management server 60 performs the following information generation processing using the accessed information.
[1] From the device and wiring variation data provided by the fabs 10 to 12, the performance variation (circuit characteristic variation) related to the benchmark circuits provided by the fabless 13 to 16 is obtained. In short, by the simulation using the benchmark circuit, it is possible to obtain variations in circuit characteristics (variations in circuit performance) according to variations in devices and wiring. [2] A yield (characteristic yield) in terms of performance is obtained from the circuit characteristic variation and product specifications.
[3] The yield (foreign matter yield) caused by the foreign matter is obtained from the foreign matter data provided by the fabs 10 to 12 and the layout data provided by the fabless 13 to 16. [4] A product yield of the target LSI is obtained from the characteristic yield and the foreign matter yield (for example, as a product of both). The product yield obtained in this way is a fabless 13
The service request source of the design data servers 50 to 53 is acquired. [5] Further, the knowledge management server 60 obtains a wafer unit price suitable for the balance from the product yield and the chip unit price desired by the fabless 13 to 16. This wafer unit price is obtained by the fabs 10 to 12 as a result of the request. [6] Further, the knowledge management server 60 obtains a chip unit price commensurate with the balance from the product yield and the wafer unit price desired by the fabs 10 to 12. The chip unit price is obtained by the service request source among the fabless 13 to 16 as a result of the request.

FIG. 8 shows an example of information input / output relating to the process of providing device parameters for circuit design.

The knowledge management server 60 is provided with the line data servers 40-4 of the target fabs 10-12.
2 is accessed to fetch typical device characteristics, device variation data, and wiring variation data in the same manner as described above, and further accesses benchmark circuits relating to those devices. The benchmark circuit is a netlist for circuit simulation relating to a circuit portion that represents the performance of a target device.

The knowledge management server 60 uses the accessed information to generate [7] device parameters and [8] wiring parameters. The device parameter is a parameter used when performing a circuit simulation at the time of circuit design, and is, for example, a set of coefficients for representing characteristics of a MOS transistor. Regarding the generation of the parameters, the worst, best, and typical (Worst, Best, Typical)
Acquisition in a mode. The parameters obtained in this way are obtained by the service request source among the fabless 13 to 16 (design data servers 50 to 53) as a result of the request.

FIG. 9 shows a first information input / output example relating to the process of providing a line yield improvement measure. This information input / output is positioned as corresponding to the flow of steps S1, S2, and S3 in FIG.

The knowledge management server 60 is provided with the line data servers 40-4 of the target fabs 10-12.
2 to access the typical device characteristics and the device variation data, as well as the process conditions and benchmark circuits for those devices.

The knowledge management server 60 uses the information accessed in response to the request from the fabs 10 to 12,

[9] When it is assumed that the benchmark circuit is manufactured based on the performance and process conditions of the accessed device, a process for obtaining process conditions and a device structure for improving the device performance or reducing variations in device characteristics is performed. Do. In short, this process seeks to optimize the device structure and process conditions for a plurality of process conditions while considering circuit characteristics such as whether to operate at high speed based on the benchmark circuit. Fab 10-12 line data servers 40-4
The optimum process conditions as a yield improvement measure given to the service requester among the three are, for example, the amount of implanted impurities, ion implantation energy, implantation angle, and the like. The device condition as a yield improvement measure is, for example, a condition such as a channel length of a MOS transistor and an oxide film thickness. That is, the line yield improvement measures given in this process are related to device manufacturing.

FIG. 10 shows a second example of information input / output relating to the process of providing a line yield improvement measure. This information input / output is positioned as corresponding to the flow of steps S4, S5, S6, and S7 in FIG.

The knowledge management server 60 is provided with the line data servers 40-4 of the target fabs 10-12.
2 to access the typical device characteristics and the device variation data, as well as the process conditions and the line data relating to the defect density (data on a line data server). This access information is the same as the access information described in FIG.

The knowledge management server 60
Accesses the target design data servers 50 to 53 of the fabless 13 to 16 and sets the target LSI
Information such as benchmark circuits, layout data, and circuit performance specifications (circuit performance specifications). The benchmark circuit is a netlist for circuit simulation relating to a circuit portion that represents the performance of a target LSI.

The knowledge management server 60 responds to the request from the fabs 10 to 12 and, based on the accessed information, [10] when it is assumed that the benchmark circuit is manufactured based on the performance and process conditions of the accessed device. In order to improve the device performance or reduce the variation in device characteristics, a process for obtaining a device structure and process conditions is performed. In short, this process
The present invention proposes a layout structure that can optimize circuit characteristics while considering circuit characteristics such as whether to operate at high speed based on the benchmark circuit.

FIG. 11 shows an example of information input / output relating to the pre-silicon parameter providing process. The pre-silicon parameter (pre-silicon device parameter) means a device parameter generated by predicting a device under other conditions and a device of a next-generation process from a device parameter extracted from an existing device.

The knowledge management server 60 is provided with the line data servers 40-4 of the target fabs 10-12.
2 to access information on typical device characteristics, process variations, and wiring variations (wiring capacitance, wiring resistance) relating to existing devices, as described above. Further, information on a device having another target condition or a condition (target device condition) relating to a device of a next-generation process is accessed. The target device conditions include, for example, in the case of a MOS transistor, a gate length (Lg), a gate oxide film thickness (Tox), a relationship between a gate length and a threshold voltage (Lg-Vth), and the like. Furthermore,
Knowledge Management Server 60 is the target fab 1
The information of the benchmark circuit is acquired by accessing the line data servers 40 to 42 of 0 to 12. The benchmark circuit may be a netlist of circuits that can be evaluated by performing a simulation assuming that a circuit designed with an existing device is configured with a target device.

The knowledge management server 60 generates [11] pre-silicon device parameters and [12] pre-silicon wiring parameters using the accessed information. With respect to the generation of the pre-silicon parameter, the worst, best, and typical (Worst, Best, Typical) modes are obtained using the benchmark circuit. The parameters obtained in this way are obtained by the service request source among the fabless 13 to 16 (design data servers 50 to 53) as a result of the request. The service requester of the fabless 13 to 16 can use the obtained pre-silicon device parameters related to the target device, and can proceed with the circuit design while performing simulation before the fab 10 to 12 develop the device. Become. This makes it possible for the fabless units 13 to 16 to have an earlier order for an LSI design.

FIG. 12 shows an example of information input / output relating to the process of providing line mediation. This process is fabless 13 ~
16 is a process for obtaining information on which fabs 10 to 12 should be ordered, and naturally relates to the yield of the fabs. Therefore, similarly to the case of FIG. Design data server 5
The line data servers 40 to 4 of the target fabs 10 to 12 are used as information necessary for obtaining the product yield of the target LSI required by the service request source among the service request sources 0 to 53
2 to access typical device characteristics, device variation data, and foreign matter data, and access and acquire information on benchmark circuits, layout data, and product specifications from the requesting fabless 13 to 16. Further, the knowledge management server 60 accesses the line data servers 40 to 42 of the target fabs 10 to 12 as information necessary for performing the line mediation based on the product yield of the target LSI, and relates to the line throughput. The information and the like are acquired, and the request source fabless 13-16 receives the wafer unit cost budget, the request process,
Information such as the required number of chips and the required number of chips obtained from one wafer is acquired.

The knowledge management server 60 uses the accessed information to perform [13] target LS
The product yield of I is obtained, and [14] The unit price per chip is obtained from the product yield and the wafer unit cost budget. Also, the knowledge management server 60 [15]
For each production line, the completion time of the product requested by the service requester among the fabless units 13 to 16 is estimated based on the throughput of the production line and the congestion state of the production line. The service request source of the fabless 13 to 16 is
12 based on the product completion time and chip unit price,
The fabs 10 to 12 to be requested are selected. In this way, the optimal fab mediation for producing the product is performed.

FIG. 13 shows an example of information input / output relating to the process of providing lot input timing data. This process provides information to a fab when a fabless receives an order for a product and a delivery date from the fabless, taking into account periodic changes in the status of the fab production line. That is, the knowledge management server 60 accesses the line data servers 40 to 42 of the target fabs 10 to 12 to obtain time-series data on the device variation and the wiring variation of the fab described in FIG. Besides that,
The knowledge management server 60 acquires the manufacturing period and foreign matter data of one lot from the target fab. The knowledge management server 60 also sets up the fabless 13-1.
The information of the benchmark circuit, the layout data, the design specifications, and the chip unit cost budget are obtained from the design data server 6 as in FIG. Further, the knowledge management server 60 sends the fabless 13
The information on the requested delivery date and the required number of chips of the target LSI is acquired from the order request source in the design data servers 50 to 53 (design data servers 50 to 53).

The knowledge management server 60 performs the following processing using the accessed information. [16] From the time-series device variation data and the wiring variation data provided by the fabs 10 to 12, the characteristic variation of the circuit provided by the order request source among the fabless 13 to 16 is obtained. In short, a simulation by the benchmark circuit obtains a variation in circuit characteristics (variation in circuit performance) according to a variation in device and wiring. [17] A yield (characteristic yield) relating to performance is obtained for each period and period from the product specifications. [18] Foreign matter data provided by the service request source among the fabs 10 to 12 and the fabless 13 to 16
The yield (foreign matter yield) due to the foreign matter is obtained from the layout data provided by the order request source. [19] From the characteristic yield and the foreign matter yield, obtain a product yield for each time and period for the target product. [20] Fabless 13
In order to manufacture the number requested by the order requester out of ~ 16 by the required delivery date, it is required to determine from which time and for how long the lot of the product is to be flown. The service request source of the fabs 10 to 12 acquires the data of the lot input timing and the lot input period obtained as a result of the request.

<< Information Processing Method >> FIG. 14 illustrates a data flow of the product yield calculation by [1] to [4] described with reference to FIG. In the figure,> Fb means information given to the fab, Fb> means information given from the fab,> Fl means information given to the fabless, and Fl> Means that the information is provided by fabless.

First, device parameters (also referred to as model parameters) are extracted from typical device characteristics obtained from the fabs 10 to 12 (line data servers 40 to 42) (T1), and typical for circuit simulation. Generate device parameters. Generated device parameters and fabs 10-12
Statistical device parameter extraction is executed using the device variation data obtained from the (line data servers 40 to 42) (T2) to generate process variation data. FIG. 37 shows statistical device parameter extraction (T
2) An outline of the process is illustrated, and based on typical device parameters and device variation data,
For example, process variations such as an oxide film thickness (Tox), a gate length (Lg), a channel dose (Nch), and a short channel effect suppression implant dose (Nlx) of a MOS transistor are generated.

The generated process variation data, wiring resistance and capacitance variation data obtained from fabs 10 to 12 (line data servers 40 to 42), and fabless 13 to 16 (design data servers 50 to 53) The circuit characteristic variation analysis is performed using the netlist of the benchmark circuit, the specification of the power supply voltage, and the specification of the temperature obtained from the service request source (T3), and characteristic variation data is generated. FIG. 39 illustrates a state of the circuit characteristic variation analysis. Using the model parameters, the netlist, and the process variations, variations in circuit characteristics such as variations in the threshold Vth and the drain / source current Ids and variations in the delay time can be obtained.

Using the obtained characteristic variation data and the circuit performance specification obtained from the service request source in the fabless 13 to 16 (design data servers 50 to 53), a characteristic yield calculation process is executed (T4). And characteristic yield.
FIG. 40 illustrates the characteristic yield calculation. According to this, the characteristic yield is obtained by multiplying the yield for each characteristic obtained from the circuit specifications.

A critical area analysis is performed using the defect density for each wiring layer obtained from the fabs 10 to 12 (line data servers 40 to 42) and the layout data obtained from the service request source in the fabless 13 to 16 (T5) to obtain the foreign matter yield. The product yield is calculated from the characteristic yield and the foreign matter yield (T6), and the yield of the product is obtained.

Thus, the service request source of the fabless units 13 to 16 can know in advance the product yield when the product is ordered to each of the fabs 10 to 12, and appropriately select the fabs 10 to 12. Will be able to do it.

FIG. 15 exemplifies a data flow for obtaining an appropriate unit price of a wafer described with reference to FIG. The wafer price is calculated from the product yield obtained as described above, the budget of the chip unit price obtained from the fabless 13 to 16 (design data server 50 to 53), and the number of chips obtained from one wafer, and the appropriate unit price of the wafer. (T7).

As a result, the fab that is the service requester among the fabs 10 to 12 can know the wafer unit price that matches the balance with respect to the chip unit price desired by the fabless units 13 to 16.

FIG. 16 shows an example of a data flow for obtaining the appropriate unit price of the chip described with reference to FIG. Product yields and fabs 10 to 12 (line data server 4
The chip unit price is calculated from the wafer unit price obtained from 0 to 42) and the number of chips obtained from one wafer, and an appropriate unit price of the chip is obtained (T8).

Thus, the fabless units 13 to 16 can know in advance the cost of ordering the product to each of the fabs 10 to 12 from the chip unit price.
Choosing the right fab can help you lower costs and increase profits.

FIG. 17 shows a data flow for generating the device parameters for design described in FIG. Device parameters are extracted from the typical device characteristics obtained from the fabs 10 to 12 (line data servers 40 to 42) (T1), and typical device parameters for circuit simulation are generated. Statistical device parameter extraction is executed using the generated device parameters and the device variation data obtained from the fabs 10 to 12 (T2) to generate process variation data. Generated process variation data, fabs 10-12 (line data servers 40-4
The variation data of the resistance and capacitance of the wiring obtained from 2),
Fabless 13-16 (design data server 50-53)
The circuit characteristic variation analysis is performed using the benchmark circuit netlist obtained from the service request source in (T3) to generate characteristic variation data. A process for generating worst and best parameters for circuit design from the obtained characteristic variation data is executed (T9), and the obtained device and wiring worst and best parameters are converted into fabless 13 to 16 ( The service is provided to the service request source in the design data servers 50 to 53). FIG. 41 shows an example of worst and best parameter generation processing. A characteristic with a small delay and a large cutoff current is adopted as a best parameter, and a characteristic with a large delay and a small drain-source current is used as the worst. It is adopted as a parameter.

According to the processing in FIG.
6 simulates the circuit using the device parameters, so that each fab 1
It is possible to confirm the characteristics or performance when the manufacture of the product is requested from 0 to 12, and it is possible to select an appropriate fab that can manufacture a product satisfying the performance specifications.

FIG. 18 is a data flow for seeking a yield improvement measure described with reference to FIG. Device parameters are extracted from typical device characteristics obtained from the fabs 10 to 12 (line data servers 40 to 42) (T
1) Generate typical device parameters for circuit simulation. Generated device parameters and fabs 10 to 12 (line data server 40 to
Using the device variation data obtained in step 42), statistical device parameter extraction is executed (T2) to generate process variation data. In addition, device robust processing is executed based on typical device characteristics and device process conditions (T10), and optimum process conditions in the sense of small variations are obtained and provided to the fab. The provided process condition expression has contents as shown in FIG. Further, the device characteristics and process variation obtained here, and fab 10 to 12
A circuit characteristic variation analysis is performed using the netlist of the benchmark circuit provided by the service requester among the (line data servers 40 to 42) (T11), and an optimum device structure is obtained and provided to the fab.

As a result, the service request source among the fabs 10 to 12 can increase the yield and reduce defective products, which leads to an increase in sales.

FIG. 19 exemplifies a data flow for seeking a yield improvement measure exclusively for a fabless product described with reference to FIG. Device parameters are extracted from the typical device characteristics obtained from the fabs 10 to 12 (line data servers 40 to 42) (T1), and typical device parameters for circuit simulation are generated. Statistical device parameter extraction is executed using the generated device parameters and device variation data obtained from the fabs 10 to 12 (line data servers 40 to 42) (T
2) Generate process variation data. In addition, device robust processing is executed based on typical device characteristics and device process conditions (T10), and optimum process conditions are determined to provide service request sources to the fabs 10 to 12 (line data servers 40 to 42). provide. Further, a circuit characteristic variation analysis is performed using the device characteristics and process variation obtained here and the netlist of the benchmark circuits provided by the fabless 13 to 16 (design data servers 50 to 53) (T1).
1) The variation in characteristics and the optimum device structure are obtained and provided to the service request source among the fabs 10 to 12 (line data servers 40 to 42). In addition, fabless 13
特性 16 (design data servers 50５３53), the characteristic yield of the product is calculated using the specification of the circuit performance, the characteristic variation obtained above, and the improved device structure (T
4). On the other hand, the defect density for each wiring layer obtained from the fabless 13 to 16 (design data server 50 to 53) is subjected to a critical area analysis using the layout data obtained from the fabless 13 to 16 (design data server 50 to 53). Then, the foreign material yield is obtained (T5). The product yield is calculated from the characteristic yield and the foreign matter yield (T6), and the yield of the product is obtained.

The product yield obtained by the product yield calculation (T6) is improved for the fabs 10 to 12 in the process and the device structure (improved process conditions, improved device structure).
As a result, the expected yield improvement can be expected. In short, the service requesting source among the fabs 10 to 12 can increase the yield of the ordered products of the fabless 13 to 16 and reduce the defective products. Therefore, when the sales price of one chip is fixed, the service request source among the fabs 10 to 12 can sell one wafer at a higher price, and when the sales price of one wafer is fixed, one service is required. Because the cost per chip can be reduced,
Leads to increased profits.

The critical area analysis processing (T
The improved layout obtained in 5) is fabless 13-16
(Design data servers 50 to 53). As a result, the service request source among the fabless units 13 to 16 can review the layout design so as to improve the yield.

FIG. 20 illustrates a data flow for generating the pre-silicon device parameters for circuit design described with reference to FIG. Device parameters are extracted from the typical device characteristics obtained from the fabs 10 to 12 (line data servers 40 to 42) (T1), and typical device parameters for circuit simulation are generated. Pre-silicon device parameter generation processing is executed using the generated device parameters and the channel length dependence of the target device channel length, oxide film thickness, and threshold value (T12) to generate typical pre-silicon device parameters. Fab 10
12 (line data servers 40 to 42), process variation and wiring resistance and capacitance variation data,
A circuit characteristic variation analysis is performed using the benchmark circuit netlist obtained from the foundry (T3),
Generate characteristic variation data. A process for generating the worst and best parameters for circuit design from the obtained characteristic variation data is executed (T9), and the obtained device and wiring worst and best pre-silicon parameters are converted to fabless 13 to 16 (design data server 50). ~ 5
It is provided to the service request source in 3).

Thus, the service request source among the fabless units 13 to 16 can perform a circuit simulation using the device parameters before the fab units 10 to 12 develop the device. It is possible to confirm the performance of the characteristics at the time of receiving the order at an early stage, and it is possible to appropriately select a fab that can manufacture a product satisfying the performance specifications.

FIG. 21 shows an example of a data flow when mediating a production line to a service request source among the fabless units 13 to 16 described in FIG. Fabless 13-1
6, the delivery date of the product is calculated from the request process of the product obtained from the service request source, the required number, the throughput of the line obtained from the fabless 13 to 16 (design data server 50 to 53) and the order receiving status (T13). ), Providing information to service request sources in the fabless 13 to 16 (design data servers 50 to 53), and responding to a request for delivery date from the service request source in the fabless 13 to 16 (design data servers 50 to 53). Find matching fabs 10-12.
The order receiving situation is given as information as exemplified in FIG. At the same time, product yield and fab 10-12
The wafer unit price obtained from the (line data servers 40 to 42) and the chip size obtained from the fabless 13 to 16 (design data server 50 to 53) are calculated (T8), and the fabless 13 to 16 (design Data servers 50 to 53) are provided to the service requester, and fabless 13 to 16 are determined based on the balance between product delivery and chip unit price.
The fabs 10 to 12 that meet the request from the service request source in the (design data servers 50 to 53) are mediated.

Thus, the fabless units 13 to 16 can select a fab that can manufacture a product at an appropriate price and at a desired delivery date. Also, for the fabs 10 to 12, the operating rate of the line can be increased, which leads to an increase in sales.

FIG. 22 exemplifies a data flow for obtaining the lot input timing of the product described in FIG. Device parameters are extracted from characteristics of typical devices obtained from service request sources in the fabs 10 to 12 (line data servers 40 to 42) (T1),
Typical device parameters for circuit simulation are generated. Generated device parameters and fabs 10-12 (line data servers 40-4
Statistical device parameter extraction is executed using the time-series variation data of the device obtained in 2) (T
2), process variation data is generated. Generated process variation data, time-series wiring resistance and capacitance variation data obtained from service request sources among fabs 10 to 12 (line data servers 40 to 42), and fabless 13 to 16 (design data server 50-5
The circuit characteristic variation analysis is performed using the benchmark circuit netlist, power supply voltage specification, and temperature specification obtained from the order request source in (3) (T3), and time-series characteristic variation data is generated. You. The characteristic yield calculation process is executed using the obtained characteristic variation data and the circuit performance specifications obtained from the order request source in the fabless 13 to 16 (design data servers 50 to 53) (T
4) A time-series characteristic yield is required. Fab 1
Defect densities for each wiring layer obtained from service request sources among 0-12 (line data servers 40-42) and obtained from order request sources among fabless 13-16 (design data servers 50-53) A critical area analysis is performed using the layout data (T5), and a foreign matter yield is obtained. A product yield is calculated from the characteristic yield and the foreign matter yield (T6), and a time-series yield of the product is obtained. From the chronological yield, the number of good products obtained from one lot is calculated, and from what time and for how long it is necessary to put the product into the line to produce the required quantity by the required delivery date, That is, the lot input timing is obtained (T14).

The characteristics of the devices manufactured in the line are shown in FIG.
As shown in FIG. 2, the frequency fluctuates periodically at the timing of cleaning the production line. By determining the lot input timing using this information, the service request source among the fabs 10 to 12 (the line data servers 40 to 42) depends on the product specifications. It is possible to allocate the manufacturing time according to the product performance, such as introducing the product at a time when the product is high, and supplying a medium speed product or a low speed product at another time. Also,
As illustrated in FIG. 43, when the yield of the high-speed product A fluctuates in synchronization with the cleaning cycle of the manufacturing line, if the required delivery date of the high-speed product A is early, it is necessary to input a lot even when the yield is low. Become. On the other hand, if the required delivery date is late, a production lot of the product A is put in only at a high yield period, and another product (a low-speed product, a medium-speed product) with a higher yield than the product A during other periods. May be allocated to the production lot. Therefore, the required number can be manufactured with a small number of wafers, and the fabs 10 to 12 (the line data servers 40 to 4) can be manufactured.
For the service requester of 2), the cost is reduced.

FIG. 23 shows a device parameter extraction (T
The processing method 1) is exemplified from the viewpoint of data flow.
This method is a method of extracting a device parameter expression used for device parameters (model parameters) of static characteristics of the BSIM3 model developed by UCB, that is, a device parameter set 106.

First, the storage device 10 such as a hard disk
From the device characteristics measurement data 101 of the Vds-Ids characteristics and Vgs-Ids characteristics stored in 1, device characteristics such as a short channel effect, a narrow channel effect, a substrate effect, a sub-threshold swing characteristic, and a surface punch-through characteristic of the device are obtained. The intermediate data 103 is generated and stored in a storage device such as a hard disk as an intermediate file. In the intermediate data generation processing 102, the model parameters are hierarchically grouped from the viewpoint of the threshold value, the current, and the like, and the intermediate data 103 of the device characteristics such as the short channel effect and the narrow channel effect are generated.

Next, the intermediate data 103 of the device characteristics stored in the intermediate file and the separately measured MOS data such as the channel length, the oxide film thickness, and the profile stored in the storage device in the hard disk or the like. In the parameter extraction process 105, each parameter of the BSIM3 model is extracted from the device structure data 104 related to the device structure, and the device parameter set 1
06 is obtained. The device characteristic data and the device structure data are separately measured in advance by a known device characteristic measuring device such as a curve tracer or a tester, or a known analyzing device such as a scanning electron microscope (SEM).

FIG. 24 exemplifies the device parameter extraction processing T1 from the viewpoint of the processing procedure. Step S2
In step S22, the device parameters relating to the actual channel length, oxide film thickness, mobility, and saturation speed are determined.
Then, device parameters relating to the execution channel length are extracted. The values of the device parameters for determining the threshold value are set in the order of steps S23 to S27, that is, the substrate effect, the sub-threshold swing characteristic, the surface punch-through characteristic,
The device parameters are extracted in the order of the short-channel effect and the narrow-channel effect. Further, the values of the device parameters relating to the current are set in the order of steps S28 to S30, that is,
The device parameters are extracted in the order of bulk charge effect, parasitic resistance, and effective channel width. In short, device parameters are extracted for each physical phenomenon.

The method for extracting the device parameters described with reference to FIG. 23 is described in detail in, for example, Japanese Patent Application Laid-Open No. 2000-322456.

FIG. 25 illustrates the method of the statistical device parameter extraction processing T2 from the viewpoint of data flow. This method uses the UCB from a large number of MOS characteristic measurement data.
This is a method of extracting a part of the device parameters (model parameters) of the static characteristics of the BSIM3 model, that is, a statistical device parameter set.

First, device information data 111 stored in a storage device such as a hard disk is input, and M
The processing of the netlist generation function unit 112 for performing the circuit simulation of the OS alone is executed, and the obtained netlist 113 is stored as an intermediate file in a storage device such as a hard disk.

A circuit simulation function unit 115 receives the generated netlist 113 and a set of device parameter sets 114 extracted from a specific MOS as inputs.
Is executed, and the output results of the saturation current and the threshold value obtained by the simulation are stored as a circuit simulation output result 116 in a storage device such as a hard disk. The circuit simulator used here is a commonly used SPIC
E-compliant simulator (The Design's
Guide to SPICE &# 38 SPECTRE, Kenneth S. Kundert
Author, Academic Publishers).

Output result 116 of the simulation
And the measurement data 11 of the saturation current and the threshold obtained from the measurement
7 and the convergence determination condition data 118 are input, and the convergence determination function unit 119 compares the two data to determine whether the difference between the saturation current and the threshold obtained by the simulation satisfies the convergence determination condition. .

If the convergence condition is not satisfied, partial device parameters related to the process at this time (device parameters representing oxide film thickness, channel dose, short channel effect suppression implant dose, channel length, channel width) 120 And search range data 1 for each parameter
With 21 as an input, the parameter search function unit 122 changes a parameter value within the search range to determine a new parameter value, and changes a device parameter set and a netlist value. When the convergence condition is satisfied, the device parameter value at that time is stored as a statistical device parameter set 123 in a storage device such as a hard disk.

FIG. 26 illustrates the method of the statistical device parameter extraction processing T2 from the viewpoint of the processing procedure. As shown in the figure, first, the parameters of the oxide film thickness and the channel dose are extracted from the long channel MOS saturation current and the threshold (S41), and then the channel length and the short channel are extracted from the short channel MOS saturation current and the threshold. A parameter representing the effect suppression implant dose is extracted (S42). Finally, a parameter representing the channel width is extracted from the saturation current of the short channel MOS and the threshold (S43). In short, device parameters are extracted for devices having different device sizes and the like. In step S41, parameters are extracted for a saturation current in a long-channel MOS, an oxide film thickness, and a channel dose, which are factors that cause variations in threshold, and in step S42, A parameter representing a channel length and a short channel effect suppression implant dose, which are the causes of the variation in the saturation current and the threshold in the short channel MOS, is extracted. Extract parameters. FIG. 38 shows the difference in parameters extracted between the short channel MOS transistor and the long channel MOS transistor. Represents the typical device characteristics actually obtained by the wafer probe test, and ○ represents the characteristics obtained by the circuit simulation, and illustrates the latter being fitted to the former. The processing in steps S41 to S43 is described in detail in the specification of Japanese Patent Application No. 2000-322456.

FIG. 27 shows the circuit characteristic variation analysis T3.
Is exemplified. According to this, process variations, device parameters, and a net list are read (S45 to S47). Then, a random number is generated from the central value of the process variation, the type of distribution, and the standard deviation (S48), and the device parameters and the netlist value are rewritten accordingly (S49), thereby executing a circuit simulation (S50). Then, the circuit characteristics are executed (S51). The processes in steps S48 to S51 are repeatedly performed for the specified number of times or more, and the process ends.

FIG. 28 illustrates a processing flow of the characteristic yield calculation T4. First, the characteristic variation and the circuit performance specification are read (S55, S56), and the central value and the standard deviation of the characteristic variation are obtained (S57). Then, by calculating a normal cumulative distribution in a range satisfying the specifications from the distribution of the circuit performance specifications and the characteristic variations, a characteristic yield is obtained (S58), and this is output (S59).

FIG. 29 illustrates a processing flow of the product yield calculation T6. First, the characteristic yield and the foreign matter yield are read (S60, S61), and the product yield is calculated (S6).
2) The calculated product yield is output (S63).

FIG. 30 illustrates a processing flow of the calculation T7 of the wafer price. The product yield, the cost per chip, and the number of chips per wafer are read (S64 to S6).
6) The wafer price is calculated (S67), and the calculated wafer price is output (S68).

FIG. 31 illustrates a processing flow of the chip unit price calculation T8. Product yield, wafer unit price, wafer 1
The number of chips per chip is read (S70 to S72),
The chip unit price is calculated (S73), and the calculated chip unit price is output (S74).

FIG. 32 exemplifies a processing flow of the worst and best parameter generation T9. The characteristic variation is read (S76), the central value of the characteristic variation and the standard deviation are calculated (S77), a condition where the characteristic variation is three times the standard deviation is detected (S78), and the condition is written in the parameter. (S79), and the process ends.

FIG. 33 shows the device robust design T1.
0 is exemplified. This process flow uses a linear programming method. First, parameters and levels are determined (S80), and the parameters and levels are assigned to an orthogonal table (S81).
In response, a process and device simulation are executed (S82). Based on the simulation result, SN regarding the threshold value (Vth) of the MOS transistor
The ratio and the sensitivity are calculated (S83), and the S / N ratio and the degree of duty with respect to Vth and Ids (drain-source current) of the MOS transistor are calculated (S84). It is created (S85), and the optimum condition is determined using it (S86). And SN
The ratio, the sensitivity, and the effect are estimated (S87), and a confirmation simulation is performed on the estimation result (S8).
8) After confirming the reproducibility (S89), the process ends.

FIG. 34 illustrates a processing flow of the pre-silicon device parameter generation T12. The device parameters and information on the target channel length and the oxide film thickness are read (S90, S91), whereby the conditions of the channel length and the oxide film thickness are rewritten (S92).
This time, the Lg-Vth dependency is read (S93),
Lg-Vth dependency matching is performed (S94),
Thereby, the device parameters are rewritten (S95).

FIG. 35 exemplifies a processing flow of the product delivery date calculation T3. First, data of the requested number of requested processes, the throughput, and the order status are read (S96).
~ 98). The line introduction timing of the required product is calculated from the read order status and the line throughput (S9).
9). Further, the throughput of the line is read from the requested process (S100), and the delivery date of the requested product is calculated from the line input timing of the requested product and the throughput of the requested process (S101).

FIG. 36 exemplifies a processing flow of calculation T14 of the lot input timing and period of the product. First, the number of chips per chip, the required number, and the required delivery date are read (S102), and the product yield in time series is read (S103). The lot input timing for performing the lot out before the delivery date from the period is calculated (S104). Then, prior to the lot input timing, the products are selected in descending order of yield (S105), and the number of non-defective products is calculated from the product yield and the number of chips per wafer (S106). Is determined to be greater than or equal to the required number (S107). If the number of non-defective products is small, the process returns to step S105 and the process is repeated. Is output (S108),
The process ends.

FIG. 46 shows the knowledge management server 6.
0, the data providing sources and providing timings (or access timings) for various data such as the typical device data used are shown in an organized manner.

<< Second System Configuration >> FIG. 2 shows a second embodiment of the information processing system according to the present invention connected to a network.
Is exemplified. In this example, the fab 10A representatively shown is a knowledge management server (KMS (1s
t): first computer device) 61. That is, the fab 10A has a plurality of manufacturing lines 23 to 25, measuring instruments 33 to 35, and a line data server (Ln (2nd):
A second computer 43) and a knowledge management server 61. The line data server 43 holds and manages various line information measured by a measuring device for each line. The line data server 43 is connected to a knowledge management server 61, and the knowledge management server 61 is connected to the Internet 18, and the design data servers (Dg) 50 to 53 of the plurality of fabless 13 to 16 are connected to the Internet 18. . As in the system of the first embodiment, the knowledge management server 61 and the design data servers 50 to 53 can exchange information with each other via the Internet 18.
Therefore, in the meantime, the charging method described in FIG. 5 and the security method described in FIG. 6 may be applied as they are. The line data server 43 and the knowledge management server 61 are connected to an intranet or a LAN.
, And information can be exchanged with each other. Since both belong to the same organization, a method unique to the intranet or LAN may be adopted for accounting and security.

The knowledge management server 61 obtains device information of a line from the line data server 43 and obtains information of chips designed by the fabless devices 13 to 16 from the design data servers 50 to 53. still,
Each of the servers 43, 50 to 53, and 61 is realized by a computer device such as a personal computer or an engineering workstation having an Internet connection function, an information processing function, and an information storage function.

The knowledge management server 61 manages information obtained from the line data server 43 and the design data servers 50 to 53, integrates information from both, and generates or processes information that is effective for both. A service is provided that provides information and processed information in response to requests from the line data server 43 and the design data servers 50 to 53.

This service provides the line data server 43 and the design data servers 50 to 53 with each other by processing one of the information into an effective form and providing it to the other. In other words, information obtained from both parties is integrated, and effective information is generated and provided to the other party in consideration of one situation. For example,
In FIG. 2, the knowledge management server 61 provides a product yield information providing process SV1a, a proper chip unit price providing process SV2a, a circuit design device parameter providing process SV3a, and a circuit design pre-silicon device parameter providing process SV4a. Perform offer processing.

The product yield information providing process SV1a is based on the device information of the fab 10A and the design data obtained from the fabless 13-16, and the product yield when the product requested by the fabless 13-16 is manufactured by the fab 10A. This is a process for generating and providing stay information. This process can generate product yield information for each production line, and is substantially the same as the process SV1 for providing product yield information.

The appropriate chip unit price providing process SV2a is a process of generating and providing a chip unit price that matches the balance from the product yield and the wafer unit price desired by the fab. The fabless units 13 to 16 (design data servers 50 to 53) ) Is given to the service requester. This process is substantially the same as the appropriate chip unit price providing process SV2.

In the circuit design device parameter providing process SV3a, a service request source among the fabless 13 to 16 (design data servers 50 to 53) designs a circuit from the data of the line data server 43 (data for each production line). This is the process of generating the device parameters necessary for this and providing it to the request source. This process is substantially the same as the circuit design device parameter providing process SV3.

The process of providing the pre-silicon device parameters for circuit design SV4a is based on the device information of each production line of the line data server 43 and the device conditions of the unknown device.
This is a process for generating and providing pre-silicon device parameters necessary for the circuit design by the service requester of (1) to (53). This process is substantially the same as the process SV4 for providing pre-silicon device parameters for circuit design.

Even in the configuration in which the fab 10A has the knowledge management server 61, in the knowledge management server 61, a situation in which the fabless for designing the LSI and the fab for manufacturing the LSI are managed as separate companies is becoming apparent. Among them, as described above, a service can be provided in which information of the fab 10A and the information of the fabless 13 to 16 are integrated to generate or process effective information for both. Therefore, the fabless units 13 to 16 can determine whether it is costly and timely to order a product from the fab 10A, which can contribute to cost reduction and QTAT in product development. .

<< Third System Configuration >> FIG. 3 shows a third information processing system according to the present invention connected to a network.
Is exemplified. In this example, the representative fabless 13A is a knowledge management server (KMS).
(1st): first computer device) 62.
That is, the fabless 13A is connected to the design data server (Dg
(3rd): third computer device) 54 and a knowledge management server 62. Design data server 5
Reference numeral 4 stores and manages design data of an LSI designed inside the fabless 13A. The design data server 54 is connected to the knowledge management server 62, and the knowledge management server 62 is connected to the Internet 18, and the Internet 18 has the plurality of fabs 10 to 10.
Twelve line data servers 40 to 42 are connected. As in the system of the first embodiment, the knowledge management server 62 and the line data servers 40 to 42 can exchange information with each other via the Internet 18. Therefore, in the meantime, the charging method described in FIG. 5 and the security method described in FIG. 6 may be applied as they are. The design data server 54 and the knowledge management server 62 are connected to an intranet or a LAN.
, And information can be exchanged with each other. Since both belong to the same organization, a method unique to the intranet or LAN may be adopted for accounting and security.

The knowledge management server 62 obtains device information and the like of the manufacturing lines 20 to 22 from the line data servers 40 to 42, and obtains the design data server 54
From the fabless 13A. Each of the servers 40 to 42, 54, 62
For example, it is realized by a computer device such as a personal computer or an engineering workstation having an Internet connection function, an information processing function, and an information storage function.

The knowledge management server 62 manages information obtained from the line data servers 40 to 42 and the design data server 54, integrates information from both, and generates or processes information effective for both, and generates the information. The information and the processed information are transmitted to the line data servers 40 to 42.
And a service provided in response to a request from the design data server 54.

This providing service is to process the line data servers 40 to 42 and the design data server 54 so that one of the information is processed into an effective form for the other and provide the processed information. In other words, information obtained from both parties is integrated, and effective information is generated and provided to the other party in consideration of one situation. For example,
In FIG. 3, the knowledge management server 61 performs an appropriate wafer unit price providing process SV2b, a line yield improving measure providing process SV5b, and a lot input timing data providing process SV7.
b. service providing process is performed.

The process of providing the appropriate wafer unit price SV2b is a process of obtaining a wafer unit price matching the balance from the product yield and the chip unit price desired by the fabless. It is given to a service request source among the data servers 40 to 42. This processing is substantially the same as the processing SV2.

The provision processing SV5b of the line yield improvement measure is as follows.
While considering circuit characteristics such as whether to operate at high speed based on benchmark circuits, for multiple process conditions,
This is a process for optimizing device conditions and process conditions.
The service requester is provided to the service requester out of 42. This processing is S
This is substantially the same as the processing of V5.

Provision processing of lot input timing data SV7b
From the time-series device variation data, wiring variation data, foreign matter data provided by the fabs 10 to 12 and the number of products requested by the fabless design data server 54 and the requested delivery date, the delivery date and the number of the products are reduced. This is a process of generating data of a lot input time to satisfy with the wafer of the above and providing the data to the fabs 10 to 12. This processing is substantially the same as the processing SV7.

As shown in FIG. 3, the fabless 13A
Has a knowledge management server 62, however, the knowledge management server 62 has been described in a situation where the fabless for designing the LSI and the fab for manufacturing the LSI are managed as separate companies. As described above, it is possible to perform a service that integrates the information as its own fabless 13A and the information of the fabs 10 to 12 to generate or process effective information for both of them. Therefore, the fabs 10 to 12 can obtain information for increasing the lot input timing and the yield.

The invention made by the present inventor has been specifically described based on the embodiments. However, it is needless to say that the present invention is not limited to the embodiments and can be variously modified without departing from the gist of the invention. No.

For example, the contents of the service provided by the knowledge management server are not limited to those shown in FIGS. 1 to 3 and can be changed as appropriate. It manages information obtained from fabs and fabless, integrates information from both to generate or process information that is valid for both parties, and responds to requests from fabs and fabless by using the generated information and processed information. And the like provided by the service.

In the example shown in FIG. 1, the fab has one line data server, the fabless has one design data server, and the fab is described as being equivalent to the one line data server. Although fabless is described as being equivalent to one design data server, it is natural that each fab or fabless may be provided with a plurality of data servers. Provision is performed in line data server units and design data server units.

[0172]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, information of both fabless and fab can be integrated to generate and provide effective information for both.

It is possible to provide one of fabless or fab information by converting the information into information that is valid for the other, or by adding information that is valid for the other to the one information.

The information of one of fabless and fab can be converted into information effective for the one, or the one of the information can be provided with added value.

For example, based on information of a device manufactured by a fab and information of a chip designed by a fabless, LS
It becomes possible to generate parameter information, yield information, chip unit price, and other information necessary for the design of I to produce fabless information, and to generate information to increase the yield and provide it to the fab. Since the fabless can determine which fab to order the product for in terms of cost and time, it is possible to reduce the cost and make the product development QTAT.
In addition, the fab can obtain information for increasing the yield, and since the fabless can be provided with a line for ordering products, an effect of improving sales can be expected.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a first embodiment of an information processing system according to the present invention connected to a network.

FIG. 2 is a block diagram illustrating a second embodiment of the information processing system according to the present invention connected to a network.

FIG. 3 is a block diagram illustrating a third embodiment of the information processing system according to the present invention connected to a network.

FIG. 4 is a flowchart illustrating an example of a relationship between service providing processes by a knowledge management server.

FIG. 5 is an explanatory diagram illustrating a billing method between a fab and a fabless and a service provider.

FIG. 6 is an explanatory diagram illustrating security measures between a fab and a fabless and a service provider.

FIG. 7 is an explanatory diagram of information input / output regarding provision processing of product yield data, wafer unit price, and chip unit price.

FIG. 8 is an explanatory diagram of input / output of information regarding provision processing of device parameters for circuit design.

FIG. 9 is an explanatory diagram of first information input / output relating to processing for providing a line yield improvement measure.

FIG. 10 is an explanatory diagram of second information input / output relating to a process of providing a line yield improvement measure.

FIG. 11 is an explanatory diagram of information input / output relating to a pre-silicon parameter providing process.

FIG. 12 is an explanatory diagram of information input / output relating to a process of providing a line placement.

FIG. 13 is an explanatory diagram of information input / output relating to a process of providing lot input timing data.

FIG. 14 is a data flow of product yield calculation according to [1] to [4] described in FIG.

FIG. 15 is a data flow for obtaining an appropriate unit price of a wafer described in FIG. 7;

FIG. 16 is a data flow for obtaining an appropriate unit price of a chip described with reference to FIG. 7;

FIG. 17 is a data flow for generating device parameters for design described in FIG. 8;

FIG. 18 is a data flow for seeking a yield improvement measure described with reference to FIG. 9;

FIG. 19 is a data flow for seeking a yield improvement measure exclusively for a fabless product as described with reference to FIG. 10;

FIG. 20 is a data flow for generating pre-silicon device parameters for circuit design described in FIG. 11;

FIG. 21 is a fabless 13 to 16 described with reference to FIG.
3 is a data flow when a production line is introduced to a service request source.

FIG. 22 is a data flow for obtaining the lot input timing of the product described in FIG.

FIG. 23 is a flowchart illustrating a processing method of device parameter extraction (T1) from the viewpoint of a data flow.

FIG. 24 is a flowchart illustrating a device parameter extraction process (T1) from the viewpoint of a processing procedure.

FIG. 25 is a flowchart illustrating a method of statistical device parameter extraction processing (T2) from the viewpoint of data flow.

FIG. 26 is a flowchart illustrating a method of statistical device parameter extraction processing (T2) from the viewpoint of a processing procedure.

FIG. 27 is a flowchart illustrating a process of circuit characteristic variation analysis (T3).

FIG. 28 is a flowchart illustrating a processing flow of characteristic yield calculation (T4).

FIG. 29 is a flowchart illustrating a processing flow of a product yield calculation (T6).

FIG. 30 is a flowchart illustrating a processing flow of calculating a wafer price (T7).

FIG. 31 is a flowchart illustrating a processing flow of chip unit price calculation (T8).

FIG. 32 is a flowchart illustrating a processing flow of worst and best parameter generation (T9).

FIG. 33 is a flowchart illustrating a processing flow of device robust design (T10).

FIG. 34: Pre-silicon device parameter generation (T1)
It is a flowchart which illustrates the processing flow of 2).

FIG. 35 is a flowchart illustrating a process flow of calculating a product delivery date (T3).

FIG. 36: Calculation of lot input timing and period of product (T1)
It is a flowchart which illustrates the processing flow of 4).

FIG. 37 is an explanatory diagram schematically illustrating a process of statistical device parameter extraction (T2).

FIG. 38 is an explanatory diagram illustrating a difference in parameters extracted between a short channel MOS transistor and a long channel MOS transistor;

FIG. 39 is an explanatory diagram illustrating an example of a circuit characteristic variation analysis;

FIG. 40 is an explanatory diagram illustrating an example of a characteristic yield calculation.

FIG. 41 is an explanatory diagram illustrating an example of worst and best parameter generation processing;

FIG. 42 is an explanatory view exemplifying a state in which device characteristics manufactured in a line vary periodically with a cleaning timing of a manufacturing line.

FIG. 43 is an explanatory diagram illustrating a state in which the yield of high-speed products fluctuates in synchronization with a cleaning cycle of a manufacturing line.

FIG. 44 is an explanatory diagram illustrating a process condition expression;

FIG. 45 is an explanatory diagram showing an example of information indicating the order status of a fab.

FIG. 46 is an explanatory diagram showing a data providing source and providing timing for various types of data such as typical device data used by the knowledge management server.

[Explanation of symbols]

 10A, 10-12 Fab 13A, 13-16 Fabless 17 Service provider 18 Network 20-22 Manufacturing line 30-32 Measuring instrument 40-42,43 Line data server 50-53,54 Design data server 60,61,62 Knowledge management server

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Joe Yoji 5-2-1, Josuihoncho, Kodaira-shi, Tokyo Within the Semiconductor Group, Hitachi, Ltd. (72) Kosuke Okuyama In-house Kosuihonchogo, Kodaira-shi No. 20-1 in Hitachi Semiconductor Group, Ltd. (72) Megumi Kawakami, Inventor 5--20-1, Kamimizu Honcho, Kodaira-shi, Tokyo F-Term in Hitachi Semiconductor Group, Ltd. F-term (reference) 5F064 HH06 HH09 HH11 HH12

Claims (63)

[Claims] 1. A computer device that can be connected to a transmission line, wherein the computer device is connected via the transmission line
Receiving element characteristic information of a semiconductor element and design information of a semiconductor integrated circuit, responding to a request from a source of the element characteristic information, generating response information to the request source based on the received information; An information processing system capable of executing a process of returning generated response information to the request source. 2. The information processing system according to claim 1, further comprising a plurality of other computer devices capable of outputting said element characteristic information to said transmission path. 3. The information processing system according to claim 1, further comprising a plurality of other computer devices capable of outputting the design information to the transmission path. 4. A computer device connectable to a transmission line, wherein the computer device is connected via the transmission line,
Upon receiving the device characteristic information of the semiconductor device and the design information of the semiconductor integrated circuit, in response to a request from a supplier of the device characteristic information, response information to the request source is transmitted to the semiconductor integrated circuit by the device characteristic information. An information processing system capable of executing a process of generating a response assuming use of the element specified in (1) and returning the generated response information to the request source. 5. The information processing system according to claim 4, further comprising a plurality of other computer devices capable of outputting said element characteristic information on said transmission path. 6. The information processing system according to claim 4, further comprising a plurality of other computer devices capable of outputting the design information to the transmission path. 7. The semiconductor device according to claim 7, wherein the response information is a chip presented by a predicted yield information and a design information supply source of the semiconductor integrated circuit when it is assumed that the semiconductor integrated circuit is configured using an element specified by the element characteristic information. 5. The information processing system according to claim 1, further comprising wafer unit price information generated based on the unit price information. 8. The method according to claim 7, wherein the response information is formed based on time-series element characteristic information of the semiconductor element and a required amount of the semiconductor integrated circuit and a production deadline given from a supplier of the design information. 5. The information processing system according to claim 1, further comprising information relating to a required amount of the semiconductor integrated circuit and a lot input timing satisfying a delivery date. 9. A computer device connectable to a transmission line, wherein the computer device is connected via the transmission line,
Receiving the element characteristic information of the semiconductor element and the design information of the semiconductor integrated circuit, in response to a request from the supply source of the design information, generating response information to the request source based on the received information, An information processing system capable of executing a process of returning generated response information to the request source. 10. The information processing system according to claim 9, further comprising a plurality of other computer devices capable of outputting said element characteristic information on said transmission path. 11. The information processing system according to claim 9, further comprising a plurality of other computer devices capable of outputting said design information to said transmission path. 12. A computer device that can be connected to a transmission line, wherein the computer device receives, via the transmission line, element characteristic information of a semiconductor element and design information of a semiconductor integrated circuit, and receives the design information of the semiconductor integrated circuit. In response to a request from a supply source, response information to the request source is generated on the assumption that an element specified by the element characteristic information is used in the semiconductor integrated circuit, and the generated response information is generated. An information processing system capable of executing a process of returning to a request source. 13. The information processing system according to claim 12, wherein a plurality of other computer devices capable of outputting said element characteristic information are provided on said transmission path. 14. The information processing system according to claim 12, further comprising a plurality of other computer devices capable of outputting said design information to said transmission path. 15. The response information according to claim 9, wherein the response information includes predicted yield information assuming that the semiconductor integrated circuit is configured using an element specified by the element characteristic information. Information processing system. 16. The apparatus according to claim 15, wherein the response information includes chip unit price information generated based on the predicted yield information and wafer unit price information presented by the element characteristic information supply source. Information processing system. 17. The semiconductor device according to claim 9, wherein the response information includes information on a layout structure for a semiconductor integrated circuit for improving variation in circuit characteristics of a benchmark circuit provided from a source of the design information. 13. The information processing system according to item 12. 18. The method according to claim 18, wherein said response information is chip unit price information obtained from predicted unit yield information of said semiconductor integrated circuit and wafer unit price information provided from a supplier of said design information, and a manufacturing unit provided from a supplier of element characteristic information. 16. The information processing system according to claim 15, further comprising a line congestion state and a completion time of a required wafer obtained based on a throughput of the manufacturing line. 19. A computer device that can be connected to a transmission line, wherein the computer device can receive element characteristic information of a semiconductor element via the transmission line.
In response to the request via the transmission path, generate device parameters for simulating the element characteristics specified by the received element characteristic information, and return the generated device parameters to the request source via the transmission path An information processing system capable of executing processing. 20. The information processing system according to claim 19, further comprising a plurality of other computer devices capable of outputting said element characteristic information on said transmission path. 21. The information processing system according to claim 19, further comprising a plurality of further computer devices capable of outputting said request to said transmission path. 22. A computer device which can be connected to a transmission path, wherein the computer apparatus can receive element characteristic information of a first semiconductor element and element conditions of a second semiconductor element via the transmission path. And generating a pre-silicon device parameter for simulating the device characteristics of the second semiconductor device based on the received device characteristics information and the device conditions in response to a request via the transmission line. An information processing system capable of executing a process of returning a silicon device parameter to the request source via the transmission path. 23. The information processing system according to claim 22, wherein the transmission path includes a plurality of other computer devices capable of outputting the element characteristic information and the element conditions. 24. The information processing system according to claim 22, further comprising a plurality of other computer devices capable of outputting said request to said transmission path. 25. A computer device connectable to a transmission line, said computer device receiving, via the transmission line, element characteristic information of a semiconductor element and benchmark circuit information using the element, and receiving the element characteristic information. In response to a request from a source of benchmark circuit information, a process of returning response information obtained assuming that a benchmark circuit is configured using an element specified by the element characteristic information to the requestor can be performed. An information processing system, characterized in that: 26. The information processing system according to claim 25, wherein the transmission path includes a plurality of other computer devices capable of outputting the element characteristic information and the benchmark circuit information. 27. The information processing system according to claim 25, wherein the response information includes information on a process condition and a device structure for a semiconductor element for improving variation in circuit characteristics of the benchmark circuit. 28. A computer having a first computer device connectable to a transmission path and a second computer device connected to the first computer device, wherein the first computer device comprises:
Device characteristic information of a semiconductor element is input from the second computer device, and design information of the semiconductor integrated circuit is received via the transmission line, and in response to a request from the second computer, An information processing system capable of executing a process of generating response information based on the input information and returning the generated response information to the second computer. 29. The information processing system according to claim 28, further comprising a plurality of third computer devices capable of outputting said design information to said transmission path. 30. A computer having a first computer device connectable to a transmission line and a second computer device connected to the first computer device, wherein the first computer device comprises:
Device characteristic information of a semiconductor element is input from the second computer device, design information of the semiconductor integrated circuit is received via the transmission line, and in response to a request from the second computer, response information to the request source is received. Is generated assuming that an element specified by the element characteristic information is used for the semiconductor integrated circuit, and a process of returning the generated response information to the second computer can be executed. Processing system. 31. The information processing system according to claim 30, comprising a plurality of third computer devices capable of outputting said design information to said transmission path. 32. A computer having a first computer device connectable to a transmission path and a second computer device connected to the first computer device, wherein the first computer device comprises:
Device characteristic information of a semiconductor element is input from the second computer device, design information of the semiconductor integrated circuit is received via the transmission line, and in response to a request from a supply source of the design information, An information processing system capable of executing a process of generating response information based on the input information and returning the generated response information to the request source. 33. The information processing system according to claim 32, comprising a plurality of third computer devices capable of outputting said design information to said transmission path. 34. A computer having a first computer device connectable to a transmission line and a second computer device connected to the first computer device, wherein the first computer device includes:
Device characteristic information of a semiconductor element is input from the second computer device, design information of the semiconductor integrated circuit is received via the transmission line, and in response to a request from a supply source of the design information, An information processing system capable of executing a process of generating response information on the assumption that an element specified by the element characteristic information is used, and returning the generated response information to the request source. 35. The information processing system according to claim 34, comprising a plurality of third computer devices capable of outputting said design information to said transmission path. 36. The response information according to claim 32, wherein the response information includes predicted yield information assuming that the semiconductor integrated circuit is configured using an element specified by the element characteristic information. Information processing system. 37. The apparatus according to claim 36, wherein the response information includes chip unit price information generated based on the predicted yield information and wafer unit price information presented by the element characteristic information supplier. Information processing system. 38. A computer having a first computer device connectable to a transmission line and a second computer device connected to the first computer device, wherein the first computer device includes:
Device characteristic information of a semiconductor device can be input from the second computer device, and in response to a request from a transmission line, device parameters for simulating the device characteristic specified by the input device characteristic information are generated. An information processing system capable of executing a process of returning the generated device parameter to the request source. 39. The information processing system according to claim 38, comprising a plurality of third computer devices capable of outputting said request to said transmission path. 40. A computer having a first computer device connectable to a transmission path and a second computer device connected to the first computer device, wherein the first computer device comprises:
Device characteristic information of the first semiconductor device and device condition of the second semiconductor device can be input from the second computer device, and the input device characteristic information and the device condition are input in response to a request from the transmission line. Generating a pre-silicon device parameter for simulating the device characteristics of the second semiconductor device based on the above, and returning the generated pre-silicon device parameter to the request source via the transmission line. Characteristic information processing system. 41. The information processing system according to claim 40, comprising a plurality of third computer devices capable of outputting said request to said transmission path. 42. A computer having a first computer device connectable to a transmission line and a third computer device connected to the first computer device, wherein the first computer device comprises:
Receiving element characteristic information of the semiconductor element through the transmission path,
Design information of a semiconductor integrated circuit is input from the third computer device, and in response to a request from a source of the element characteristic information, response information to the request source is converted into the received information and the input information. An information processing system capable of executing a process of generating the response information based on the request information and returning the generated response information to the request source. 43. The information processing system according to claim 42, comprising a plurality of second computer devices capable of outputting said element characteristic information to said transmission path. 44. A computer having a first computer device connectable to a transmission path and a third computer device connected to the first computer device, wherein the first computer device comprises:
Receiving element characteristic information of the semiconductor element through the transmission path,
Design information of a semiconductor integrated circuit is input from the third computer device, and in response to a request from a supplier of the element characteristic information, response information to the request source is transmitted to the semiconductor integrated circuit by the element characteristic information. An information processing system, which is capable of executing a process of generating the response information on the assumption that a specified element is used and returning the generated response information to the request source. 45. The information processing system according to claim 44, further comprising a plurality of second computer devices capable of outputting said element characteristic information to said transmission path. 46. The response information includes predicted yield information and chip unit price information presented by a semiconductor integrated circuit design information supplier when it is assumed that the semiconductor integrated circuit is constituted by the element specified by the element characteristic information. 43. The apparatus according to claim 42, further comprising: wafer unit price information generated based on
Or the information processing system according to 44. 47. The response information, wherein the response information is formed based on a time-series element characteristic information of a semiconductor element and a required amount and a production deadline of the semiconductor integrated circuit given from a supply source of the design information. 45. The information processing system according to claim 42, further comprising information relating to a lot input time that satisfies the delivery date and the number of semiconductor integrated circuits. 48. A computer having a first computer device connectable to a transmission line and a third computer device connected to the first computer device, wherein the first computer device comprises:
Through the transmission path, receives element characteristic information of a semiconductor element and benchmark circuit information using the element, and in response to a request from a supplier of the element characteristic information and the benchmark circuit information, is specified by the element characteristic information. An information processing system capable of executing a process of returning response information obtained assuming that a benchmark circuit is configured by using elements to the request source. 49. The information processing system according to claim 48, wherein a plurality of second computer devices capable of outputting said element characteristic information and said benchmark circuit information are provided on said transmission path. 50. The information processing system according to claim 48, wherein the response information includes information on a process condition and a device structure for a semiconductor element for improving a variation in circuit characteristics of the benchmark circuit. 51. A computer having a first computer device connectable to a transmission line and a third computer device connected to the first computer device, wherein the first computer device includes:
Receiving element characteristic information of the semiconductor element through the transmission path,
Design information of a semiconductor integrated circuit is input from the third computer device, and in response to a request from the third computer device, response information to the request source is determined based on the received information and the input information. An information processing system capable of executing a process of generating and returning the generated response information to the requesting third computer device. 52. The information processing system according to claim 51, comprising a plurality of second computer devices capable of outputting said element characteristic information to said transmission path. 53. A computer having a first computer device connectable to a transmission line and a third computer device connected to the first computer device, wherein the first computer device comprises:
Receiving element characteristic information of the semiconductor element through the transmission path,
Design information of a semiconductor integrated circuit is input from the third computer device, and in response to a request from the third computer device, response information to the request source is specified in the semiconductor integrated circuit by the element characteristic information. An information processing system capable of executing a process of generating the response information assuming use of the element and returning the generated response information to the requesting third computer device. 54. The information processing system according to claim 53, comprising a plurality of second computer devices capable of outputting said element characteristic information to said transmission path. 55. A process for inputting element characteristic information of a semiconductor device from a fab server having a semiconductor integrated circuit manufacturing line via a network, and a process for inputting device characteristic information of a semiconductor device from the fabless server for designing the semiconductor integrated circuit via the network. A process of inputting design information of the device, and a process of generating predicted yield information of the product based on the input device characteristic information and design information, assuming that the product required by the fabless is manufactured by the fab. An information processing method comprising: 56. The method according to claim 5, further comprising a step of generating wafer unit price information based on the predicted yield information and chip unit price information presented from the fabless.
5. The information processing method according to item 5. 57. The information processing method according to claim 55, further comprising a step of generating chip unit price information based on said predicted yield information and wafer unit price information presented from said fab. 58. A process of estimating a completion time of a required wafer based on a production line congestion state and a production line throughput inputted from the fab server, and the chip unit price information and the completion time information are transmitted via a network. 58. The information processing method according to claim 57, further comprising: processing to supply to a fabless server. 59. A delivery date and number of semiconductor integrated circuits based on time-series element characteristic information of a semiconductor device inputted from a fabless server, and a required amount and a production delivery date of a semiconductor integrated circuit inputted from a fabless server. 58. The information processing method according to claim 57, further comprising a process of generating information on a lot input timing satisfying the following. 60. A process for inputting element characteristic information of a semiconductor element from a fab server having a semiconductor integrated circuit manufacturing line via a network, and a circuit for designing a circuit based on the input element characteristic information. An information processing method comprising: a process of generating device parameters required for a simulation; and a process of supplying the generated device parameters to a fabless server for designing a semiconductor integrated circuit via a network. 61. A process of inputting element characteristic information of a first semiconductor element and element conditions of a second semiconductor element from a fab server having a production line of a semiconductor integrated circuit via a network; Processing for generating a pre-silicon device parameter for simulating the device characteristics of the second semiconductor device based on the device condition, and generating the pre-silicon via a network to a fabless server for designing a semiconductor integrated circuit. An information processing method comprising: supplying a device parameter. 62. A process for inputting element characteristic information of a semiconductor device from a fab server having a semiconductor integrated circuit manufacturing line via a network, and a process for inputting device characteristic information from a fabless server for designing the semiconductor integrated circuit via the network. A process of inputting the design information of, and a process of generating, based on the input device characteristic information and design information, improvement measure information on a layout structure for improving a variation in circuit characteristics of a benchmark circuit included in the design information. Supplying the generated improvement measure information to the fabless server via a network. 63. A process of inputting element characteristic information of a semiconductor element and benchmark circuit information using the semiconductor element from a fab server having a semiconductor integrated circuit manufacturing line via a network, and the input element characteristic information and the benchmark. A process of generating improvement information on a process condition and a device structure for a semiconductor element for improving the circuit characteristic variation of the benchmark circuit based on the circuit information; and transmitting the generated improvement information to the fab server by a network. And a process of supplying the information via a computer.