JP2002351672A - Device and method for processing assembler, and program for making computer execute the same method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To generate a program capable of performing the same processing even when it is operated by any of a big endian and a little endian. SOLUTION: In this assembler processor 1 having an instruction set consisting of 16 bit length instruction and 32 bit length instruction and to generate an instruction code corresponding to a processor in which execution orders of two 16 bit length instruction codes are replaced when it is operated by a different endian, it is provided with a temporary storage buffer 5 to temporarily store the 16 bit length instruction code converted from a source file, an arrangement converting part 6 to replace the two 16 bit length instruction codes arranged in the temporary storage buffer 5 on the boundary of 32 bit and an file output part 7 to output the two replaced 16 bit length instruction codes to an object file.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an assembler processing apparatus, an assembler processing method, and a program for causing a computer to execute an assembler processing method for generating, from a source file, an instruction file to be executed by a processor.・
The present invention relates to an assembler processing device that generates an instruction code (machine language) to be executed by a processor, an assembler processing method, and a program that causes a computer to execute the method.

[0002]

2. Description of the Related Art FIG. 18 is a block diagram showing a configuration of a conventional assembler for inputting a source file, converting the source file into an object file, and outputting the converted object file. Conventional assembler
As shown in FIG. 18, the configuration includes a file input unit 12, a syntax analysis unit 13, a code conversion unit 14, and an object file output unit 17. FIG.
Is a flowchart of assembler processing by a conventional assembler. FIG. 14 is an explanatory diagram showing a part of the code conversion table 10 referred to by the code conversion unit 14. Here, in FIG. 14, the code conversion table 10 is a table in which mnemonics 18 in assembly language are associated with machine languages (instruction codes) 19 converted from each mnemonic.

As shown in FIG. 19, in a conventional assembler, a source file is read from a file input unit 12, and a command described in the read source file is analyzed by a syntax analysis unit 13. After the analysis, the code conversion unit 14 converts the mnemonic into a machine language (instruction code) by referring to the code conversion table 10. The converted machine language is sequentially output to a file by the file output unit 17 to generate an object file.

[0004] In recent years, processors that can operate by switching between big endian and little endian have appeared. Here, big endian is a byte ordering scheme in which the most significant byte of data is assigned to the lowest address in memory, and little endian is byte ordering in which the least significant byte of data is assigned to the lowest address in memory. Refers to the method. When the processor supports both endians (bi-endian), the machine language itself executed by the processor is common regardless of the endian regardless of whether the processor operates in big endian or little endian. When a conventional bi-endian assembler outputs a machine language to an object file, the machine language and data to be handled are output as a memory image by changing a byte sequence according to each endian.

FIG. 15 is an explanatory diagram showing a state in which a mnemonic is converted into a machine language and stored in a memory in hexadecimal notation and a memory. FIG. 15 shows a relationship between a mnemonic 20 described in an assembly language, a machine language (instruction code) 21 corresponding to the mnemonic 20, and an address 22 when each instruction is arranged on a memory.
In FIG. 15, instruction A represents a 32-bit instruction, instructions B and C represent 16-bit instructions, and shows, as an example, a program described to be executed in the order of instructions A, B, and C.

FIGS. 16 and 17 show a case where a code obtained by converting the program into a machine language using the assembler 11 is output as an object file, and the machine language of the object file is expanded on a memory of a system for executing the program. FIG. 4 is an explanatory diagram showing a memory image of FIG. FIG.
6 shows an arrangement 23 of instruction codes on a memory when performing a big endian operation, and FIG. 17 shows an arrangement 24 of instruction codes on a memory when performing a little endian operation. In either state, the instruction code generated by the assembler has an instruction A at address 0, an instruction B at address 4 and an instruction C at address 6, and a normal processor has instructions A, B, Execution is performed in the order of the instruction C.

[0007]

A processor operating in big endian and having two instruction lengths of 16 bits and 32 bits has been generally known. FIG. 12 is a schematic diagram showing instruction codes of this type of processor. FIG. 13 is a flowchart showing the operation of the processor. As shown in FIG. 13, the processor comprises:
Data is read from the object file in 32-bit units. If the fetched data is a 32-bit instruction code, the instruction code is executed. On the other hand, if the fetched data is a 16-bit instruction code consisting of two instructions, the upper 16-bit instruction code (16-bit instruction 1 in FIG. 12) is executed first, and the lower 16 bits (in FIG. 12). , 16-bit instruction 2). Also, the most significant bit of the lower 16 bits is used as a simultaneous execution flag bit, and when this bit is 1, the two read instruction codes are executed in parallel,
When it is 0, two 16-bit instruction codes are sequentially executed as described above.

There is a processor in which the bus interface of such a processor operating in big endian is modified so that it can operate in little endian different from the conventional one. The processor with such a modification also executes the instruction execution processing as in the flowchart of FIG.

When this processor operates in the big endian mode, when the instruction of the memory image shown in FIG. 16 is executed, the 32-bit [0x90F0123] of the address 0 is obtained.
4] as a read instruction A. Next, 32-bit [0x00C27F20] at address 4 is read, and instruction B at address 4 and instruction C at address 6 are executed in this order.

On the other hand, when the processor operates in little endian, 32 bits [0x90F01234] at address 0 are read out from the memory image shown in FIG. Next, 32 bits [0x7F2000C2] at address 4 are read and executed in the order of instruction C at address 6, instruction B at address 4.

As described above, when two instruction codes having a 16-bit length are sequentially executed in the processor, the execution order of the instructions is reversed between the big endian and the little endian. Become.

For this reason, when creating a program to be executed by the processor performing the above operation in the little endian operation, coding is performed in consideration of the fact that the address is reversed when two 16-bit instruction codes are sequentially executed. There is a need to do. However, when writing in assembly language, it is difficult to describe a program under such restrictions because it is not necessary to describe whether the instruction to be used is 32-bit length or 16-bit length. There was a problem that the production efficiency of software deteriorated.

The present invention has been made in view of the above,
It is an object of the present invention to provide an assembler processing apparatus capable of generating a program that performs the same processing regardless of which endian is operated, efficiently developing an assembly language program, and improving software production efficiency.

[0014]

In order to achieve the above object, an assembler processing apparatus according to the present invention has an instruction set consisting of a 16-bit instruction and a 32-bit instruction, and operates at different endians. 1
In an assembler processing apparatus for generating an instruction code corresponding to a processor in which the execution order of a 6-bit instruction code is exchanged, a storage means for temporarily storing a 16-bit instruction code code-converted from a source file; An arrangement conversion means for exchanging two 16-bit instruction codes arranged on a 32-bit boundary in accordance with an endian of an operation target, and a file output for outputting the two exchanged 16-bit instruction codes to an object file Means.

According to the present invention, the 16-bit instruction code code-converted from the source file is temporarily stored in the storage means, and the two 16-bit instruction codes arranged at the 32-bit boundary are stored in the storage means. Since two 16-bit instruction codes are output to the object file by replacing them according to the endian of the operation target, the same source of the assembly language description can be used even if the processor operates in either big endian or little endian endian. It is possible to generate an object file that executes the same processing using the file, and it is possible to improve the productivity of software.

[0016] In the assembler processing apparatus according to the next invention, in the above-mentioned invention, the arrangement conversion means, when a 16-bit instruction code is stored in the storage means,
Further, a 16-bit NOP instruction code is added to the storage means.

According to the present invention, when the 16-bit instruction code is stored in the storage means, a 16-bit NOP instruction code is further added to the storage means.
By arranging a 6-bit instruction at a 32-bit boundary, it is possible to ignore that a 16-bit instruction is an execution operation that goes backward to an address during little endian operation. Further, when the correspondence between the memory image and the mnemonic is displayed in the disassembly, the coded procedure is output as it is, so that the verification is convenient and the software development can be made more efficient.

An assembler processing apparatus according to the next invention is a processor having an instruction set consisting of a 16-bit instruction and a 32-bit instruction and in which the execution order of two 16-bit instruction codes is switched when operating in different endian. In an assembler processing apparatus for generating a corresponding instruction code, a code associating a mnemonic of a compound instruction defined as one 32-bit instruction by combining two 16-bit instructions and an instruction code of the compound instruction A conversion table and code conversion means for converting the compound instruction read from a source file into an instruction code corresponding to the compound instruction with reference to the code conversion table are provided.

According to the present invention, one 32-bit instruction obtained by combining two 16-bit instructions is defined as a compound instruction, and a code conversion table in which mnemonics of the compound instruction are associated with instruction codes. Is defined. Then, since the composite instruction read from the source file is code-converted into the instruction code of the composite instruction using the code conversion table, all the generated instruction codes have a 32-bit length. For this reason, the reverse execution of the instruction during the little endian operation of the processor can be reliably eliminated, and the amount of code can be optimized.

The assembler processing method according to the next invention is directed to a processor having an instruction set including a 16-bit length instruction and a 32-bit length instruction, and in which the execution order of two 16-bit length instruction codes is switched when operating in different endian. In an assembler processing method for generating a corresponding instruction code, a storage step of temporarily storing a 16-bit instruction code converted from a source file in a storage means; And a file output step of outputting the replaced two 16-bit instruction codes to an object file. I do.

According to the present invention, the 16-bit instruction code code-converted from the source file is temporarily stored in the storage means, and the two 16-bit instruction codes arranged on the 32-bit boundary are stored in the storage means. Since two 16-bit instruction codes are output to the object file by replacing them according to the endian of the operation target, the same source of the assembly language description can be used even if the processor operates in either big endian or little endian endian. It is possible to generate an object file that executes the same processing using the file, and it is possible to improve the productivity of software.

[0022] In the assembler processing method according to the next invention, in the above-mentioned invention, the layout conversion step may include:
When a 6-bit instruction code is stored in the storage means, a 16-bit NOP instruction code is further added to the storage means.

According to the present invention, when the 16-bit instruction code is stored in the storage means, the 16-bit NOP instruction code is further added to the storage means.
By arranging a 6-bit instruction at a 32-bit boundary, it is possible to ignore that a 16-bit instruction is an execution operation that goes backward to an address during little endian operation. Further, when the correspondence between the memory image and the mnemonic is displayed in the disassembly, the coded procedure is output as it is, so that the verification is convenient and the software development can be made more efficient.

The assembler processing method according to the next invention is directed to a processor which has an instruction set consisting of a 16-bit instruction and a 32-bit instruction, and which switches the execution order of two 16-bit instruction codes when operating in different endians. In an assembler processing method for generating a corresponding instruction code, code conversion in which a mnemonic of a compound instruction defined as one 32-bit instruction by combining two 16-bit instructions and an instruction code of the compound instruction are associated with each other. A code conversion step of converting the compound instruction read from the source file into an instruction code corresponding to the compound instruction with reference to a table.

According to the present invention, one 32-bit instruction combining two 16-bit instructions is defined as a compound instruction, and a code conversion table in which mnemonics of the compound instruction are associated with instruction codes. Is defined. Then, since the composite instruction read from the source file is code-converted into the instruction code of the composite instruction using the code conversion table, all the generated instruction codes have a 32-bit length. For this reason, the reverse execution of the instruction during the little endian operation of the processor can be reliably eliminated, and the amount of code can be optimized.

A program according to the next invention is a program for causing a computer to execute the assembler processing method according to any one of the above-described inventions, and the program becomes machine-readable, thereby enabling the computer to execute the above-described invention. Any one of the operations can be performed by a computer.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of an assembler processing apparatus, an assembler processing method and a program for causing a computer to execute the method according to the present invention will be described below in detail with reference to the accompanying drawings.

Embodiment 1 FIG. 1 is a block diagram showing a configuration of the assembler according to the first embodiment of the present invention. The assembler according to the first embodiment is a bi-endian-compatible assembler that outputs an instruction code for big endian (machine language) and an instruction code for little endian (machine language) from a source file described in an assembler language as an object file. . Further, the assembler according to the first embodiment has an instruction code shown in FIG. 12 described above and generates an instruction code executed by a processor that performs the operation shown in the flowchart in FIG. 13 described above.

As shown in FIG. 1, a bi-endian assembler 1 according to the first embodiment includes a file input unit 2 for reading a source file, and an assembly language source code described in the source file read by the file input unit 2. A code analysis unit 3, a code conversion table 10, a code conversion unit 4 that converts the assembly language mnemonic into an instruction code (machine language) with reference to the code conversion table 10, and a converted instruction code Temporary storage buffer 5 for temporarily storing the instruction code, an arrangement conversion unit 6 for converting the arrangement of the instruction code stored in the temporary storage buffer 5, a converted instruction code or the temporary storage buffer 5
And a file output unit 7 that performs an output process on the converted instruction code stored in the file as an object file.

The code conversion table 10 is a table in which mnemonic notation of the assembler language is associated with instruction codes, and FIG. 14 is an explanatory diagram showing an example of the code conversion table 10. In the temporary storage buffer, when the assembler 1 is executed, an array of four byte data (char BUF [3]) is secured on the memory as the storage means. The arrangement conversion unit 6 converts the arrangement of the instruction codes stored in the temporary storage buffer 5 in byte units according to the operating endian.

Next, a description will be given of a processing procedure for generating an instruction code for big endian by the bi-endian-compatible assembler configured as described above. FIG.
9 is a flowchart showing a processing procedure for generating an instruction code for big endian.

The assembler 1 first stores an array of four byte data (cha) in the memory as the temporary storage buffer 5.
r BUF [3]) is secured and initialized (step S201). Then, one line of the source file described in the assembly language is read by the file input unit 2 (step S202), and the read source code is parsed by the parsing unit 3 (step S20).
3). After the syntax analysis, the code conversion unit 4 converts the source code into an instruction code (machine language) with reference to a code conversion table 10 (FIG. 14) in which a correspondence table between mnemonics and instruction codes (machine language) is described. (Step S2
04).

Then, the arrangement conversion unit 6 further performs the following arrangement conversion processing for generating an instruction code for big endian. First, the size of the code-converted instruction code is checked (step S205). If the instruction code has a 32-bit length, it is further checked whether or not the instruction code corresponding to the previous conversion remains in the temporary storage buffer 5 (step S206). If not, four bytes, one byte at a time, from the upper byte of the converted instruction code are stored in the temporary storage buffer 5 as BUF [0],
BUF [1], BUF [2], and BUF [3] are stored in this order (step S209). Then, the file output unit 7
Output the instruction code stored in the temporary storage buffer 5 to the object file (step S21).
3). The output order and the arrangement for each byte are BUFF
[0], BUF [1], BUF [2], and BUF [3] are output in order from the lower address (that is, MSB) of the object file in correspondence with big endian.

As a result of the code size check in step S205, if the converted instruction code has a 16-bit length, it is checked whether or not the previously converted instruction code remains in the temporary storage buffer 5 (step S205). Step S210). If not, the upper 8 bits of the 16-bit instruction code are stored in the BUF of the temporary storage buffer 5.
The lower 8 bits are stored in BUF [1] in [0] (step S211).

Next, the next one line of source code is read from the source file in the file input unit 2 (step S202), and the processing up to step S205 is similarly performed. If this instruction is a 16-bit instruction code, it is checked whether or not the instruction code of the previous conversion remains in the temporary storage buffer 5 (step S21).
0) In this case, the upper 8 bits of the newly converted instruction code are stored in BUF [2] and the lower 8 bits are stored in BUF [3] because they remain in BUF [0] and BUF [1]. (Step S212). Then, the file output unit 7
The BUF [0], BUF [1], BUF [2], BUF
In the order of F [3], the object file is output from the lower address (ie, MSB) of the object file in correspondence with the big endian (step S213).

In step S205, if the instruction code read and converted following the 16-bit instruction code is a 32-bit instruction code, whether the instruction code of the previous conversion remains in the temporary storage buffer 5 or not. It is checked whether or not it is not (step S206).
And BUF [1], so step S207
To BUF [2] and BUF of the temporary storage buffer 5
A 16-bit no-processing instruction (NOP) is additionally stored in [3]. Then, the instruction code stored in the temporary storage buffer 5 is converted by the file output unit 7 into BUF [0], B
Output in order of UF [1], BUF [2], and BUF [3] from the lower address (that is, MSB) of the object file corresponding to big endian (step S).
208) Then, the next 32-bit instruction code is stored in the temporary storage buffer 5 (step S209) and output to the object file (step S21).
3).

FIG. 4A shows an example in which the source code is converted into a 32-bit instruction code A, a 16-bit instruction code B, and a 16-bit instruction code C in this order. FIG. 4 is an explanatory diagram showing a storage state of each instruction code for big endian in a temporary storage buffer 5 and an output state to an object file.
FIG. 4B shows, as an example, a state of storing each instruction code in the temporary storage buffer 5 when the source code is converted into an instruction code B having a length of 16 bits and an instruction code A having a length of 32 bits in this order. FIG. 9 is an explanatory diagram showing a state of output to an object file.

When the processor operates in big endian, the processor executes the instruction code loaded from the object file onto the memory in the order of addresses 0, 4, and 6, as shown in FIGS. 4 (a) and 4 (b). ), The storage arrangement of each instruction code in the object file is converted so that it is arranged in the execution order of instruction codes in the case of big endian, so that the instruction order of the source file and the instruction execution order match. It will be.

Next, a description will be given of a processing procedure for generating an instruction code for little endian by the assembler 1 of the first embodiment. FIG. 3 is a flowchart illustrating a processing procedure for generating a little endian instruction code. The assembler 1 initializes the temporary storage buffer 5 (step S301), reads one line from the source file (step S302), analyzes the syntax (step S303), and performs code conversion, as in the case of the big endian instruction code generation processing. Perform (step S304). Then, the arrangement conversion unit 6 further performs the following arrangement conversion processing for generating an instruction code for little endian. First, the size of the converted instruction code is checked (step S3).
05). If the instruction code is 32 bits long,
Further, it is checked whether or not the instruction code of the previous conversion remains in the temporary storage buffer 5 (step S30).
6). If not, BUF [0], BUF [1], BUF [1], BUF [1]
[2] and BUF [3] are stored in this order (step S30).
9). Then, the instruction code stored in the temporary storage buffer 5 is output to the object file by the file output unit 7 (step S313). The output order and the arrangement for each byte are BUF [0], BUF [1], B
The data is output from the lower address (that is, LSB) of the object file in the order of UF [2] and BUF [3] in correspondence with little endian.

As a result of the code size check in step S305, if the converted instruction code is 16 bits long, it is checked whether or not the previously converted instruction code remains in the temporary storage buffer 5 (step S305). S310). If not, the upper 8 bits of the 16-bit instruction code are stored in the BUF of the temporary storage buffer 5.
The lower 8 bits are stored in BUF [2] in [3] (step S311).

Next, the next one line of source code is read from the source file in the file input section 2 (step S302), and the processing up to step S305 is similarly performed. If the instruction is a 16-bit instruction code, it is checked whether or not the instruction code of the previous conversion remains in the temporary storage buffer 5 (step S31).
0) In this case, the upper 8 bits of the newly converted instruction code are stored in BUF [1] and the lower 8 bits are stored in BUF [0] because they remain in BUF [3] and BUF [2]. (Step S312). Then, the file output unit 7
The BUF [0], BUF [1], BUF [2], BUF
In the order of F [3], output is performed from the lower address (that is, LSB) of the object file in correspondence with little endian (step S313).

In step S305, if the instruction code read and converted after the 16-bit instruction code is a 32-bit instruction code, whether the instruction code of the previous conversion remains in the temporary storage buffer 5 or not. It is checked whether or not it is not (step S306). In this case, BUF [3]
And BUF [2], so step S307
To BUF [1] and BUF in the temporary storage buffer 5
A 16-bit no-processing instruction (NOP) is additionally stored in [0]. Then, the instruction code stored in the temporary storage buffer 5 is converted by the file output unit 7 into BUF [0], B
Output in the order of UF [1], BUF [2], and BUF [3] from the lower address (ie, LSB) of the object file corresponding to little endian (step S).
308) Then, the next 32-bit instruction code is stored in the temporary storage buffer 5 (step S309) and output to the object file (step S31).
3).

FIG. 5A shows an example in which the source code is converted into a 32-bit instruction code A, a 16-bit instruction code B, and a 16-bit instruction code C in this order. FIG. 4 is an explanatory diagram showing a storage state of each little endian instruction code in a temporary storage buffer 5 and an output state to an object file.
FIG. 5B shows, as an example, the state of storing each instruction code in the temporary storage buffer 5 when the source code is converted into an instruction code B having a length of 16 bits and an instruction code A having a length of 32 bits in this order. FIG. 9 is an explanatory diagram showing a state of output to an object file.

Even when the processor operates in little endian, the processor can read the instruction code loaded from the object file into the memory at addresses 0, 4, 6
The addresses are executed in the order of the addresses. As can be seen from FIGS. 5A and 5B, the storage arrangement of each instruction code in the object file is converted so as to be arranged in the execution order of the instruction codes in the case of little endian. Therefore, the order of the instructions in the source file matches the order of execution of the instructions.

By performing assembler processing as described above, even if the same source file described in assembly language is used, an object file that executes the same processing in both endians can be generated in the processor. Performance can be improved.

Embodiment 2 The bi-endian-compatible assembler according to the first embodiment is configured such that if an instruction following a 16-bit instruction on a 32-bit boundary is a 16-bit instruction,
In the bi-endian assembler according to the second embodiment, the remaining half of 16 bits is always converted when converting a 16-bit instruction. NOP
Processing is simplified by using instructions.

FIG. 6 is a block diagram showing a structure of an assembler according to the second embodiment of the present invention. As shown in FIG. 6, the bi-endian compatible assembler according to the second embodiment includes a file input unit 2, a syntax analysis unit 3, a code conversion unit 4, a code conversion table 10, a temporary storage buffer 5, a layout conversion And a file output unit 7. Here, the file input unit 2, the syntax analysis unit 3,
The code conversion unit 4, the code conversion table 10, the temporary storage buffer 5, and the file output unit 7 are the same as those of the assembler of the first embodiment, and thus the description is omitted. When the 16-bit instruction code is stored in the temporary storage buffer 5, the arrangement conversion unit 66 adds the 16-bit instruction code and the NO
This is for converting the arrangement of P instructions.

Next, a description will be given of a processing procedure for generating an instruction code for big endian by the bi-endian-compatible assembler according to the second embodiment configured as described above. FIG. 7 is a flowchart illustrating a processing procedure for generating an instruction code for big endian.

The assembler 1 initializes the temporary storage buffer 5 (step S601), reads one line from the source file (step S602), and analyzes the syntax (step S603), similarly to the big endian instruction code generation processing of the first embodiment. ) And perform code conversion (step S60)
4). Then, the arrangement conversion section 66 further performs the following arrangement conversion processing for generating an instruction code for little endian. First, the size of the code-converted instruction code is checked (step S605).

When the instruction code has a 32-bit length, four bytes, one byte at a time, from the upper byte of the code-converted instruction code are stored in the temporary storage buffer 5 in the BUFF.
[0], BUF [1], BUF [2], and BUF [3] are stored in this order (step S606). Then, the instruction code stored in the temporary storage buffer 5 is converted by the file output unit 7 into BUF [0], BUF [1], BUF [1].
[2] and BUF [3] are output in order from the lower address (that is, MSB) of the object file in correspondence with big endian (step S610).

As a result of the code size check in step S605, if the converted instruction code has a 16-bit length, the upper 8 bits of the 16-bit instruction code are stored in BUF [0] of the temporary storage buffer 5, and the lower 8 bits. 8 bits are stored in BUF [1] (step S607). Then, BUF [2], BUF of the temporary storage buffer 5
A 16-bit no-processing instruction (NOP) is additionally stored in [3] (step S608). Further, "1" is set to the most significant bit of BUF [2] of the buffer storing the NOP instruction (step S609). The most significant bit of BUF [2] is used for parallel execution when determining whether or not to execute two read 16-bit instructions in parallel when the processor performing the operation in FIG. 13 executes the instruction code. It corresponds to a bit. By setting the most significant bit to “1”, the 16-bit instruction stored in BUF [0] and BUF [1], BUF [2] and BUF
The NOP instruction stored in [3] is executed in parallel by the processor.

The file output unit 7 converts the instruction code stored in the temporary storage buffer 5 into BUF [0], BUF
[1], BUF [2], and BUF [3] are output in order from the lower address (that is, MSB) of the object file in correspondence with big endian (step S6).
10).

Next, a description will be given of the procedure for generating an instruction code for little endian by a bi-endian compatible assembler. FIG. 8 is a flowchart illustrating a processing procedure for generating a little endian instruction code.

The assembler 1 stores the temporary storage buffer 5 in the same manner as the big endian instruction code generation processing described above.
Initialization (step S701), one line is read from the source file (step S702), and syntax analysis (step S701)
703), and code conversion is performed (step S704). Then, the arrangement conversion section 66 further performs the following arrangement conversion processing for generating an instruction code for little endian.

First, the size of the code-converted instruction code is checked (step S705). When the instruction code has a 32-bit length, four bytes, one byte at a time, from the lower byte of the code-converted instruction code are stored in the temporary storage buffer 5 in BUF [0], BUF [1], and BUF.
F [2] and BUF [3] are stored in this order (step S7).
06). Then, the BUF is output by the file output unit 7.
[0], BUF [1], BUF [2], and BUF [3] in this order, the instruction code stored in the temporary storage buffer 5 from the lower address (ie, LSB) of the object file corresponding to little endian. Output to an object file (step S710).

As a result of the code size check in step S705, if the code-converted instruction code has a 16-bit length, the upper 8 bits of the 16-bit instruction code are stored in BUF [3] of the temporary storage buffer 5, Store the lower 8 bits in BUF [2]. (Step S70
7). Then, BUF [1], B of the temporary storage buffer 5
A 16-bit no-processing instruction (NOP) is additionally stored in UF [0] (step S708). Further, "1" is set to the most significant bit of BUF [2] of the buffer storing the 16-bit instruction code (step S709). This B
The most significant bit of UF [2] corresponds to the parallel execution bit, as in the processing for big endian.
By setting the most significant bit to “1”, B
The 16-bit instruction stored in UF [3] and BUF [2] and the NOP instruction stored in BUF [1] and BUF [0] are executed in parallel by the processor.

Then, the instruction code stored in the temporary storage buffer 5 is converted by the file output unit 7 into a BUFF.
[0], BUF [1], BUF [2], and BUF [3] are output from the lower address (that is, LSB) of the object file in correspondence with little endian (step S710).

As described above, in the assembler according to the second embodiment, all the 16-bit instructions are arranged on the 32-bit boundary. The operation can be ignored, and when displaying the correspondence between the memory image and the mnemonic by disassembling, the coded procedure is output as it is, which is convenient for verification and improves software development efficiency. be able to. Also, since the bit corresponding to the parallel execution bit is set to “1”, the 16-bit instruction and the 16-bit NOP instruction can be executed in parallel.
An increase in the execution time of the processor due to the addition of the OP instruction can be reduced.

Embodiment 3 The bi-endian-compatible assemblers of the first and second embodiments have the advantage that the same source file can be used in the big-endian and little-endian operation modes. The inversion phenomenon of the address in unavoidable. Therefore, in the bi-endian assembler of the third embodiment, the mnemonics of compound instructions are defined for all combinations of 16-bit instructions, and the source file described by the compound instructions is converted into instruction codes to reverse the addresses. Is completely prevented.

FIG. 9 is a block diagram showing the structure of the assembler according to the third embodiment. Assembler 1 of Embodiment 3
As shown in FIG. 9, the file input unit 2, the syntax analysis unit 3, the code conversion unit 904, and the code conversion table 9
10 and a file output unit 7. Here, the file input unit 2, the syntax analysis unit 3, and the file output unit 7
Has the same configuration as that of the conventional assembler, and thus the description is omitted.

FIG. 10 is a block diagram showing a definition example of a compound instruction used in the assembler according to the third embodiment.
A “composite instruction” is an instruction that combines two 16-bit instructions. In FIG. 10, the blocks in the left column and the center column are mnemonics 8 of the existing 16-bit instructions, and the blocks in the right column are mnemonics representing the processing content of two instructions by combining two existing 16-bit instructions. Notation 9 As shown in FIG. 10, the mnemonic notation 9 of the compound instruction is defined for all combinations of two 16-bit length instructions.

The assembler according to the third embodiment generates an instruction code (machine language) from a source file described with such a composite instruction. Therefore, the code conversion unit 904 reads the composite code read from the source file. The instruction is converted to an instruction code (machine language) of a corresponding composite instruction with reference to the code conversion table 910. The code conversion table 910 associates the mnemonic notation 9 of the compound instruction shown in the definition example of FIG. 10 with the instruction code of the compound instruction in the format shown in FIG. 14 described above.

FIG. 11 is a flowchart showing an assembler processing procedure by the assembler according to the third embodiment. As shown in FIG. 11, in the assembler according to the third embodiment, first, a buffer is initialized (step S1101). Then, one line of the compound instruction is read from the source file described by the compound instruction by the file input unit 2 (step S1102), and the read compound instruction is analyzed by the syntax analysis unit 3 (step S1103). Next, the code conversion unit 904 converts the mnemonic of the compound instruction into a 32-bit instruction code (machine language) with reference to the code conversion table 910 (step S1104), and stores the converted machine language in a buffer. (Step S110
5). The machine language stored in the buffer is generated into an object file by the file output unit 7 in accordance with the endian (Step S1106). The processing from step S1102 to step S1106 is repeatedly performed for the composite instructions of all the lines described in the source file.

As described above, in the assembler according to the third embodiment, a compound instruction as shown in FIG. 10 is defined, and code conversion is performed using the code conversion table 910 for associating the mnemonic notation of the compound instruction with the instruction code. Part 904
, The generated instruction codes are all 32 bits long. For this reason, the reverse execution of the instruction in the little endian operation of the processor can be reliably eliminated, and the code amount of the generated instruction code can be optimized.

[0065]

As described above, according to the present invention, the same processing is executed using the same source file of the assembly language description regardless of whether the processor operates in either big endian or little endian. It is possible to generate an object file, and it is possible to improve the productivity of software.

According to the next invention, all the 16-bit instructions are arranged on the 32-bit boundary, and it is possible to ignore the fact that the 16-bit instructions have an execution operation backward to the address during little endian operation. It has the effect of being able to. Further, when the correspondence between the memory image and the mnemonic is displayed in the disassembly, the coded procedure is output as it is, so that there is an effect that the verification is convenient and the efficiency of software development can be improved.

According to the next invention, the reverse execution of the instruction during the little endian operation of the processor can be reliably eliminated, and the effects of optimizing the code amount can be achieved.

According to the next invention, even when the processor operates in either big endian or little endian, it is possible to generate an object file that executes the same processing by using the same source file of the assembly language description. It is possible to improve the productivity of software.

According to the next invention, all the 16-bit instructions are arranged on the 32-bit boundary, and it is possible to ignore the fact that the 16-bit instructions have an execution operation backward to the address during little endian operation. It has the effect of being able to. Further, when the correspondence between the memory image and the mnemonic is displayed in the disassembly, the coded procedure is output as it is, so that there is an effect that the verification is convenient and the efficiency of software development can be improved.

According to the next invention, there is an effect that the reverse execution of the instruction during the little endian operation of the processor can be reliably eliminated, and the amount of code can be optimized.

According to the next invention, there is an effect that any one of the above-mentioned inventions can be executed by a computer.

[Brief description of the drawings]

FIG. 1 is a view illustrating a first embodiment and a second embodiment of the present invention;
FIG. 2 is a block diagram illustrating a configuration of an assembler.

FIG. 2 is a flowchart illustrating a procedure of a big-endian instruction code generation process performed by the assembler according to the first embodiment illustrated in FIG. 1;

FIG. 3 is a flowchart showing a little-endian instruction code generation processing procedure by the assembler of the first embodiment shown in FIG. 1;

FIG. 4 (a) shows a 32-bit instruction code A, a 16-bit instruction code B, and a 16-bit instruction code A when the big-endian instruction code is generated in the assembler of the first embodiment shown in FIG. FIG. 7 is an explanatory diagram showing a state of storing a bit-length instruction code C in a temporary storage buffer and a state of output to an object file. FIG. 4 (b)
In the assembler according to the first embodiment shown in FIG. 1, when the big endian instruction code is generated, the 16-bit instruction code B and the 32-bit instruction code A are stored in the temporary storage buffer, and are stored in the object file. FIG. 4 is an explanatory diagram showing an output state.

FIG. 5 (a) shows a 32-bit instruction code A, a 16-bit instruction code B, and a 16-bit instruction code A in generating the little endian instruction code in the assembler of the first embodiment shown in FIG. FIG. 7 is an explanatory diagram showing a state of storing a bit-length instruction code C in a temporary storage buffer and a state of output to an object file. FIG. 5 (b)
In the assembler according to the first embodiment shown in FIG. 1, when the little endian instruction code is generated, the 16-bit instruction code B and the 32-bit instruction code A are stored in the temporary storage buffer, and the FIG. 4 is an explanatory diagram showing an output state.

FIG. 6 is a block diagram showing a configuration of an assembler according to a second embodiment of the present invention.

7 is a flowchart illustrating a procedure of a big-endian instruction code generation process performed by the assembler illustrated in FIG. 6;

FIG. 8 is a flowchart showing a little-endian instruction code generation processing procedure by the assembler of the second embodiment shown in FIG. 6;

FIG. 9 is a block diagram showing a configuration of an assembler according to a third embodiment of the present invention.

FIG. 10 is a block diagram showing a definition example of a compound instruction used in the assembler of the third embodiment shown in FIG. 9;

FIG. 11 is a flowchart of an assembler processing procedure by the assembler according to the third embodiment shown in FIG. 9;

FIG. 12 is a diagram showing types of instructions of a processor to which the assembler shown in FIGS. 1, 6, and 9 is applied;

FIG. 13 is a flowchart showing an instruction execution procedure of a processor to which the assembler shown in FIGS. 1, 6, and 9 is applied;

FIG. 14 is an explanatory diagram of a code conversion table referred to by a code conversion unit of the assembler shown in FIGS. 1 and 6;

FIG. 15 is a diagram showing a memory arrangement of a hexadecimal code converted into a machine language.

FIG. 16 is an explanatory diagram showing a memory arrangement of a machine language in big endian.

FIG. 17 is an explanatory diagram showing a memory arrangement of a machine language in little endian.

FIG. 18 is a block diagram illustrating a configuration of a conventional assembler.

FIG. 19 is a flowchart of an assembler processing procedure in a conventional assembler.

[Explanation of symbols]

1 assembler, 2 file input section, 3 syntax analysis section, 4 code conversion section, 5 temporary storage buffer, 6 layout conversion section, 7 file output section, 8 mnemonic notation, 9 mnemonic notation of compound instruction, 10 code conversion table, 11 Assembler, 12 file input section,
13 syntax analyzer, 14 code converter, 17 file output unit, 18 mnemonic, 19 machine language, 20
Mnemonics, 21 machine language (instruction code), 22 addresses, 23 instruction code arrangement (big endian), 24 instruction code arrangement (little endian), 66 arrangement conversion unit, 904 code conversion unit, 910
Code conversion table.

Claims (7)

[Claims] An assembler that has an instruction set consisting of a 16-bit instruction and a 32-bit instruction and generates an instruction code corresponding to a processor in which the execution order of two 16-bit instruction codes is switched when operating in different endians. A storage device for temporarily storing a 16-bit instruction code code-converted from a source file; two 16-bit instruction codes arranged on a 32-bit boundary in the storage device;
An arrangement conversion means for exchanging bit-length instruction codes in accordance with an endian to be operated, and a file output means for outputting the two exchanged 16-bit instruction codes to an object file. Assembler processing unit. 2. The arrangement conversion means according to claim 1, wherein when a 16-bit instruction code is stored in said storage means, a 16-bit NOP instruction code is further added to said storage means. The assembler processing device according to claim 1. 3. An assembler having an instruction set consisting of a 16-bit instruction and a 32-bit instruction and generating an instruction code corresponding to a processor in which the execution order of two 16-bit instruction codes is switched when operating in different endians. A code conversion table in which a mnemonic of a compound instruction defined by combining two 16-bit instructions as one 32-bit length instruction and an instruction code of the compound instruction are read from a source file. Code conversion means for converting the compound instruction into an instruction code corresponding to the compound instruction with reference to the code conversion table. 4. An assembler having an instruction set including a 16-bit instruction and a 32-bit instruction and generating an instruction code corresponding to a processor in which the execution order of two 16-bit instruction codes is switched when operating in different endians. In the processing method, a storage step of temporarily storing a 16-bit instruction code code-converted from a source file in a storage means;
An assembler characterized by comprising: an arrangement conversion step of exchanging bit-length instruction codes according to an endian of an operation target; and a file output step of outputting the exchanged two 16-bit instruction codes to an object file. Processing method. 5. The arrangement conversion step further comprises the step of: when a 16-bit instruction code is stored in the storage means,
5. The assembler processing method according to claim 4, wherein a 6-bit NOP instruction code is added to said storage means. 6. An assembler that has an instruction set including a 16-bit instruction and a 32-bit instruction and generates an instruction code corresponding to a processor in which the execution order of two 16-bit instruction codes is switched when operating in different endian. In the processing method, a source file is referred to by referring to a code conversion table that associates a mnemonic of a compound instruction defined as one 32-bit instruction with a combination of two 16-bit instructions and an instruction code of the compound instruction. A code conversion step of converting the compound instruction read out of the program into an instruction code corresponding to the compound instruction. 7. A program for causing a computer to execute the assembler processing method according to claim 4.