JP2002344306A - Logic gate based on single flux quantum theory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a logic gate capable of high speed operation with a small number of logic stages and employing single flux quanta as basic elements used for information carriers. SOLUTION: The logic gate comprises an input confluent circuit for gathering input single flux quanta inputted from input terminals into a single signal line, a clock branching circuit for generating inner clock signal flux quanta synchronous with an inputted external clock signal and initialized single flux quanta held on a superconductor loop in the gate, and an output circuit for detecting the existence of the initialized single flux quantum in the superconductor loop to output the detection result on an output terminal upon the input of the input single flux quantum, the inner clock single flux quantum and the initialized signal flux quantum. In the clock branching circuit, the initialized signal flux quantum is sent to the output circuit with an adequate time delay after the inner clock single flux quantum is sent to the output circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a single flux quantum (SFQ) using a flux quantum as an information carrier.
m) The basic gate of superconducting integrated circuits based on
Specifically, the present invention relates to a logic gate characterized by high-speed operation.

[0002]

2. Description of the Related Art In general, it is well known that any logical function can be realized by providing a NOT gate and an OR gate or a NOT gate and an AND gate in a logic circuit. If a NOR gate or a NAND gate having the characteristics of these two types of gates can be formed, any logical function can be realized by one type of logic gate.

In addition, single flux quantum (SFQ: Single Flux)
The OR gate and the NOT gate based on the (Quantum) theory are described in IEEE Trans. Appl. Supercond. Vol. 1, 1991, pp. 3 to 28, and the like. By combining these, it is possible to form a NOR gate. However, the number of logical stages of the configured NOR gate is two stages of the OR gate and the NOT gate.
In order to operate this NOR gate, two clocks are required as an external clock. The logical sum operation is performed at the first clock, and the negative operation is performed at the next clock.

[0004]

The NOR gate constructed using the prior art requires two logic stages for the operation.
Originally, in a single flux quantum logic circuit devised to realize a high-speed logic operation, it is desirable that all logic gates have one logic stage.

SUMMARY OF THE INVENTION An object of the present invention is to provide a logic gate based on a single magnetic flux quantum theory that can perform arithmetic processing with one logic stage in order to realize a higher-speed operation.

[0006]

According to the present invention, there is provided an input single flux quantum having one or more input terminals and corresponding to an input single flux quantum. And an input merging circuit that combines the input single flux quantum of each input terminal into one signal line, and an internal clock single flux quantum that has an external clock terminal and is synchronized with the input external clock single flux quantum A clock branching circuit for generating an initial single flux quantum to be held by a superconducting loop in a gate, and inputting the input single flux quantum, an internal clock single flux quantum, and an initial single flux quantum; It consists of an output circuit that detects the presence or absence of the default single flux quantum in the loop and outputs the result to the output terminal. In the clock branch circuit, the timing at which the default single flux quantum is sent to the superconducting loop is determined. After the internal clock single flux quantum is sent to the output circuit, it is set to be sent to the superconducting loop with an appropriate time delay, and the retained initial single flux quantum in the superconducting loop is , Are driven out by the input single flux quanta, and the conditions to be driven out are determined by the number of input single flux quanta, and in the output circuit, when the internal clock single flux quanta is input, superconductivity Only when there is an initial setting single flux quantum in the loop, the flux quantum is set to be output to the output terminal.

Further, the number of input terminals of the input merging circuit is two or more, and the number of input single flux quanta necessary to drive out the initially set single flux quantum in the superconducting loop is set to one or more. Thus, a multi-input NOR operation is performed. In addition, the number of input terminals of the input merging circuit is one, and the number of input single flux quanta required to drive out the single flux quantum initially set in the superconducting loop to the outside is set to one, so that a negative operation is performed. I do.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. (Embodiment 1) FIG. 1 shows a two-input NOR gate according to a first embodiment of the present invention. The two-input NOR gate has two input terminals A and B, an external clock terminal CLK, and an output terminal OUT.
It comprises a clock branching circuit 5 and an output circuit 4 for detecting the presence or absence of a single magnetic flux quantum held in a superconducting loop provided in the gate and outputting the single magnetic flux quantum to an output terminal.

The input merging circuit 6 has an input buffer circuit 1-
A, 1-B and inductor _LAB are included. The input buffer circuits 1-A and 1-B are supplied with current from a common current source Ib _AB and generate an input single flux quantum corresponding to an input signal.
The currents associated with the input single flux quanta corresponding to the inputs A and B are combined by the common inductor L _AB to form the output circuit 4 J
1. Flow to J2.

The clock branching circuit 5 comprises an internal clock single flux quantum generating circuit 2, an initial setting buffer circuit 3, inductors L _clk2 and L _Tin . An internal clock single flux quantum generation circuit 2 generates an internal clock single flux quantum based on an external clock signal input from an external clock terminal CLK. The internal clock single flux quantum is branched by the inductors L _clk2 and L _Tin , and the single flux quantum passing through the inductor L _clk2 is sent to the output circuit 4 as the internal clock single flux quantum. Further, the single flux quantum that has passed through the inductor L _Tin is sent to the initial setting buffer circuit 3. Initialization Initialization single flux quantum is generated in the buffer circuit 3, it is held in the superconducting loop containing inductor L _T. At this time, the timing at which the initially set single flux quantum is sent to the superconducting loop is set so that the internal clock single flux quantum is sent to the superconducting loop with an appropriate time delay after being sent to the output circuit. You.

The output circuit 6 comprises three Josephson junctions J1, J
It consists of 2, J3. The output circuit 6 detects the presence / absence of a single magnetic flux quantum held in a superconducting loop installed in the gate, and outputs the magnetic flux quantum to an output terminal. The output circuit 6 via the inductor L _out, is connected to the output terminal OUT.

In this embodiment, three superconducting loops: loop _{T
(J T1, J T2, L} T, J1, J2), loop A (J A 1, J A2, L AB, J1, J
_{2), loop B (J B1} , J B2, L AB, J1, J2) are formed.
Each superconducting loop contains a Josephson junction and is designed to change its internal state by an input single flux quantum. By the internal clock single flux quantum, the initially set single flux quantum is held in the superconducting loop loop _T (set state). The initial single flux quantum in the superconducting loop loop _T is driven out through J1 by the input single flux quantum sent from the input merging circuit (reset state). For a two-input NOR gate, the default single flux quantum is released when one or more input single flux quantums are sent. When the internal clock single flux quantum is input to the output circuit 4, the single flux quantum is output to the output terminal OUT only when there is an initial setting single flux quantum in the superconducting loop loop _T.

Next, the operation of the two-input NOR gate of this embodiment will be described. (a) Initial setting, (b) When both inputs A and B are not present, (c) When there is only input A, When there is only (d) B, (e) When both inputs A and B are present, Will be described in this order.

(A) Initial setting To create an initial state, an external clock signal is input.
Internal clock generation circuit 2
Generates an internal clock single flux quantum. The internal clock single flux quantum is sent to the initialization buffer circuit 3. The initial setting single flux quantum is generated with an appropriate time delay in the initial setting buffer circuit 3, and the superconducting loop loop is generated.
_T holds one magnetic flux quantum (set state). (b) When neither input A nor B is present When there is no input signal for both input A and input B, the state is the initial setting, that is, a state where a circulating current of one flux quantum flows through the superconducting loop loop _T ( (Set state) is maintained.
In this state, when an external clock signal is input, an internal clock single flux quantum is generated and input to the output circuit 4 through the Josephson junction J3. Then, the Josephson junction J2 is switched by the input of the internal clock single flux quantum. The flux quantum is output to the output terminal OUT via the inductor L _out by the switch of the Josephson junction J2. At this time, the critical current values Ic _J1 and Jc of the Josephson junctions J1, J2, and J3 are set so that the Josephson junction J3 switches by adding the circulating current of the superconducting loop loop _{T and} the current pulse due to the internal clock single flux quantum. The inductances of Ic _J2 , Ic _J3 , inductors L _clk2 , and L _AB are designed in _advance .
Also, Ic _J2 and Ic _J3 are designed so that Ic _J2 > Ic _J3 so that the Josephson junction J3 does not switch first. Thereafter, the initial setting single flux quantum is generated with a delay from the input of the internal clock single flux quantum to the output circuit 4.
At that time, the state returns to the state in which a circulating current of one flux quantum flows in the superconducting loop loop _T (set state).

(C) When there is only an input A An input signal is input from the input terminal A in the set state.
And input single flux quantum is generated by input buffer circuit 1-A
And the inductor L_ABAnd the flux quantum component
The circulating current is added to the current flowing through Josephson junction J1.
You. Superconducting loop loop _TAlready has one round of flux quantum
Electric current is flowing. For the current increase due to the input single flux quantum
Thus, the Josephson junction J1 switches. And
Superconducting loop loop by Josephson junction J1 switch
_TThe initial single flux quantum held in
And the circulating current disappears (reset state). At this time,
Superconducting loop loop_TCurrent and the input single flux quantum
Josephson junction J1
As can be seen, the critical currents of Josephson junctions
Flow value Ic_J1,I c_J2,I c_J3, Inductor L_clk2, L_ABInn
Design the conductance and so on.

In this state, when an external clock signal is input, the internal clock single flux quantum is converted into a Josephson junction.
Input to output circuit 4 from J3. Josephson junction J2, J
Because the critical current values Ic _J2 and Ic _{J3 of 3} are Ic _J2 > Ic _J3 , even if there is an input of an internal clock single flux quantum, the Josephson junction J2 does not switch but the Josephson junction J3 switches . Because Josephson junction J3 switches first,
No single flux quantum is output to the output terminal OUT. At this time, the inductances of the critical current values Ic _J1 , L _T , and L _AB are supplied to the Josephson junction J1 so that only the circulating current necessary to hold one flux quantum in the superconducting loop loop _T flows. Etc. are designed. Thereafter, the initial setting single flux quantum is generated with a delay from the input of the internal clock single flux quantum to the output circuit 4. At this time, the state returns to the state in which a circulating current of one flux quantum flows in the superconducting loop loop _T (set state).

(D) When there is only the input B In this case, the output terminal OUT
Does not output a single flux quantum.

(E) When both inputs A and B are present When the input signal is inputted from the input terminal A in the set state, the superconducting loop 1
The flux quantum held in oop _T is released to the outside, and the circulating current disappears (reset state).

Furthermore, the input signal from the input terminal B is input, the input single flux quantum in the input buffer circuit 1-B is generated, through the inductor L _AB, Josephson junctions J1
Sent to By the input of the input single flux quantum, the Josephson junction J1 switches, and the single flux quantum is not held in the superconducting loop loop _T (reset state). At this time,
In the Josephson junction J1, the circulating current required to hold one flux quantum in the superconducting loop loop _T flows, but the flux quantum 1 flows in the superconducting loops loop _A and loop _B.
The critical current value Ic _J1 , the inductance of the inductor L _AB , and the like are designed so that the circulating current necessary to maintain the current does not flow.

In this state, when an external clock signal is input, the internal clock single flux quantum becomes a Josephson junction.
Input to output circuit 4 from J3. Josephson junction J2, J
Since the critical current values Ic _J2 and Ic _{J3 of 3} are Ic _J2 > Ic _J3 , even if there is an input of an internal clock single flux quantum, the Josephson junction J2 does not switch but the Josephson junction J3 switches . Because Josephson junction J3 switches first,
No single flux quantum is output to the output terminal OUT.

Thereafter, the initial setting single flux quantum is generated with a delay from the input of the internal clock single flux quantum to the output circuit 4. At this time, the state returns to the state in which a circulating current of one flux quantum flows in the superconducting loop loop _T (set state).

Table 1 shows a truth table of the two-input NOR gate in this embodiment. Table 2 shows an example of element parameters for forming a NOR gate designed to perform the above operation. FIG. 2 shows a simulation result of a two-input NOR gate having the parameters shown in Table 2. Fig. 2 shows the voltage at point P _clk , the points P _{A ,,}
P _B , T voltage, output terminal OUT voltage, Josephson junction J1
Shows the current value I _J1 flowing through. As described above, the flux quantum is output from the output terminal only when there is no input to both the A and B input terminals, so that a two-input NOR gate is configured. In this embodiment, since a logical operation can be performed by one external clock signal, the present embodiment is a logical gate of one logical stage. Therefore, a faster two-input NOR operation can be performed. In this embodiment, the two-input NOR gate is shown. However, the number of input terminals constituting the input merging circuit, and the number of input terminals necessary to release the initially set single flux quantum in the superconducting loop are set. Just by changing the setting of the flux quantum number,
Various logic gate configurations are possible.

[0023]

[Table 1]

[0024]

[Table 2]

(Embodiment 2) FIG. 3 shows a three-input NOR gate according to a second embodiment of the present invention. The three-input NOR gate has three input terminals A, B, and C, an external clock terminal CLK, and an output terminal OUT, and has an input merging circuit 6, a clock branching circuit 5, and a gate inside the input terminals A, B, and C. To detect the presence or absence of magnetic flux quanta in the superconducting loop
An output circuit 4 outputs a magnetic flux quantum to an output terminal.

The configuration of this embodiment is the same as that of the two-input NOR gate shown in the first embodiment except for the number of input terminals and input buffer circuits. 3 For input NOR gates, with one or more input single flux quantum, superconducting loop _{loop T (J T1, J T2} , L T, J1, J2) to be retained initial set SFQ as the release (reset state), designing a critical current value Ic _J1 etc. J1.

Table 3 shows a truth table of the three-input NOR gate in this embodiment. As described above, the flux quantum is output from the output terminal only when there is no input to all of the input terminals A, B, and C, so that a three-input NOR gate is configured. In this embodiment, since a logical operation can be performed by one external clock signal, the present embodiment is a logical gate of one logical stage.
Therefore, a faster three-input NOR operation can be performed.

[0028]

[Table 3]

(Embodiment 3) FIG. 4 shows a NOT gate according to a third embodiment of the present invention. Negation gate is one input terminal
A, an external clock terminal CLK, and an output terminal OUT,
Input junction circuit 6 following input terminal A 6, Clock branch circuit 5, Output circuit that detects the presence or absence of a single flux quantum held in a superconducting loop installed in the gate, and outputs a single flux quantum to the output terminal 4 The configuration of this embodiment is
Except for the number of input terminals and input buffer circuits,
The configuration is the same as that of the NOR gate shown in the embodiment and the second embodiment. If not the gate is a single input single flux quantum, superconducting loop _{loop T (J T1, J T2} , L T, J1, J2) initialized held to release the single flux quantum (the reset state As described above, the critical current value Ic _{J1 of J1} is designed.

Table 4 shows a truth table of the NOT gate in this embodiment. As described above, when there is no input at the input terminal, the flux quantum is output from the output terminal, so that a negative gate is configured. In this embodiment, since a logical operation can be performed by one external clock signal, the present embodiment is a logical gate of one logical stage. Therefore, a faster negation operation can be performed.

[0031]

[Table 4]

[0032]

The present invention is embodied in the form described above and has the following effects. One or
An input merging circuit having a plurality of input terminals, generating an input single flux quantum corresponding to the input single flux quantum, and collecting the input single flux quantum input from each input terminal into one signal line; A clock splitter circuit having an external clock terminal and generating an internal clock single flux quantum synchronized with an input external clock signal and an initial setting single flux quantum held by a superconducting loop in a gate; It consists of an output circuit that inputs a flux quantum, an internal clock, a single flux quantum, and a default single flux quantum, detects the presence or absence of a default single flux quantum in the superconducting loop, and outputs the result to an output terminal. However, in the clock branch circuit, the timing at which the initially set single flux quantum is sent to the output circuit is delayed by an appropriate time after the internal clock single flux quantum is sent to the output circuit. Set to be sent to the flop, and
In the superconducting loop, the initial single flux quantum inside is driven out by the input single flux quantum, and the conditions for the ejection are determined by the number of input single flux quanta, and in the output circuit: When the internal clock single flux quantum is input, only when there is no single flux quantum initially set in the superconducting loop, the flux quantum is output to the output terminal so that the number of logical stages is calculated in one step It is possible to realize a logic gate based on a single magnetic flux quantum that enables high-speed operation. Further, the present invention can be applied to various types of input terminals by simply changing the input terminals constituting the input merging circuit and the setting of the number of input magnetic fluxes necessary for releasing the initial setting single magnetic flux quantum held in the superconducting loop. A configuration of a high-speed logic gate is possible.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a two-input NOR gate showing a first embodiment of the present invention;

FIG. 2 is an explanatory diagram of the operation of the NOR gate of the first embodiment;

FIG. 3 is a circuit diagram showing a three-input NOR gate according to a second embodiment of the present invention;

FIG. 4 is a circuit diagram showing a NOT gate according to a third embodiment of the present invention.

[Explanation of symbols]

L _clk , J _T1 , J _T2 , J _A1 , J _A2 , J _B1 , J _B2 , J _C1 , J _C2 , J1,
J2, J3 Josephson junctions L _clk1 , L _clk2 , L _Tin , L _T , L _Ain , L _Bin , L _Cin , L _AB , L
_ABC, L _out inductor _{Ib clk, Ib A, Ib B} , Ib C bias terminal CLK, A, B, C input signal terminal Out output signal terminal _{P Clk, T, P A,} P B, P C voltage signal reading point 1 -A, 1-B Input buffer circuit 2 Internal clock generation circuit 3 Initial setting buffer circuit 4 Output circuit 5 Clock branch circuit 6 Input merging circuit

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Satoshi Nakayama 1-8-8 Nakase, Mihama-ku, Chiba City, Chiba Prefecture Inside Seiko Instruments Inc. 103 (72) Inventor Hiroaki Meiren 923-30 Shimookubo, Urawa-shi, Saitama 501F Nitta No.6 Nakajima Heights F-term (reference) 4M113 AA42 AD14 AD24 AD26 5J042 AA01 BA01 CA00 CA25 CA28 DA00 DA03

Claims (3)

[Claims] A logic gate based on a single flux quantum theory using a flux quantum as an information carrier, the logic gate having one or a plurality of input terminals and having an input single flux corresponding to the input single flux quantum An input merging circuit that generates quanta and combines the input single flux quantum of each input terminal into one signal line, and an internal clock single flux that has an external clock terminal and is synchronized with the input external clock single flux quantum A clock branching circuit for generating an initial single flux quantum to be held by a quantum and a superconducting loop in a gate; and inputting the input single flux quantum, the internal clock single flux quantum, and the default single flux quantum. And an output circuit for detecting the presence or absence of an initially set single flux quantum in the superconducting loop and outputting the result to an output terminal. The timing at which the element is sent to the superconducting loop is set to be sent to the superconducting loop with an appropriate time delay after the internal clock single flux quantum is sent to the output circuit; The default single flux quantum held in a conduction loop is driven out by the input single flux quantum, and the conditions for driving are determined by the number of input single flux quanta, and the output In the circuit, it is set that when the internal clock single flux quantum is input, the flux quantum is set to be output to the output terminal only when the initial setting single flux quantum exists in the superconducting loop. Logic gate based on single flux quantum logic. 2. The logic gate based on the single flux quantum theory according to claim 1, wherein the number of input terminals of the input merging circuit is two or more, and the initial setting single flux quantum in the superconducting loop is used. A logic gate based on single flux quantum theory that performs multi-input NOR operation by setting the number of input single flux quantums required to drive out to one. 3. The logic gate based on the single flux quantum theory according to claim 1, wherein the number of input terminals of the input converging circuit is one and the initial setting single flux quantum in the superconducting loop is outside. Input single flux quantum number required to drive
A logic gate based on single flux quantum theory that performs a negation operation when set to one.