JP2002344292A - Schmidt circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a through current flowing between a power supply voltage and a reference voltage, when an input voltage is in the vicinity of a threshold voltage. SOLUTION: Since a PMOS transistor 13 is in an interrupted state, when an input signal transits from a reference voltage level to a power supply voltage level, a through-current does not flow through a PMOS transistor 11. Since an NMOS transistor 14 is in interrupted state, when the input signal transits from the power supply voltage level to the reference voltage level, a through- current will not flow through an NMOS transistor 12. Consequently, the through- current is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Schmitt circuit having a hysteresis characteristic, and more particularly to a technique for suppressing power consumption that occurs when the transition of an input signal is gradual.

[0002]

2. Description of the Related Art For example, it is important to extend the operable time by reducing the power consumption of a portable electric device or the like powered by a battery or the like. Therefore, CMOS (complementary MOS) technology that can easily reduce power consumption is often used for semiconductor devices.

In order to prevent chattering and noise, Schmitt circuits having hysteresis characteristics (also referred to as "hysteresis circuits" and "Schmitt trigger circuits") are often used in input circuits and the like of semiconductor devices.

FIG. 4 is a logic diagram showing a configuration of a conventional Schmitt circuit. In this figure, in these figures,
110, 120 and 130 are all CMOS inverters. FIG. 5 is a circuit diagram for more specifically explaining the operation of the Schmitt circuit shown in FIG. As shown in FIG. 5, the CMOS inverter 110 includes a PMOS transistor 111 and an NMOS transistor 112, and the CMOS inverter 120 includes a PMOS transistor 121 and an NMOS transistor 122.

[0005] First, in FIG.
10 input signals, that is, input voltages, are at reference voltage levels (L
(Level) will be described. When the input voltage of the CMOS inverter 110 is at the reference voltage level, the PMOS transistor 111 is conducting and the NMOS transistor 112 is off, so that the output level of the CMOS inverter 110, ie, CM
The input level of the OS inverter 130 is at the H level. Therefore, the output level of the CMOS inverter 130, that is, the output signal of this Schmitt circuit becomes L level. Thereby, the PMOS of the CMOS inverter 120
The transistor 121 is turned on, and the NMOS transistor 122 is turned off. In this state, no through current flows from the power supply voltage to the reference voltage.

Next, the case where the input signal of CMOS inverter 110 rises from the reference voltage level to the power supply voltage level (that is, the input signal transitions from L level to H level) will be described. As the input voltage of the CMOS inverter 110 gradually increases from the reference voltage level, the conduction resistance of the PMOS transistor 111 gradually increases, and the conduction resistance of the NMOS transistor 112 gradually decreases.

At this time, as can be seen from FIG.
The input voltage of the inverter 130 is determined by the combined resistance value of the PMOS transistor 111 and the PMOS transistor 121,
NMOS transistor 112 and NMOS transistor 1
22 is a voltage level obtained by dividing the voltage between the power supply voltage and the reference voltage. In addition, the CMOS inverter 130
Until the input voltage of the CMOS inverter 130 falls below the threshold voltage of the CMOS inverter 130, since the output level of the CMOS inverter 130 is at the L level, the PMOS transistor 121 is kept conductive and the NMOS transistor 122 is kept off. Therefore, the PMOS transistor 11
1 gradually increases and the NMOS transistor 1
As the conduction resistance of the transistor 12 gradually decreases, the input level of the CMOS inverter 30 gradually decreases from the power supply voltage level.

When the PMOS transistor 121 is on and the NMOS transistor 122 is off, the input voltage of the CMOS inverter 130 becomes CM.
In order to fall below the threshold voltage of the OS inverter 130, the input voltage of the CMOS inverter 110 must be higher than the threshold voltage of the CMOS inverter 110 alone. That is, in this state, the input voltage of the CMOS inverter 130 is
The input voltage of the CMOS inverter 110 for lowering the threshold voltage to the threshold voltage of the inverter 130 becomes the threshold voltage on the high-level side of the hysteresis characteristic of this Schmitt circuit.

When the input voltage of the CMOS inverter 110 exceeds the high-level threshold voltage of the Schmitt circuit and goes to the H level, the PMOS transistor 111 is turned off and the NMOS transistor 112 is turned on. , Ie, the input level of the CMOS inverter 130 is at the L level. Therefore, the output level of the CMOS inverter 130 becomes H level, the PMOS transistor 121 of the CMOS inverter 120 is turned off, and the NMOS transistor 122 is turned on. In this state, no current flows from the power supply voltage to the reference voltage.

Next, the case where the input voltage of CMOS inverter 110 falls from the power supply voltage level to the reference voltage level (that is, the input signal transitions from H level to L level) will be described. As the input voltage of the CMOS inverter 110 gradually decreases from the power supply voltage level, the conduction resistance of the PMOS transistor 111 gradually decreases and the conduction resistance of the NMOS transistor 112 gradually increases.

As described above, the CMOS inverter 13
0 is applied to the PMOS transistor 111 and the PMO
This is a voltage level obtained by dividing the voltage between the power supply voltage and the reference voltage by the combined resistance value of the S transistor 121 and the combined resistance value of the NMOS transistor 112 and the NMOS transistor 122. When the input voltage of the CMOS inverter 130 is C
Until the threshold voltage of the MOS inverter 130 is exceeded, the output level of the CMOS inverter 130 is at the H level, so that the PMOS transistor 121 is kept off and the NMOS transistor 122 is kept on. Therefore, the conduction resistance of the PMOS transistor 111 gradually decreases, and the conduction resistance of the NMOS transistor 112 gradually increases and decreases.
Input voltage gradually rises from the power supply voltage level.

When the PMOS transistor 121 is turned off and the NMOS transistor 122 is turned on, the input voltage of the CMOS inverter 130 becomes CMOS.
In order to exceed the threshold voltage of the inverter 130, the input voltage of the CMOS
It must be lower than the threshold voltage of the S inverter 110 alone. In other words, in this state,
C for raising the input voltage of the CMOS inverter 130 to the threshold voltage of the CMOS inverter 130
The input voltage of the MOS inverter 110 becomes a low-level threshold voltage of the hysteresis characteristic of the Schmitt circuit.

From the above, it is apparent that the threshold voltage on the high level side is clearly higher than the threshold voltage on the low level side. Therefore, the hysteresis characteristic of the Schmitt circuit is obtained.

[0014]

As can be seen from the above description, in the conventional Schmitt circuit, for example, when the input signal is gradually increased from the L level to the H level, the conduction resistance of the PMOS transistor 111 is accordingly reduced. The NMOS transistor 11
2, the conduction resistance gradually decreases. In the meantime, PMOS
The transistor 121 is on. Accordingly, at this time, a current path between the power supply voltage and the reference voltage via the PMOS transistor 111 and the NMOS transistor 112 and the current path between the PMOS transistor 121 and the NMOS
In a current path via the transistor 112, a through current flows.

Conversely, when the input signal is gradually increased from the H level to the L level, the conduction resistance of the PMOS transistor 111 gradually decreases and the conduction resistance of the NMOS transistor 112 gradually increases. Meanwhile,
NMOS transistor 122 is conductive. Therefore, at this time, the current path between the power supply voltage and the reference voltage via the PMOS transistor 111 and the NMOS transistor 112,
In the current path through the MOS transistor 122,
A through current flows.

These through currents increase when the input voltage is near the threshold voltage. Therefore, especially when the input voltage transitions gently near the threshold voltage, the power consumption of the circuit increases, and the low power consumption characteristic which is a characteristic of the CMOS circuit is deteriorated.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and has a simple structure capable of reducing power consumption due to a through current flowing between a power supply voltage and a reference voltage when an input voltage is near a threshold voltage. An object of the present invention is to provide a Schmitt circuit having a circuit configuration.

[0018]

According to a first aspect of the present invention, a Schmitt circuit includes a first and a second PMOS transistor connected in series between a power supply voltage and an intermediate node, and a series connection between the intermediate node and a reference voltage. First and second connected to
Circuit comprising: an NMOS transistor, a first CMOS inverter that inverts the potential of the intermediate node and outputs an output signal, and second and third CMOS inverters that invert the output of the first CMOS inverter Wherein an input signal is input to the gates of the first PMOS transistor and the first NMOS transistor, an output of the second CMOS inverter is connected to the intermediate node, and the third CMOS inverter Is connected to the gates of the second PMOS transistor and the second NMOS transistor.

The Schmitt circuit according to claim 2 is the Schmitt circuit according to claim 1, wherein the first PM
An OS transistor and the first NMOS transistor constitute an output stage of a logic gate circuit such as a NOR or a NAND.

[0020]

<First Embodiment> FIG. 1 is a circuit diagram showing a configuration of a Schmitt circuit according to a first embodiment of the present invention. In this figure, 10, 20, 30, 4
0 is a CMOS inverter. The CMOS inverter 10 includes a PMOS transistor 11 and an NMO
It comprises an S transistor 12, and receives an input signal.
The CMOS inverter 20 includes a PMOS transistor 21 and an NMOS transistor 22. Further, the PMOS transistor 11 has P
The MOS transistor 13 has an NMOS transistor 14 between the NMOS transistor 12 and a reference voltage.
Are connected in series.

The CMOS inverter 30 inverts the potential at the connection point (intermediate node) between the PMOS transistor 11 and the NMOS transistor 12 and outputs an output signal.
The CMOS inverter 40 inverts the output of the CMOS inverter 30 and outputs the PMOS transistor 13 and the NMO
Output to the gate of S transistor 14. The output of the CMOS inverter 30 is further input to the gates of a PMOS transistor 21 and an NMOS transistor 22 forming the CMOS inverter 20, and the output of the CMOS inverter 20 is an intermediate node, that is, the CMOS inverter 30.
Is connected to the input side. That is, as shown in FIG.
The OS transistor 21 is connected to the PMOS transistors 11, 1
3 and the NMOS transistor 22 is connected in parallel to the NMOS transistors 12 and 14.

The operation of the Schmitt circuit shown in FIG. 1 will be described. First, a circuit state when the input voltage of the CMOS inverter 10, that is, the input voltage is at the reference voltage level (L level) will be described. When the input voltage of CMOS inverter 10 is at the reference voltage level, PMOS transistor 11 is conductive and NMOS transistor 1
2 is in the cutoff state, the output level of the CMOS inverter 10, that is, the input level of the CMOS inverter 30, is at the H level. Therefore, the CMOS inverter 3
The output level of 0, that is, the output signal of the Schmitt circuit is at the L level, and the output of the CMOS inverter 40 is at the H level. Accordingly, at this time, the NMOS transistor 14 and the PMOS transistor 21 are in a conductive state, and the PMOS transistor 13 and the NMOS transistor 22 are in a cutoff state. In this state, no current flows from the power supply voltage to the reference voltage.

Next, the input voltage of CMOS inverter 10 rises from the reference voltage level to the power supply voltage level (ie,
The case where the input signal transitions from L level to H level) will be described. As the input voltage of the CMOS inverter 10 gradually rises from the reference voltage level, the PM
The conduction resistance of the OS transistor 11 gradually increases, and NM
The conduction resistance of the OS transistor 12 gradually decreases.

As can be seen from FIG. 1, the input voltage of the CMOS inverter 30 depends on the PMOS transistors 11, 1
3, 21 and the combined resistance of the NMOS transistors 12,
14 and 22 are voltage levels obtained by dividing the voltage between the power supply voltage and the reference voltage. Until the input voltage of the CMOS inverter 30 falls below the threshold voltage of the CMOS inverter 30, the output level of the CMOS inverter 30 is at the L level.
OS transistor 13 and NMOS transistor 22
Is in a shut-off state. Therefore, as the conduction resistance of the NMOS transistor 12 gradually decreases, the input voltage of the CMOS inverter 30 gradually decreases from the power supply voltage level.

The NMOS transistor 14 and P
When the MOS transistor 21 is conducting and the PMOS transistor 13 and the NMOS transistor 22 are off, the input voltage of the CMOS inverter 30 becomes CMO.
In order to fall below the threshold voltage of the S inverter 30, the input voltage of the CMOS inverter 10
It must be higher than the threshold voltage of the inverter 10 alone. In other words, in this state, C for lowering the input voltage of the CMOS inverter 30 to the threshold voltage of the CMOS inverter 30 is used.
The input voltage of the MOS inverter 10 becomes a high-level threshold voltage of the hysteresis characteristic of the Schmitt circuit.

As described above, in the Schmitt circuit according to the present embodiment, when the input signal is gradually increased from the L level to the vicinity of the high-level threshold voltage, the conduction resistance of the PMOS transistor 11 is accordingly reduced. NMOS transistor 1
2, the conduction resistance gradually decreases. In the meantime, NMOS
Transistor 14 and PMOS transistor 21 are conducting, and PMOS transistor 13 and NMOS transistor 22 are off.

Therefore, at this time, the through current flowing between the power supply voltage and the reference voltage flows through the PMOS transistor 21 and the NMOS transistors 12 and 14, but the PMOS transistor 13 is in the cut-off state. 11 does not flow. As a result, the through current flowing between the power supply voltage and the reference voltage when the input voltage is near the threshold voltage is reduced as compared with the conventional Schmitt circuit shown in FIG.

When the input voltage of the CMOS inverter 10 exceeds the high-level threshold voltage of the Schmitt circuit and goes to the H level, the PMOS transistor 1
1 is turned off, and the NMOS transistor 12 is turned on, so that the output level of the CMOS inverter 10, that is, the input level of the CMOS inverter 30, becomes L level. Therefore, the output level of the CMOS inverter 30 (the output signal of the Schmitt circuit) is at the H level,
The output of inverter 40 is at L level. Therefore, at this time, the NMOS transistor 14 and the PMOS transistor 21 are in the cutoff state, and the PMOS transistor 13 and the NMOS transistor 22 are in the conductive state. In this state, no current flows from the power supply voltage to the reference voltage.

Next, a case where the input voltage of the CMOS inverter 10 falls from the power supply voltage to the reference voltage (that is, the input signal transitions from the H level to the L level) will be described. As the input voltage of the CMOS inverter 10 gradually decreases from the power supply voltage, the conduction resistance of the PMOS transistor 11 gradually decreases and the conduction resistance of the NMOS transistor 12 gradually increases.

As described above, the CMOS inverter 13
0 is applied to the PMOS transistors 11, 13, 2
1 and the NMOS transistors 12, 14,.
22 and a potential obtained by dividing the voltage between the power supply voltage and the reference voltage. Until the input voltage of the CMOS inverter 30 exceeds the threshold voltage of the CMOS inverter 30, the output level of the CMOS inverter 30 becomes H
Level, the NMOS transistor 14 and P
The MOS transistor 21 is kept off, and the PMOS transistor 13 and the NMOS transistor 22 are kept on. Therefore, the conduction resistance of the PMOS transistor 11 gradually decreases, and the CMOS inverter 30
Input voltage gradually rises from the power supply voltage level.

The NMOS transistor 14 and P
When MOS transistor 21 is off and PMOS transistor 13 and NMOS transistor 22 are on, input voltage of CMOS inverter 30 is CMO
In order to exceed the threshold voltage of the S inverter 30, the input voltage of the CMOS
It must be lower than the threshold voltage of the inverter 10 alone. That is, in this state, C for raising the input voltage of the CMOS inverter 30 to the threshold voltage of the CMOS inverter 30 is set.
The input voltage of the MOS inverter 10 becomes a threshold voltage on the low level side of the hysteresis characteristic of the Schmitt circuit.

From the above, it is apparent that the threshold voltage on the high level side is clearly higher than the threshold voltage on the low level side. Therefore, the hysteresis characteristic of the Schmitt circuit is obtained.

As described above, in the Schmitt circuit according to the present embodiment, when the input signal is gradually lowered from the H level to the vicinity of the threshold voltage on the low level side, the conduction resistance of the PMOS transistor 11 is accordingly reduced. NMOS transistor 1
The conduction resistance of No. 2 gradually increases. In the meantime, NMOS
The transistor 14 and the PMOS transistor 21 are turned off, and the PMOS transistor 13 and the NMOS transistor 22 are turned on.

Therefore, at this time, the through current flowing between the power supply voltage and the reference voltage depends on the PMOS transistors 13 and 1
1, but does not flow to the NMOS transistor 12 because the NMOS transistor 14 is in the cutoff state. As a result, the through current flowing between the power supply voltage and the reference voltage when the input voltage is near the threshold voltage is reduced as compared with the conventional Schmitt circuit shown in FIG.

In this embodiment, the PMOS transistor 11 and the NMOS transistor 12 receiving the input signal and the PMOS transistor 13 and the NMOS transistor 14 receiving the output of the CMOS inverter 40 are connected in series between the power supply voltage and the reference voltage. Although connected, the order of the arrangement is not limited to that shown in FIG.
That is, the PMOS transistors 11 and 13 are provided between the power supply voltage and the intermediate node, and the NMOS transistors 11 and 13 are provided between the intermediate node and the reference voltage.
As long as the transistors 12 and 14 are connected in series, the same effect as the Schmitt circuit of FIG. 1 can be obtained regardless of the order of the arrangement.

Second Embodiment In the first embodiment, the configuration using the CMOS inverter, that is, the NOT gate circuit in the input stage of the Schmitt circuit has been described. However, the scope of application of the present invention is not limited to the configuration, and CMOS
It is widely and easily applicable to Schmitt circuits using technology.

For example, FIG. 2 is a circuit diagram of a Schmitt circuit according to the second embodiment.
FIG. 3 is a circuit diagram when a NOR gate made of CMOS is used. In this figure, elements having the same functions as those in FIG. 1 are denoted by the same reference numerals. 50 is CMOS
In the output stage.
NOR gate 50 constructed using CMOS for output stage
Is, for example, as shown in FIG.
1 and 52 and NMOS transistors 53 and 54. Since the circuit configuration of the NOR gate 50 is generally well known, a detailed description thereof will be omitted.

Here, the Schmidt circuit shown in FIG.
CMOS inverter 10 in Schmitt circuit of FIG.
Is replaced by a NOR gate 50, which operates as a two-input OR gate having a hysteresis characteristic.

In the circuit of FIG. 2, similarly to the Schmitt circuit of FIG. 1, for example, when the output level of the NOR gate 50 is gradually increased from the reference voltage level, the PMOS transistor 13 is in the cut-off state. No through current flows between the power supply voltage and the reference voltage. Conversely, when the output level of the NOR gate 50 is gradually decreased from the power supply voltage level, the through current between the power supply voltage and the reference voltage flows through the NMOS transistors 53 and 54 because the NMOS transistor 14 is in the cutoff state. Absent. As a result, the through current flowing between the power supply voltage and the reference voltage when the input signal 1 and the input signal 2 are near the threshold voltage is smaller than that of the Schmitt circuit of the OR gate having neither the PMOS transistor 13 nor the NMOS transistor 14. Reduced.

The circuit configuration of the NOR gate 50 is shown in FIG.
Are not limited to those shown in FIG.
Any circuit configuration using an OS may be used.

FIG. 3 shows an example in which the CMOS inverter 10 in the Schmitt circuit of FIG. 1 is replaced with a NAND gate 60 using CMOS as its output, and is a two-input AND gate having hysteresis characteristics. It works. The NAND gate 60 includes, for example, PMOS transistors 61 and 6 as shown in FIG.
2. It is composed of NMOS transistors 63 and 64. Since the circuit configuration of the NAND gate 60 is generally well known, a detailed description thereof will be omitted.

In the configuration of FIG. 3, similarly to the Schmitt circuit of FIG. 1, for example, when the output level of the NAND gate 60 is gradually increased from the reference voltage level, the PMOS transistor 13 is in the cut-off state. No through current flows between 62 and 62 between the power supply voltage and the reference voltage. Conversely, when the output level of NAND gate 60 is gradually lowered from the power supply voltage level, NMO
Since the S transistor 14 is in the cutoff state, no through current between the power supply voltage and the reference voltage flows through the NMOS transistors 63 and 64. As a result, the PMOS transistor 13
And AN having a configuration having no NMOS transistor 14
As compared with the Schmitt circuit of the D gate, the through current flowing between the power supply voltage and the reference voltage when the input signal 1 and the input signal 2 are near the threshold voltage is reduced.

The circuit configuration of the NAND gate 60 is as follows.
The circuit configuration is not limited to that shown in FIG. 3 and may be any circuit configuration using CMOS in the output stage.

Furthermore, although a Schmitt circuit of a two-input AND gate and an OR gate is shown here as an example,
It is apparent that the scope of the present invention is not limited to these, but can be applied to any gate circuit using CMOS.

As described above, the PMOS transistor and the NMOS which are the input stages of the Schmitt circuit according to the present invention
Transistors constitute an output stage of a logic gate circuit such as NOR or NAND, so that even in a Schmitt circuit having a hysteresis characteristic operated by a plurality of input signals, the power supply voltage is reduced when the input signal is near a threshold voltage. Current flowing between the reference voltage and the reference voltage can be reduced.

[0046]

As described above, according to the Schmitt circuit of the first aspect, the first and second PMOS transistors connected in series between the power supply voltage and the intermediate node, the intermediate node and the reference voltage First and second NMOS transistors connected in series between them, a first CMOS inverter for inverting the potential of the intermediate node and outputting an output signal, and a second CMOS inverter for inverting the output of the first CMOS inverter
And a third CMOS inverter, wherein the input signal is a first PMOS transistor and a first NMOS
The input of the transistor, the output of the second CMOS inverter is connected to the intermediate node, the third CMOS
The output of the S inverter is connected to the gates of the second PMOS transistor and the second NMOS transistor. Therefore, when the input signal transitions from the reference voltage level to the power supply voltage level, no through current flows through the first PMOS transistor because the second PMOS transistor is in the cutoff state. When the input signal transitions from the power supply voltage level to the reference voltage level, the second NMOS
Since the transistor is in the cutoff state, no through current flows through the first NMOS transistor. As a result, the through current flowing between the power supply voltage and the reference voltage when the input signal is near the threshold voltage is reduced.

According to the Schmitt circuit according to the second aspect, in the Schmitt circuit according to the first aspect, the first PMOS transistor and the first NMOS transistor connect an output stage of a logic gate circuit such as a NOR or a NAND. With this configuration, even in a Schmitt circuit having a hysteresis characteristic operated by a plurality of input signals, a through current flowing between the power supply voltage and the reference voltage when the input signal is near the threshold voltage can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a Schmitt circuit according to a first embodiment.

FIG. 2 is a circuit diagram of a Schmitt circuit according to a second embodiment.

FIG. 3 is a circuit diagram of a Schmitt circuit according to a second embodiment.

FIG. 4 is a logic diagram showing a configuration of a conventional Schmitt circuit.

FIG. 5 is a circuit diagram for explaining an operation of a conventional Schmitt circuit.

[Explanation of symbols]

10, 20, 30, 40 CMOS inverters, 11,
13 PMOS transistor, 12, 14 NMOS transistor, 50 NOR gate, 60 NAND gate.

Claims (2)

[Claims] A first and a second PMOS transistor connected in series between a power supply voltage and an intermediate node; a first and a second NMOS transistor connected in series between the intermediate node and a reference voltage; A Schmitt circuit comprising: a first CMOS inverter for inverting the potential of the intermediate node to output an output signal; and second and third CMOS inverters for inverting the output of the first CMOS inverter. A signal is input to the gates of the first PMOS transistor and the first NMOS transistor, an output of the second CMOS inverter is connected to the intermediate node, and an output of the third CMOS inverter is 2nd P
A Schmitt circuit connected to gates of a MOS transistor and the second NMOS transistor. 2. The Schmitt circuit according to claim 1, wherein the first PMOS transistor and the first NM.
A Schmitt circuit, wherein the OS transistor forms an output stage of a logic gate circuit such as a NOR or a NAND.