JP2002343886A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory device realizing dynamic memory by the memory cell of simple transistor structure. SOLUTION: Each MIS transistor of the semiconductor memory device is provided with a semiconductor layer 12, a source area 15 formed at the semiconductor layer 12, a drain area 14 which is formed separately from the source area 15 on the semiconductor layer 12 and where the semiconductor layer between the source area 15 and the drain area becomes a channel body in a floating state, a first gate 13 for forming a channel at the channel body, a second gate 20 for controlling the potential of the channel body by capacity connection, and a high density area 21 formed on the second gate side of the channel body and having impurity density higher than that of the channel body.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device for dynamically storing data using a channel body of a transistor as a storage node.

[0002]

2. Description of the Related Art In a conventional DRAM, a memory cell is constituted by a MOS transistor and a capacitor. DR
The miniaturization of AM has been greatly advanced by adopting a trench capacitor structure or a stacked capacitor structure. Current,
Size of a unit memory cell (cell size), the minimum feature size is F, it is reduced to an area of 2F × 4F = 8F ^2. That is, when the minimum processing dimension F decreases with generation and the cell size is generally αF ² , the coefficient α also decreases with generation, and when F = 0.18 μm, α = 8 at present.
Has been realized.

[0003]

In order to secure the same trend of cell size or chip size as in the past, if F <0.18 μm, α <8 and F <0.1
In the case of 0.13 μm, α <6 is required to be satisfied, and how to form the cell size in a small area together with the fine processing is a major issue. Therefore, 1 transistor / 1
It proposed that the memory cell capacitor to the size of 6F ² or 4F ² is also made various. However, there are technical difficulties such as the need to make the transistors vertical, problems such as increased electrical interference between adjacent memory cells, and difficulties in manufacturing techniques such as processing and film formation. Absent.

An object of the present invention is to provide a semiconductor memory device capable of dynamically storing data using a memory cell having a simple transistor structure.

[0005]

In order to solve the above-mentioned problems, a semiconductor memory device according to the present invention is a semiconductor memory device having a plurality of MIS transistors for forming a memory cell, wherein each MIS transistor comprises: A semiconductor layer, a source region formed in the semiconductor layer, and a drain region formed apart from the source region in the semiconductor layer, wherein the semiconductor layer between the source region and the drain region is A drain region serving as a floating channel body; a first gate for forming a channel in the channel body; a second gate for controlling a potential of the channel body by capacitive coupling; A high concentration region formed on the side of the second gate, wherein the impurity concentration is higher than an impurity concentration of the channel body. Having things density, and a high concentration region,
Wherein the MIS transistor dynamically stores a first data state in which the channel body is set to a first potential and a second data state in which the channel body is set to a second potential. And

Further, a semiconductor memory device according to the present invention comprises:
A semiconductor memory device having a plurality of MIS transistors for forming a memory cell, wherein each MIS transistor includes a semiconductor layer, a source region formed in the semiconductor layer, and a semiconductor region separated from the source region in the semiconductor layer. A drain region formed, wherein the semiconductor layer between the source region and the drain region serves as a floating channel body; and a first region for forming a channel in the channel body. Gate and
Wherein the MIS transistor applies the same potential to the first gate when a channel current flows from the source region to the drain region and when a channel current flows from the drain region to the source region. In this case, the MIS transistor has an impact ionization near the drain junction or sets the semiconductor layer to a first potential by a drain leak current induced by the first gate. Dynamically storing a first data state and a second data state in which a forward bias current is applied between the drain region and the channel body to set the semiconductor layer to a second potential. I do.

[0007] A semiconductor memory device according to the present invention comprises:
A semiconductor memory device having a plurality of MIS transistors for forming a memory cell, wherein each MIS transistor includes a semiconductor layer, a source region formed in the semiconductor layer, and a semiconductor region separated from the source region in the semiconductor layer. A drain region formed, wherein the semiconductor layer between the source region and the drain region is a floating channel body, a drain region, and a gate for forming a channel in the channel body; The MIS transistor has a first data state in which the semiconductor layer is set to a first potential by flowing a drain leak current induced by applying a negative potential to a gate; A forward bias current flows between the channel body and the
And a second data state set at the potential of the semiconductor memory device.

[0008]

Embodiments of the present invention will be described below with reference to the drawings.

[Basic Concept] FIG. 1 shows a basic sectional structure of a unit memory cell MC of a DRAM according to each embodiment described later, and FIG. 2 shows an equivalent circuit thereof. The memory cell MC includes an N-channel MIS transistor having an SOI structure. That is, a silicon oxide film 11 is formed as an insulating film on a silicon substrate 10, and a p-type silicon layer 12 is formed on the silicon oxide film 11.
An OI substrate is used. Silicon layer 12 of this substrate
A gate electrode 13 is formed thereon via a gate oxide film 16, and n-type source / drain diffusion layers 14 and 15 are formed so as to be self-aligned with the gate electrode 13.

The source and drain 14 and 15 are formed to a depth reaching the silicon oxide film 11 at the bottom. Therefore, if the channel body made of the p-type silicon layer 12 is separated by an oxide film in the channel width direction (the direction perpendicular to the plane of the drawing), the bottom surface and the side surfaces in the channel width direction are insulated and separated from each other. The channel length direction is in a floating state in which a pn junction is separated.

When the memory cells MC are arranged in a matrix, the gate 13 is connected to the word line WL and the source 1
5 is connected to a fixed potential line (ground potential line),
4 is connected to the bit line BL.

FIG. 3 shows a layout of the memory cell array, and FIGS. 4A and 4B are AA 'and B of FIG. 3, respectively.
The section taken along the line -B 'is shown. The p-type silicon layer 12 is formed in a lattice pattern by burying the silicon oxide film 22. That is, the regions of the two transistors sharing the drain are separated from each other by the silicon oxide film 22 in the direction of the word line WL. Alternatively, the silicon oxide film 22
Instead of the burying, lateral isolation may be performed by etching the silicon layer 12. The gate 13 is formed continuously in one direction, and this becomes the word line WL. The source 15 is formed continuously in the direction of the word line WL and serves as a fixed potential line (common source line).

The transistor is covered with an interlayer insulating film 23, on which a bit line BL is formed. The bit line BL is
The drain 14 is arranged so as to contact the drain 14 shared by the two transistors and to cross the word line WL. In order to reduce the wiring resistance of the fixed potential line (common source line) of the source 15, a metal wiring parallel to the word line WL is formed above or below the bit line BL, and is formed for each of a plurality of bit lines. It may be connected to a fixed potential line.

As a result, the silicon layer 12, which is the channel body of each transistor, is separated from the bottom surface and the side surface in the channel width direction by the oxide film, and is separated from each other by the pn junction in the channel length direction to keep a floating state. It is.

In this memory cell array configuration, assuming that the word lines WL and the bit lines BL are formed at the pitch of the minimum processing size F, the unit cell area is 2F × 2F = 4F ² as shown by the broken line in FIG. Becomes

The operating principle of the memory cell MC composed of the n-channel MIS transistor utilizes the accumulation of holes, which are majority carriers, in the channel body of the MIS transistor (the p-type silicon layer 12 insulated and separated from the others). That is, by operating the transistor in the pentode region, a large current flows from the drain 14 and impact ionization occurs near the drain 14. Holes, which are majority carriers generated by the impact ionization, are held in the p-type silicon layer 12, and the hole accumulation state is, for example, data "1". The pn junction between the drain 14 and the p-type silicon layer 12 is forward-biased to
The state in which the excess holes in the type silicon layer 12 are released to the drain side is defined as data “0”.

The data "0" and "1" are stored as a difference between the potentials of the channel bodies and thus as a difference between the threshold voltages of the transistors. That is, the threshold voltage Vth1 in the data “1” state where the potential of the channel body is high due to the accumulation of holes becomes the threshold voltage Vth0 in the data “0” state.
Lower. In order to maintain the "1" data state in which holes serving as majority carriers are accumulated in the body, it is necessary to apply a negative bias voltage to the word lines. This data holding state is theoretically the same even if the read operation is performed, as long as the read operation is performed in the linear area, and the reverse data write operation (erase) is not performed. That is, non-destructive reading is possible, unlike a one-transistor / one-capacitor DRAM utilizing the charge storage of a capacitor.

There are several data reading methods. Word line potential Vwl and channel body potential VB
Is as shown in FIG. 5 in relation to data "0" and "1". Therefore, the first method of data reading is that the threshold voltage Vth of data “0” and “1” is applied to the word line WL.
0, Vth1, a read potential is given,
The fact that a current does not flow in a memory cell of "0" data and a current flows in a memory cell of "1" data is used. Specifically, for example, the bit line BL is precharged to a predetermined potential VBL, and then the word line WL is driven. Thus, as shown in FIG. 6, the bit line precharge potential VBL does not change in the case of "0" data, and the precharge potential VBL decreases in the case of "1" data.

In the second reading method, a current is supplied to the bit line BL after the word line WL is activated,
The fact that the rising speed of the bit line potential varies depending on the degree of conduction of “0” and “1” is used. Briefly, the bit line BL is precharged to 0V, and the word line WL is precharged as shown in FIG.
To supply a bit line current. At this time, data difference can be determined by detecting a difference in potential rise of the bit line by using a dummy cell.

The third read method is a method of reading a difference between bit line currents different between "0" and "1" when the bit line BL is clamped at a predetermined potential. To read the current difference, a current-voltage conversion circuit is required, but finally, the potential difference is differentially amplified to output a sense output.

According to the present invention, in order to selectively write "0" data, that is, holes are formed only from the channel body of the memory cell selected by the potential of the word line WL and bit line BL selected in the memory cell array. , The capacitive coupling between the word line WL and the channel body becomes essential. The state in which holes are accumulated in the channel body by data "1" is a state in which the word line is sufficiently biased in the negative direction, and the capacitance between the gate and the channel body of the memory cell becomes the gate oxide film capacitance (ie, the surface is depleted). (A state in which no layer is formed).

In the writing operation, it is preferable to reduce the power consumption as pulse writing for both "0" and "1". At the time of writing “0”, a hole current flows from the channel body to the drain of the selection transistor and an electron current flows from the drain to the channel body, but no hole is injected into the channel body.

A more specific operation waveform will be described. Fig. 8-
FIG. 11 shows read / refresh and read / write operation waveforms in the case of using the first read method in which data is determined based on whether or not a selected cell discharges a bit line.

FIGS. 8 and 9 show the read / refresh operation of "1" data and "0" data, respectively. Until time t1, the data is held (non-selected state).
A negative potential is applied to the word line WL. At time t1, the word line WL is raised to a predetermined positive potential. At this time, the word line potential is set to the threshold value Vth of “0” and “1” data.
It is set between 0 and Vth1. Thereby, in the case of "1" data, the bit line VBL which has been precharged in advance is
Become low potential by discharge. In the case of “0” data, the bit line potential VBL is held. As a result, "1",
"0" data is determined.

Then, at time t2, the potential of the word line WL is further increased. At the same time, when the read data is "1", a positive potential is applied to the bit line BL (FIG. 8), and the read data becomes "0". In this case, a negative potential is applied to the bit line BL (FIG. 9). As a result, when the selected memory cell is "1" data, a large channel current flows due to the pentode operation, impact ionization occurs, excess holes are injected and held in the channel body, and "1" data is written again. In the case of "0" data, the drain junction becomes forward biased, and "0" data in which no excess holes are held in the channel body is written again.

Then, at time t3, the word line WL is biased in the negative direction, and the read / refresh operation ends. In other unselected memory cells connected to the same bit line BL as the memory cell from which "1" data has been read, the word line WL is kept at a negative potential, and thus the channel body is kept at a negative potential, so that impact ionization does not occur. In other unselected memory cells connected to the same bit line BL as the memory cell from which "0" data was read, the word line W
L is held at a negative potential and no hole emission occurs.

FIGS. 10 and 11 show reading / writing of “1” data and “0” data by the same read method, respectively.
This is a write operation. The read operation at time t1 in FIGS. 10 and 11 is the same as in FIGS. 8 and 9, respectively.
After the reading, at time t2, the word line WL is set to a higher potential, and when writing "0" data to the same selected cell, a negative potential is applied to the bit line BL at the same time (FIG. 10), and "1"
When writing data, a positive potential is applied to the bit line BL (FIG. 11). As a result, in the cell to which "0" data is given, the drain junction becomes forward biased, and holes in the channel body are emitted. In a cell to which "1" data is given, impact ionization occurs near the drain, and excess holes are injected and held in the channel body.

FIGS. 12 to 15 show a second read operation in which the bit line BL is precharged to 0 V, a current is supplied to the bit line BL after the word line is selected, and data is determined based on the potential rising speed of the bit line BL. / When using the method
It is an operation waveform of refresh and read / write.

FIGS. 12 and 13 show the read / refresh operation of "1" data and "0" data, respectively. The word line WL held at the negative potential is changed to the time t1
To rise to a positive potential. At this time, the word line potential is
As shown in the figure, the threshold value Vt of the “0” and “1” data
The value is set to a value higher than h0 or Vth1. Alternatively, the word line potential is set in the same manner as in the first read method,
It may be set between threshold values Vth0 and Vth1 of “0” and “1” data. Then, a current is supplied to the bit line at time t2. As a result, in the case of "1" data, the memory cell is turned ON deeply and the potential rise of the bit line BL is small (FIG. 12). In the case of "0" data, the current of the memory cell is small (or no current flows). The bit line potential rises rapidly. Thus, "1" and "0" data are determined.

At time t3, when the read data is "1", a positive potential is applied to the bit line BL (FIG. 12), and when the read data is "0", the bit line BL
Is given a negative potential (FIG. 13). As a result, when the selected memory cell is “1” data, a drain current flows, impact ionization occurs, excess holes are injected and held in the channel body, and “1” data is written again.
In the case of "0" data, the drain junction becomes forward-biased, and "0" data without excess holes in the channel body is written again.

At time t4, the word line WL is biased in the negative direction, and the read / refresh operation ends.

FIGS. 14 and 15 show reading / writing of “1” data and “0” data by the same read method, respectively.
This is a write operation. The read operation at times t1 and t2 in FIGS. 14 and 15 is the same as in FIGS. 12 and 13, respectively. After reading, when writing “0” data to the same selected cell, a negative potential is applied to the bit line BL (FIG. 14), and when writing “1” data, the bit line BL
Is given a positive potential (FIG. 15). As a result, in the cell to which "0" data is given, the drain junction becomes forward-biased, and excess holes in the channel body are emitted.
In a cell to which "1" data is given, a large drain current flows, impact ionization occurs near the drain, and excess holes are injected and held in the channel body.

As described above, the memory cell M according to the present invention
C is constituted by a simple MIS transistor having the floating channel body which is electrically isolated from the other, the cell size of 4F ² can be realized. The potential control of the floating channel body utilizes the capacitive coupling from the gate electrode, and the source is also at a fixed potential. That is, the read / write control is performed by the word line W
L and bit line BL are simple. Furthermore, since the memory cell MC is basically a non-destructive read, it is not necessary to provide a sense amplifier for each bit line, and the layout of the sense amplifier is simplified. Further, since the current reading method is used, the resistance to noise is high. For example, reading can be performed by an open bit line method. Also, the manufacturing process of the memory cell is simple.

Also, the SOI structure will be used in the future logic LS
This is an important technology when considering the performance improvement of I. The DRAM according to the present invention has a logic L having such an SOI structure.
It is also very promising when mixed loading with SI. Unlike conventional DRAM using capacitors, logic LSI
This is because a process different from the above process is not required, and the manufacturing process is simplified.

Further, a DRA having an SOI structure according to the present invention is provided.
M is a conventional one transistor / one capacitor type DRA
There is an advantage that superior memory retention characteristics can be obtained as compared with the case where M has an SOI structure. That is, when the conventional one-transistor / one-capacitor type DRAM has the SOI structure, holes are accumulated in the floating channel body, the threshold value of the transistor decreases, and the sub-threshold current of the transistor increases. This degrades the memory retention characteristics. On the other hand, in the memory cell having only one transistor according to the present invention, there is no transistor path for reducing the storage charge, and the data retention characteristic is purely p.
It is determined only by the leakage at the n-junction, and the problem of subthreshold leakage is eliminated.

In the basic memory cell described above, how large a threshold voltage difference between data "0" and "1" stored as a difference in potential of the channel body is important for memory characteristics. become. According to a result of a simulation performed on this point, when data is written with potential control of the channel body by capacitive coupling from the gate, “0” and “1” immediately after writing are performed.
It has become clear that the channel body potential difference of "0" and "1" data in the subsequent data holding state is smaller than the channel body potential difference of data. The result of the simulation will be described below.

The device conditions are as follows: gate length Lg = 0.35
μm, the thickness of the p-type silicon layer 12 is tSi = 100 n
m, the acceptor concentration is NA = 5 × 10 ¹⁷ / cm ³ , and the donor concentration of the source 14 and the drain 15 is ND =
5 × 10 ²⁰ / cm ³ , gate oxide film thickness tox = 10
nm.

FIG. 16 shows the gate potential Vg and the drain potential Vg in "0" data writing, and thereafter, data holding and data reading (each shown instantaneously).
d and the potential VB of the channel body. FIG.
7 is the same as “1” data writing, and subsequent data holding and data reading (each shown instantaneously).
, The gate voltage Vg, the drain voltage Vd, and the channel body voltage VB.

In order to look at the threshold voltage Vth0 of "0" data and the threshold voltage Vth1 of "1" data in the data read operation from time t6 to time t7, the drain current Ids and the gate-source Voltage V
Drawing gs is as shown in FIG. Here, the channel width W and the channel length L are defined as W / L = 0.175 μm / 0.35
μm, and the drain-source voltage is Vds = 0.2V
And

FIG. 18 shows that the threshold voltage Vth0 of the “0” write cell and the threshold voltage Vth of the “1” write cell
The difference ΔVth of th1 is ΔVth = 0.32V. From the above analysis results, the problem is that the channel body potential immediately after writing “0” (time t3) is VB = −0.77 V and the channel body potential immediately after writing “1” in FIGS. VB = 0.85 V, and the difference is 1.62 V. In the data holding state (time t6), the channel body potential of the “0” write cell is VB = −2.04 V, “1” write The body potential of the cell is VB = -1.6 V, and the difference is 0.4
4V, which is smaller than immediately after writing.

As described above, there are two possible factors that reduce the difference in channel body potential due to data in the subsequent data holding state as compared to immediately after writing.

One is that the capacitance coupling from the gate to the channel body differs depending on the data.
Immediately after writing “0” (t3−t4), the drain is −
Although it is 1.5 V, the drain voltage is 2 V immediately after "1" is written. Therefore, when the gate potential Vg is subsequently reduced, the channel easily disappears in the “1” write cell,
The capacitance between the gate and the channel body becomes apparent, and holes gradually accumulate in the channel body to increase the capacitance. On the other hand, in the "0" write cell, the channel does not easily disappear, and the capacitance between the gate and the channel body does not appear.

If the drain potential is reset to 200 mV before starting to lower the gate potential, it seems that the above-mentioned imbalance is eliminated. But in this case,
In the cell in which “0” write has been performed, the drain potential rises in a state where the channel is formed, and a current flows by the triode operation. Then, the channel body potential lowered by writing “0” undesirably increases due to capacitive coupling between the n-type drain and the channel inversion layer and the p-type channel body.

The other is time t4 to t5 after writing.
During this period, the channel body potential is affected by the capacitance of the pn junction between the source or drain and the channel body, and this acts to reduce the signal amount of "0" and "1" data.

Therefore, a gate (first gate) for controlling the channel formation for the basic memory cell.
Separately, a gate (second gate) for controlling the potential of the channel body by capacitive coupling is added. In order to secure the capacitance between the second gate and the channel body,
On the surface on the second gate side, a high-concentration region of the same conductivity type as that of the channel body is formed so as to maintain an accumulation state (accumulation state) without forming a channel inversion layer. The second gate is driven, for example, at a lower potential than the first gate or at the same potential in synchronization with the first gate. Alternatively, the second gate is, for example,
The potential may be fixed to a reference potential applied to the source or a potential lower than the reference potential (a negative potential in the case of an n-channel).

A specific embodiment will be described below.

[First Embodiment] FIG. 19A shows a structure of a memory cell MC according to a first embodiment of the present invention, corresponding to FIG. The basic structure is the same as in FIG.
The difference from FIG. 1 is that the first gate 1
Separately from the oxide film 11 is a second gate 20 which is capacitively opposed to the silicon layer 12 via a gate insulating film 19.
And a point that a p ⁺ -type layer 21 having a high concentration such that a channel inversion layer is not formed is formed on the surface of the silicon layer 12 on the second gate 20 side.
That is, the p ⁺ -type layer 21 having the same conductivity type as the silicon layer 12 and an impurity concentration higher than the impurity concentration of the silicon layer 12 is formed in the silicon layer 12. The presence of the p ⁺ -type layer 21 allows a channel to be formed in the channel body on the first gate 13 side even when writing is performed by applying a positive potential to the first gate 13 and the second gate 20. Formed, but the second gate 20
A channel is formed in the side channel body.

In the memory cell MC of this embodiment, the gate insulating film 19 has the same thickness as the gate insulating film 16 on the first gate 13 side.

In an actual memory cell array configuration, FIG.
A, a plurality of memory cells MC shown in FIG.
The first gate 13 is formed continuously as a first word line WL1, and the second gate 20 is provided as a second word line WL2 parallel to the first word line WL1.

FIG. 19B shows an equivalent circuit of a memory cell array in which a plurality of such memory cells MC are arranged in a matrix. First of a plurality of memory cells MC arranged in one direction
Gate (G1) 13 is connected to the first word line WL1, and the second gate (G2) 20 is connected to the second word line W1.
L2. A bit line BL to which the drain of the memory cell MC is connected is arranged in a direction crossing these word lines WL1 and WL2. Sources 15 of all memory cells MC are connected to a fixed potential line (ground potential line VSS).

FIG. 19C shows the layout of the memory cell array, and FIGS. 19D and 19E show the layout of A in FIG. 19C, respectively.
The cross section taken along line -A 'and BB' is shown. The p-type silicon layer 12 is formed in a lattice pattern by burying the silicon oxide film 22. That is, the regions of the two transistors sharing the drain 14 are arranged in the direction of the word lines WL1 and WL2 by element isolation by the silicon oxide film 22. Alternatively, instead of embedding the silicon oxide film 22,
By etching the silicon layer 12, lateral element isolation may be performed. The first gate 13 and the second gate 20 are continuously formed in one direction, and become the word lines WL1 and WL2. The source 15 is formed continuously in the direction of the word lines WL1 and WL2, and serves as a fixed potential line (common source line). The transistor is covered with an interlayer insulating film 17 on which the bit line (BL) 1
8 are formed. The bit line 18 contacts the drain 14 shared by the two transistors, and the word line W
It is arranged so as to intersect L1 and WL2.

Thus, the silicon layer 12, which is the channel body of each transistor, is separated from each other by the oxide film on the bottom surface and the side surface in the channel width direction, and is separated from each other by the pn junction in the channel length direction, and is kept in a floating state. Dripping.

In this memory cell array configuration, assuming that the word lines WL1 and WL2 and the bit lines BL are formed at the pitch of the minimum processing size F, the unit cell area is as shown in FIG.
As indicated by the broken line in FIG. 9C, 2F × 2F = 4F ² .

With such a configuration, the same operation as described above using the basic memory cell is performed. At this time, the second
The word line WL2 is driven at a lower potential than the first word line WL1 in synchronization with the first word line WL1. Thus, the second gate 20 is connected to the first gate 13
, Data “0” and “1” with a large difference in threshold voltage can be written. That is, the second gate 20 is set to a negative potential in the data holding state, and is set to “1”.
By raising the potential at the time of data writing while maintaining the data accumulation state in a good state, the channel body potential is raised by capacitive coupling, and data writing can be ensured.

That is, in the case of writing “0” data, a positive potential is applied to the first gate 13. Then, a channel inversion layer is formed on the first gate 13 side of the channel body. However, when the channel inversion layer is formed, the channel inversion layer becomes a hindrance factor, and the capacitive coupling to the channel body by the first gate 13 is weakened. Therefore, even if a positive potential is applied to the first gate 13, the potential of the channel body cannot be sufficiently increased.

However, in this embodiment, the second game
By applying a positive potential to the
The potential of D can be sufficiently increased. Why
And p ⁺Since the mold layer 21 is formed, the channel body
A channel inversion layer is formed on the second gate 20 side of the transistor.
Therefore, a positive potential is applied to the second gate 20.
By doing so, the potential of the channel body can be sufficiently
Can be raised. For this reason,
"0" data writing is possible.

The data is held by lowering the potential of the unselected first word line WL1. At this time, the potential of the paired second word line WL2 is also lowered to control the channel body potential lower. When writing “0” data in another cell connected to the same bit line,
Data destruction in non-selected cells holding "1" data is reliably prevented. Furthermore, in a non-selected "0" data cell connected to a "1" write bit line, there is a concern that data may be destroyed due to surface breakdown or GIDL current.
In the case of this embodiment, these concerns are resolved by lowering the channel body potential by the second word line.

Further, when writing "0", if the potential of the bit line is greatly reduced, a current flows from the source to the bit line. In this embodiment, however, the second gate 20 increases the channel body potential. It is not necessary to lower the bit line potential so much. For example, the current flowing from the source to the bit line can be suppressed by setting the bit line potential to the same level as the reference potential of the source.

When data is read, "1" is erroneously detected.
It is necessary to operate the triode so as not to write. Therefore, the potential of the bit line is lower than that at the time of “1” writing, but the extension of the depletion layer between the drain and the channel body is smaller than that at the time of “1” writing, so that the capacitive coupling between the bit line and the channel body becomes larger. . This causes the carriers injected into the channel body at the time of writing to be redistributed in capacity, causing a decrease in the channel body potential. In this embodiment, the majority carrier accumulation state of the channel body can be favorably maintained by the control by the second gate 20.

In the above description, the second gate 20 is driven at a lower potential with respect to the first gate 13.
^{Since the +} type layer 21 is formed, even if the second gate 20 is driven at the same potential as the first gate 13, a channel inversion layer is not formed, and a large capacitive coupling to the channel body is achieved. The potential can be controlled.

The thickness of the gate insulating film 16 on the first gate 13 side and the thickness of the gate insulating film 19 on the second gate 20 side do not need to be the same. Each can be set optimally.

Although the first gate 13 and the second gate 20 face the upper and lower surfaces of the silicon layer in this embodiment, they may face the same surface. Specifically, the first gate and the second gate are integrally provided, and a high-concentration region for preventing formation of a channel inversion layer is formed in a part of the channel region. Operation becomes possible. The first gate and the second gate can be separately arranged on the same surface of the silicon layer.

FIG. 19F is a perspective view showing a configuration of a memory cell MC in which the first gate 13 and the second gate 20 are integrated, and FIG. 19G is a cross-sectional view taken along the line AA ′ of FIG. 19F. 19H shows a BB ′ section of FIG. 19F.

As can be seen from these figures, in this example, the second gate 20 is not formed, and the first gate 13 plays a role similar to that of the second gate 20. For this purpose, a high-concentration p ⁺ -type layer 21 is formed in a half region on the surface side of the silicon layer 12. That is, in this example, the silicon layer 12 is formed as a p ⁻ -type region having a low impurity concentration, and the p ⁺ -type layer 21 is formed as a p ⁺ -type region having a higher impurity concentration.

The p ⁺ type layer 21 is formed in a region approximately half of the silicon layer 12 in plan view. p
The depth of the ⁺ type layer 21 is formed up to a position between the gate insulating film 16 and the oxide film 11. Alternatively, the oxide film 11
You can reach it. The size of the p ⁺ -type layer 21 is arbitrary. It is sufficient that the potential can be controlled by a large capacitive coupling to the channel body so that the channel inversion layer is not formed when the first gate 13 is driven.

FIG. 19I is a diagram showing a layout of a memory cell array in which the memory cells MC shown in FIG. 19F are arranged in a matrix, and is a diagram corresponding to FIG. 19C.
FIG. 19J is a diagram showing a cross section AA ′ of FIG. 19I,
FIG. 19K is a diagram showing a BB ′ cross section of FIG. 19I,
FIG. 19L is a diagram showing a CC ′ cross section of FIG. 19I.

As can be seen from these figures, the gate 13
Are continuously formed in one direction to form one word line WL. However, in this example, the second word line WL2 is not formed because the second gate 20 does not exist. The bit line 18 is disposed so as to contact the drain 14 shared by the two transistors and cross the word line WL. Then, ap ⁺ -type layer 21 is formed on a part of the channel body between the drain 14 and the source 15 on the word line WL side.

In the memory cell MC, as shown in FIG. 19H, the p ⁺ -type layer 21 is formed so as to be in contact with the drain region 14 and the source region 15 in the BB ′ cross-sectional direction. . However, the p ⁺ type layer 21 does not necessarily have to be in contact with the drain region 14 and the source region 15.

FIGS. 19M and 19N show such examples. FIG. 19M is a perspective view showing the configuration of the memory cell MC, and corresponds to FIG. 19F. FIG. 19N is a diagram showing a BB ′ cross section in FIG. 19M, and FIG.
FIG. The section taken along the line AA ′ in FIG. 19M is the same as FIG. 19G shown above.

As shown in FIGS. 19M and 19N, the p ⁺ -type layer 21 has a drain region 14 and a source region 1.
No contact with 5. This can prevent the retention time of the memory cell MC from being shortened. More specifically, p
⁺ -Type layer 21, n-type drain region 14, and source region 15
Directly contact with each other, the extension of the depletion layer when a reverse bias is applied to the pn junction is reduced. Then, the strength of the electric field increases, the leakage current at the pn junction increases, and the retention time, which is the time during which the memory cell MC can hold data, is shortened.

On the other hand, as shown in FIGS. 19M and 19N, such a situation can be avoided by forming the p ⁺ -type layer 21 so as not to contact the drain region 14 and the source region 15. it can. That is, the p ⁺ type layer 21
Can make the retention time of the memory cell MC longer than in the case where the drain region 14 and the source region 15 are in contact with each other.

[Second Embodiment] FIG. 20 shows a second embodiment.
Is the structure of the memory cell MC. Unlike the embodiment of FIG. 19A, in this embodiment, the second gate 20
Is a common gate (backplate) that is not patterned as wiring and covers the entire cell array area
It is arranged as. That is, the second gate 20 is provided commonly to all the MIS transistors in the memory cell array. With such a structure, the alignment of the second gate 20 and the first gate 13 is not required, and the manufacturing process is simplified.

With such a configuration, the second gate 20 is fixed to, for example, the source potential or a potential lower than the source potential.
The same operation as described in the previous basic memory cell is performed. Also in this case, by increasing the amplitude of the first gate 13 (word line WL), the signal difference between “0” and “1” data can be increased. That is, the second gate 20
Is capacitively coupled to the channel body at a fixed potential,
The capacitance coupling from the gate 13 to the channel body is reduced by the capacitance division as compared with the case of the basic memory cell. However, by increasing the driving amplitude of the first gate 13, the potential of the channel body by the first gate 13 can be controlled without a large difference between “0” and “1” data. In the data holding state, it is possible to increase the difference between the threshold voltages of “0” and “1” data.

[Third Embodiment] FIG. 21 shows a third embodiment.
22 shows a layout of the memory cell array, and FIG. 22 shows a section taken along the line AA ′. In the embodiments described above, an SOI substrate is used to manufacture a transistor having a floating channel body. In this embodiment, a so-called SGT (Surroundin) is used.
g GateTransistor) structure,
A memory cell is constituted by a vertical MIS transistor having a floating channel body.

In the silicon substrate 10, grooves running vertically and horizontally are processed by RIE to form p-type columnar silicon 30 in an array. A first gate 13 and a second gate 20 are formed so as to face both side surfaces of each of the columnar silicon 30. The first gate 13 and the second gate 20 are alternately embedded between the columnar silicon 30 in the cross section of FIG. The first gate 13 is formed as an independent gate electrode between the adjacent columnar silicon 30 between the adjacent columnar silicon 30 by the technique of leaving the side wall. On the other hand, the second gates 20 are buried between adjacent columnar silicons 30 so that they are shared. The first and second gates 13 and 20 are continuously patterned as first and second word lines WL1 and WL2, respectively.

An n-type drain diffusion layer 14 is formed on the upper surface of the columnar silicon 30, and an n-type source diffusion layer 15 shared by all cells is formed below. The columnar silicon layer 3
The p ⁺ -type layer 21 is formed on the side surface of the second gate 20 on the side of the second gate 20. As a result, a memory cell MC including a vertical transistor in which each channel body is floating is configured. An interlayer insulating film 17 is formed on the substrate in which the gates 13 and 20 are embedded, and a bit line 18 is provided thereon.

According to this embodiment, the same operation as each of the previous embodiments can be performed. According to this embodiment,
It is not necessary to use an SOI substrate, so that only memory cells have a floating channel body of vertical transistors, and peripheral circuits other than the cell array, such as sense amplifiers, transfer gates, row / column decoders, use ordinary planar transistors. Can be. Therefore, unlike the case of using the SOI substrate, it is not necessary to form a contact for fixing the channel body potential of the peripheral circuit transistor in order to eliminate the instability of the circuit due to the channel body floating effect. The area of the part can be reduced.

[Embodiment 4] FIGS. 23 and 24 show a cell array layout and an AA ′ cross section of an embodiment using an SGT structure similar to that of Embodiment 3 in FIGS. 21 and 22, respectively. It is shown correspondingly. The difference from the third embodiment is that the gates 13 and 20 are integrally formed with the columnar silicon layer 30.
Is arranged as a common word line WL. Gate 20 of columnar silicon layer 30
The p ⁺ -type layer 21 is formed on the side surface facing the same as in the third embodiment.

In the case of this embodiment, the gates 13 and 20
Are driven integrally at the same potential as the word line WL. Since the gate 20 has the p ⁺ -type layer 21, no channel inversion layer is formed.
L can be coupled to the channel body with a large capacitance to control its potential. The surface on which the p ⁺ -type layer 21 is formed is not limited to one surface of the columnar silicon layer 30, but may be formed on two surfaces or three surfaces. That is, the p ⁺ type layer 21 may be formed on one or more surfaces of the columnar silicon layer 30.

[Fifth Embodiment] FIG. 25A shows a structure of a memory cell MC according to an embodiment capable of improving the reliability of writing "0" data, corresponding to FIG. The difference of the memory cell structure of this embodiment from FIG. 1 is that the gate 13 has an offset with respect to the drain 14. That is, the gate 13 is formed on the source 15 on the channel body side via the gate insulating film 16.
Are formed. That is, the amount of overlap of the gate 13 with the source 15 is positive. On the other hand, drain 1
No gate 13 is formed on 4. That is, the amount of overlap of the gate 13 with the drain 14 is negative.

This can be easily realized by oblique ion implantation for the drain 14 and the source 15 as shown in FIG. 25A. Alternatively, the same offset structure can be obtained by performing normal ion implantation in a state where a sidewall insulating film is formed only on the gate side wall on the drain side, instead of oblique ion implantation. Others are the same as FIG.

In the memory cell according to the above-described embodiment, “0” writing applies a forward bias between the drain region 14 and the channel body to discharge majority carriers in the channel body to the drain region 14. in this case,
In the normal transistor structure shown in FIG. 1, a channel inversion layer is formed and serves as a shield layer between the gate 13 and the channel body, and the capacitive coupling between the channel inversion layer and the channel body increases. As a result, when the drain region 14 is returned from the negative potential to 0 V, the channel body potential increases due to the capacitive coupling between the channel inversion layer and the channel body, and there is a possibility that sufficient “0” writing cannot be performed. In addition, since the capacitance between the gate 13 and the channel body is reduced due to the channel inversion layer, the effect of the bit line is increased. Further, when a channel inversion layer is formed, a channel current (an electron current in the case of n-channel) flows. This channel current is a current unnecessary for a write operation, and not only causes an increase in write power, but also, if impact ionization occurs, a "1" write mode is set, and the reliability of "0" write is reduced. .

On the other hand, as shown in FIG. 25A, when an offset structure is provided on the drain side, in a normal transistor operation in which a positive potential is applied to the drain region 14 and the drain junction is reverse-biased, As shown in FIG. 25B, a depletion layer DL extending from the drain region 14 extends right below the gate 13. Therefore, by applying a positive voltage to the gate 13, a channel inversion layer CH is formed between the depletion layer DL from the drain region 14 and the source region 15, and between the drain region 14 and the source region 15. The channel current flows. That is, the memory cell MC shown in FIG. 25A normally operates as a MIS transistor as shown in FIG. FIG. 26 is a graph showing the relationship between the voltage Vd applied to the drain region 14 and the current Id flowing between the source and the drain. The graph shows characteristics when the voltage Vg applied to the gate 13 is changed.

However, when a negative potential is applied to the drain region 14, the transistor operates as a drain,
The function of the source is reversed. As shown in FIG. 25C, the depletion layer DL is formed on the source region 15 side, and the channel inversion layer CH is formed away from the source region 14. For this reason, as shown in FIG.
Almost no channel current flows between the gate electrode and the source region 15.

Therefore, according to this embodiment, at the time of writing "0" (ie, when a forward bias is applied between the drain region 14 and the channel body as shown in FIG. 25C), the drain region 14 and the channel body The rise of the channel body potential due to unnecessary capacitive coupling with
The “0” write margin can be increased. Further, unnecessary channel current at the time of writing “0” can be suppressed, the write current flowing through the bit line BL can be reduced, and the write power can be reduced.

In the above, the case where almost no current flows in the reverse direction has been described. However, by giving a slight asymmetry with a difference of 10% or more in the channel current, the effect of similarly reducing the current can be obtained. An offset on the drain region 14 side is one of means for making the channel current asymmetric when the source and the drain are reversed.
Other techniques can be used to impart asymmetry to the channel current when the drain is reversed. That is, the MIS transistor has different characteristics between the case where a channel current flows from the source region 15 to the drain region 14 and the case where a channel current flows from the drain region 14 to the source region 15 even when the same potential is applied to the gate 13. What is necessary is just to have.

[Embodiment 6] FIGS. 27 and 28 show the memory cell MC of FIGS. 19A and 20 respectively.
Similarly, an embodiment in which a gate offset structure is introduced is shown. According to this embodiment, similarly, unnecessary current at the time of writing “0” can be reduced.

FIGS. 29A and 29B show an embodiment in which a gate offset structure is similarly introduced for the memory cell MC using the SGT structure. FIG. 29A
FIG. 29B is a plan view showing a layout of a memory cell array constituted by such memory cells MC, and FIG.
It is a figure which shows the AA 'cross section of FIG. 29A. These FIG.
As shown in FIG. 29A and FIG. 29B, the gate 13 is a single body surrounding the columnar silicon layer 30. Also, the high concentration region of the p ⁺ type layer 21 is not formed in the columnar silicon 30.

As shown in FIG. 29B, the columnar silicon layer 3
0, around the source 15 on the channel body side,
The gate 13 is formed via the gate insulating film.
That is, the amount of overlap of the gate 13 with the source 15 is positive. On the other hand, the gate 13 is not formed around the drain 14 in the columnar silicon layer 30. That is, the amount of overlap of the gate 13 with the drain 14 is negative.

FIG. 30A is a plan view showing a layout of a memory cell array composed of memory cells having a gate offset structure introduced in the third embodiment shown in FIGS. 21 and 22. FIG. 30B is a view showing AA ′ in FIG. 30A.
It is a figure showing a section. As shown in FIGS. 30A and 30B, the first gate 13 is formed shifted to the source region 15 side. That is, the columnar silicon layer 3
The first gate 13 is formed on the side surface of the source 15 at 0 through a gate insulating film. That is, the first
Of the gate 13 with respect to the source 15 is positive. On the other hand, the first gate 13 is not formed on the side surface of the drain 14 in the columnar silicon layer 30. That is, the amount of overlap of the first gate 13 with the drain 14 is negative. Other configurations are the same as those of the third embodiment described above, and the first gate 13 and the second gate 20 are provided as separate word lines.

FIG. 30C is a plan view showing a layout of a memory cell array constituted by memory cells having a gate offset structure introduced in the fourth embodiment of FIGS. 23 and 24. FIG. 30D shows A-
It is a figure which shows A 'cross section. These FIGS. 30C and 30D
As shown in (1), the first gate 13 is formed shifted to the source region 15 side. That is, the first gate 13 is formed on the side surface of the source 15 in the columnar silicon layer 30 via the gate insulating film. That is,
The amount of overlap of the first gate 13 with the source 15 is positive. On the other hand, the first gate 13 is not formed on the side surface of the drain 14 in the columnar silicon layer 30. That is, the amount of overlap of the first gate 13 with the drain 14 is negative. Other configurations are the same as those of the above-described fourth embodiment, and the first gate 13 and the second gate 20 are arranged as a common word line.

Similarly, according to the sixth embodiment,
Unnecessary current at the time of writing “0” can be eliminated.

[Embodiment 7] In the embodiments described so far, the substrate current caused by impact ionization near the drain junction is used for writing “1”, but instead of the impact ionization, the drain leakage induced by the gate is used. A current, a so-called GIDL current, can also be used. FIG. 31 shows that the gate length / gate width = 0.175 μm /
4 shows a gate voltage-drain current characteristic of a 10 μm MISFET. When the gate length becomes short, a large substrate current flows when a positive drain voltage Vd is applied in a region where the gate voltage Vg is negative as shown in the figure. This is GIDL
This is a current, and "1" can be written by using the current.

FIG. 32 shows "1" using the GIDL current.
3 shows operation waveforms of writing / reading. Unlike the case where impact ionization is used, at the time of writing "1", the gate voltage Vg is made negative and the drain voltage Vd is made positive. Thereby, holes can be injected and accumulated in the channel body by the GIDL current.

The "1" write method using the GIDL current can be applied not only to the basic memory cell structure shown in FIG. 1 but also to the memory cell structure of each embodiment shown in FIG. It is possible.

[Eighth Embodiment] FIGS. 33, 34A and 34B show an embodiment in which the silicon layer 12 is formed in a convex stripe shape on the insulating film 11. FIG. FIG. 33 is a plan view showing a layout of a memory cell array including such memory cells, and FIG.
FIG. 34B is a view showing a section taken along the line A ′, and FIG.
It is a figure which shows the -B 'cross section.

In this case, the gate 13 can be said to be the one in which the first gate and the second gate of each of the above embodiments are integrally formed, and are opposed to the upper surface and both side surfaces of the convex silicon layer 12. Specifically, this structure is formed by the element isolation insulating film 2
4 can be obtained by embedding the silicon layer 12 in a protruding state. And the silicon layer 12
Out of the three surfaces facing each other, for example, p
^{The +} type layer 21 is formed, and this is used as a capacitive coupling portion where the channel inversion layer is not formed. In addition, the p ⁺ type layer 21 is formed of three surfaces of the upper surface and both side surfaces of the silicon layer 12.
It may be formed on one or more surfaces.

Thus, the same operation as in each of the above embodiments can be performed.

[Embodiment 9] According to each of the above-described embodiments, a memory cell array capable of dynamic storage is constructed by using one MIS transistor as a 1-bit memory cell MC. Then, as described above, when the first gate 13 and the second gate 20 are formed separately, the first word line WL1 and the second word line WL2 may be driven synchronously at different potentials. , May be driven synchronously at the same potential.

FIGS. 35A and 35B show voltage waveforms of the word lines WL1 and WL2 and the bit line BL at the time of data writing. A pair of the first word line WL1 and the second word line WL1
Are synchronously driven. FIG. 35A shows that the second gate 20 is controlled at a lower potential than the first gate 13 when the first gate 13 and the second gate 20 are separately formed, and the second gate of the channel body is formed. 20 enables the majority carrier accumulation. On the other hand, FIG. 35B shows that the first gate 13 and the second gate 20 are driven at the same potential to enable majority carrier accumulation on the second gate 20 side of the channel body. This figure 3
5B has a first gate 13 and a second gate 2
The same applies to the case where 0 is commonly formed.

In the case of FIG. 35A, when "1" data is written, the reference potential VSS is applied to the selected first word line WL1.
The higher potential VWL1H is applied, and the lower potential VWL2H is applied to the second word line WL2 selected at the same time.
(In the example of the figure, a positive potential higher than the reference potential VSS).
A positive potential VBLH higher than the reference potential VSS is applied to the selected bit line BL. Thereby, in the selected memory cell MC, impact ionization occurs due to the pentode operation, and holes are accumulated in the channel body.

For data retention, a negative potential VWL1L lower than the reference potential VSS is applied to the first word line WL1,
Has a lower potential VWL2L.
give. As a result, "1" data in which excess holes are accumulated in the channel body is held.

At the time of writing "0" data, the same potentials VWL1H and VWL2 as at the time of "1" writing are respectively applied to the selected first and second word lines WL1 and WL2.
H, and the reference potential VSS is applied to the selected bit line BL.
Apply a lower negative potential VBLL. As a result, in the selected memory cell MC, the drain junction becomes forward-biased, holes in the channel body are discharged to the drain 14, and "0" data with a low channel body potential is written.

In the case of FIG. 35B, when "1" data is written, the selected first and second word lines WL1 and WL
2 is given a positive potential VWLH higher than the reference potential VSS,
A positive potential VBLH higher than the reference potential VSS is applied to the selected bit line BL. Thereby, in the selected memory cell MC, impact ionization occurs due to the pentode operation, and holes are accumulated in the channel body.

The data is held by the first and second word lines W
A negative potential VW lower than the reference potential VSS is applied to L1 and WL2.
Give LL. As a result, "1" data in which excess holes are accumulated in the channel body is held.

At the time of writing “0” data, the same potential VWLH as at the time of “1” writing is applied to the selected first and second word lines WL1 and WL2, and the selected bit line BL is lower than the reference potential VSS. A negative potential VBLL is applied.
As a result, the drain junction of the selected memory cell MC becomes forward-biased, holes in the channel body are discharged to the drain, and "0" data with a low channel body potential is written.

Next, an example of a specific circuit configuration of the row decoder and the word line driver in this embodiment will be described. FIG. 35C is a diagram illustrating an example of the row decoder and an example of the word line driver WDDV1 for generating the voltage waveforms of the word lines WL1 and WL2 illustrated in FIG. 35B.

As shown in FIG. 35C, the row decoder RDEC includes a NAND circuit C10, and the word line driver WDDV1 includes an inverter circuit C10.
11, a level conversion circuit C12, and a level conversion circuit C1.
3 and an output buffer circuit C14. With this configuration, the word line driver WDDV1 selected by the row decoder RDEC converts a high-level potential to VWLH, which is higher than the positive potential VCC, and supplies it to the word lines WL1 and WL2.

More specifically, the row address signal RADD and the word line enable signal WLEN are input to the NAND circuit C10. Selected word line WL
1, the word line driver WDDV1 corresponding to WL2 has a row address signal RADD of high level,
A high-level word line enable signal WLEN is input. Therefore, the selected word lines WL1, WL2
The output of the NAND circuit C10 of the word line driver WDDV1 corresponding to the low level becomes the low level, that is, the reference potential VSS. The output of the NAND circuit C10 is
11 is input.

This inverter circuit C11 inverts the input signal and outputs the inverted signal. Therefore, in the selected word line driver WDDV1, the inverter circuit C
The output of No. 11 is at a high level, that is, a positive potential VCC. The output of the inverter circuit C11 is input to the level conversion circuits C12 and C13. The output of the NAND circuit C10 is also input to the level conversion circuits C12 and C13.

The outputs of the level conversion circuits C12 and C13 are input to an output buffer circuit C14. Level conversion circuit C12 and output buffer circuit C14
As a result, the output of VCC, which is the high-level output potential of the inverter circuit C11, is converted to VWLH, which is a positive potential higher than VCC, and supplied to the word lines WL1, WL2. Further, the level conversion circuit C13 and the output buffer circuit C14 convert the output of VSS, which is the low-level output potential of the inverter circuit C11, to VWLL, which is lower than VSS, and supply it to the word lines WL1, WL2. .

In this embodiment, level conversion circuit C12 includes p-type MOS transistors PM10, PM1
1 and n-type MOS transistors NM10 and NM11. p-type MOS transistor P
The source terminals of M10 and PM11 are connected to the potential VW
LH supply line, and its drain terminal is
N-type MOS transistors NM10, NM11
Is connected to the drain terminal. The gate terminal of the p-type MOS transistor PM10 is connected to a node between the p-type MOS transistor PM11 and the n-type MOS transistor NM11.
The gate terminal of M11 is a p-type MOS transistor PM1
It is connected to a node between 0 and the n-type MOS transistor NM10.

The output of the inverter circuit C11 is input to the gate terminal of the n-type MOS transistor NM10.
The gate terminal of the type MOS transistor NM11 has an NA
The output of the ND circuit C10 is input. These n-type MOS
Source terminals of the transistors NM10 and NM11 are respectively connected to a supply line of the potential VSS.

On the other hand, the level conversion circuit C13 is a p-type MO
It comprises S transistors PM12 and PM13 and n-type MOS transistors NM12 and NM13. The source terminals of the p-type MOS transistors PM12 and PM13 are respectively connected to a supply line of the potential VCC, and the drain terminals are connected to the drain terminals of the n-type MOS transistors NM12 and NM13, respectively. The output of the inverter circuit C11 is input to the gate terminal of the p-type MOS transistor PM12.
The gate terminal of the p-type MOS transistor PM13 has N
The output of the AND circuit C10 is input.

The gate terminal of the n-type MOS transistor NM12 is connected to the p-type MOS transistor PM13 and the n-type MOS transistor NM12.
The gate terminal of the n-type MOS transistor NM13 is connected to a node between the transistor NM13 and the transistor NM13.
It is connected to a node between the p-type MOS transistor PM12 and the n-type MOS transistor NM12. Also,
Source terminals of these n-type MOS transistors NM12 and NM13 are connected to a supply line of the potential VWLL.

The output buffer circuit C14 is configured by connecting p-type MOS transistors PM14 and PM15 and n-type MOS transistors NM14 and NM15 in series.

The source terminal of the p-type MOS transistor PM14 is connected to the supply line of the potential VWLH, and the gate terminal is connected to the p-type MOS transistor of the level conversion circuit C12.
It is connected to the gate terminal of S transistor PM11. The drain terminal of the p-type MOS transistor PM14 is connected to the source terminal of the p-type MOS transistor PM15. The potential VSS is input to the gate terminal of the p-type MOS transistor PM15. For this reason, the p-type MOS transistor PM15 is a normally-on MOS transistor. The drain terminal of the p-type MOS transistor PM15 is connected to the drain terminal of the n-type MOS transistor NM14. From the node between the p-type MOS transistor PM15 and the n-type MOS transistor NM14, a word line WL1,
A voltage for driving WL2 is output.

The potential VCC is supplied to the gate terminal of the n-type MOS transistor NM14. Therefore, n
Type MOS transistor NM14 is a normally on M
It becomes an OS transistor. n-type MOS transistor NM
The source terminal of the n-type MOS transistor NM15
Is connected to the drain terminal. The gate terminal of the n-type MOS transistor NM15 is connected to the level conversion circuit C1.
3 is connected to the gate terminal of the n-type MOS transistor NM13. Also, an n-type MOS transistor N
The source terminal of M15 is connected to the supply line of the potential VWLL.

The row decoder RDEC having the above configuration
And the word line driver WDDV1 to generate the potentials VWLH and VWLL shown in FIG.
Supply to WL2. In FIG. 35C, each MO
Back gate connection is made by S transistor,
This is not necessary.

The output buffer circuit C14 of the word line driver WDDV1 includes normally-on MOS transistors PM15 and NM14, which are directly connected to the MOS transistors PM14 and NM15.
This is for preventing a potential difference between the potential VWLH and the potential VWLL from being applied. That is, normally-on MOS
By the transistors PM15 and NM14, the potential difference is reduced by the voltage for dropping the threshold. Therefore, this potential difference is directly generated by the MOS transistor PM14,
If the voltage can be applied to PM15, the MOS transistors PM15 and NM14 are connected as shown in FIG.
It can be omitted.

The row decoder RDEC and the word line driver WDDV1 shown in FIG. 35C or FIG.
FIG. 35E shows a layout diagram arranged in the memory cell array MCA. As shown in FIG. 35E, the layout pitch of word line driver WDDV1 is
1, if the wiring pitch matches WL2, the row decoder RDEC and the word line driver WDDV1 can be arranged on one side of the memory cell array MCA.

On the other hand, word line driver WDDV
1 has a large layout area, and the word line driver W
The layout pitch of DDV1 is changed to word lines WL1, WL
3 cannot be matched with the wiring pitch of FIG.
A layout as shown in FIG. 5F is conceivable. That is,
Row decoders RDEC are provided on both sides of the memory cell array MCA.
And a word line driver WDDV1, for example, the odd-numbered word line W is provided by the row decoder RDEC and the word line driver WDDV1 on the left side of the memory cell array MCA.
L1 and WL2 are decoded and driven, and the even-numbered word lines WL1 and WL2 are decoded by the row decoder RDEC and the word line driver WDDV1 on the right side of the memory cell array MCA.
Decoding and driving.

Next, the circuit configuration of the row data and word line driver corresponding to FIG. 35A will be described. FIG. 35G shows an example of the row decoder and the word line WL shown in FIG. 35A.
FIG. 1 is a diagram illustrating an example of a word line driver WDDV2 for generating a voltage waveform of WL2.

As shown in FIG. 35G, the row decoder RDEC is constituted by a NAND circuit C10, and the word line driver WDDV2 is connected to the inverter circuit C10.
11, a level conversion circuit C22, and a level conversion circuit C2.
3, an output buffer circuit C24, and a level conversion circuit C2.
5 and an output buffer circuit C26. The relationship between the voltage levels is as follows: VWL1H>VWL2H>VSS>VWL1L> V according to the example of FIG. 35A.
WL2L.

Explaining only the points different from FIG. 35C, the level conversion circuit C22 has basically the same configuration as the level conversion circuit C12 in FIG.
M20, PM21 and n-type MOS transistor NM2
0 and NM21. However, the source terminals of the p-type MOS transistors PM20 and PM21 are connected to the potential VWL.
It is connected to the 1H supply line.

The level conversion circuit C23 is also basically the same as that shown in FIG.
It has the same configuration as the level conversion circuit C13 of C
OS transistors PM22 and PM23 and n-type MOS transistors NM22 and NM23 are provided. However,
Source terminals of the n-type MOS transistors NM22 and NM23 are connected to a supply line for the potential VWL1L.

The output buffer circuit C24 is also basically the same as that shown in FIG.
It has the same configuration as the 5C output buffer circuit C14, and has p-type MOS transistors PM24, PM
M25, n-type MOS transistors NM24, NM25
And However, the p-type MOS transistor PM2
4 is connected to the supply line of the potential VWL1H, and the source terminal of the n-type MOS transistor NM25 is connected to the supply line of the potential VWL1L.

In addition, the word line driver WDDV2 of FIG. 35G includes a level conversion circuit C25 and an output buffer circuit C26. The configuration of the level conversion circuit C25 is the same as the configuration of the level conversion circuit C23,
OS transistors PM26 and PM27 and n-type MOS transistors NM26 and NM27 are provided. However,
Source terminals of the n-type MOS transistors NM26 and NM27 are connected to a supply line for the potential VWL2L.

The output buffer circuit C26 has the same configuration as the output buffer circuit C24, but includes two MOS transistors, a p-type MOS transistor PM28 and an n-type MOS transistor NM28. And
The source terminal of the p-type MOS transistor PM28 is connected to a supply line for the potential VWL2H, and the source terminal of the n-type MOS transistor NM28 is connected to a supply line for the potential VWL2L.

The reason why the normally-on MOS transistor is not inserted is that the potential difference between the potential VWL2H and the potential VWL2L is not so large, as can be seen from FIG. 35A, and this potential difference is directly applied to the MOS transistor P.
This is because no problem occurs even if the voltage is applied to M28 and NM28.

As can be seen from this configuration, the output of output buffer circuit C24 has potential VWL1H and potential VWL1L.
, Whereby the first word line WL1 is driven. The output of the output buffer circuit C26 is
The voltage swings between the potential VWL2H and the potential VWL2L in synchronization with the output of the output buffer circuit C24, whereby the second word line WL2 is driven. In FIG. 35G, the back gate connection is made in each MOS transistor, but this is not always necessary.

As in the case of the word line driver WDDV1 shown in FIG. 35D, the p-type MOS transistor PM25 and the n-type MOS transistor NM24 can be omitted in the word line driver WDDV2 as shown in FIG. 35H. is there.

The row decoder RDEC and the word line driver WDDV2 shown in FIG. 35G or FIG.
FIG. 35I shows a layout diagram arranged in the memory cell array MCA. In the word line driver WDDV2 shown in FIGS. 35G and 35H, the first word line WL1
And the second word line WL2 are driven synchronously at different potentials, the layout area of which is shown in FIGS.
The word line driver WDDV1 shown in FIG. Therefore, it is considered difficult to match the layout pitch of the word line driver WDDV2 with the wiring pitch of the word lines WL1 and WL2. Therefore, in the layout shown in FIG. 35I, the row decoder RDEC and the word line driver WDDV2 are arranged on both sides of the memory cell array MCA. That is, the row decoder RD on the left side of the memory cell array MCA
The EC and the word line driver WDDV2 decode and drive the odd-numbered word lines WL1 and WL2, and the row decoder RDEC and the word line driver WDDV2 on the right side of the memory cell array MCA provide the even-numbered word lines WL1 and WLDD.
Decode and drive WL2.

As shown in FIG. 35J, for example, a word line driver WDDV3 for the first word line WL1 is provided.
May be arranged on the left side of the memory cell array MCA, and the word line driver WDDV4 of the second word line WL2 may be arranged on the right side of the memory cell array MCA.
By arranging in this manner, the arrangement of the power supply wiring can be facilitated. That is, the first word line WL
The potential VWL1H and the potential VWL are located only on the left side of the memory cell array MCA having the one word line driver WDDV3.
1L potential supply line, and a memory cell array M having a word line driver WDDV4 for the second word line WL2.
A potential supply line for the potential VWL2H and the potential VWL2L may be provided only on the right side of CA.

However, in the case of this layout, both the word line driver WDDV3 and the word line driver WDDV4 require separate row decoders RDEC. An example of such a word line driver WDDV3 is shown in FIG. 35K, and an example of the word line driver WDDV4 is shown in FIG. 35L.

As shown in FIG. 35K, the first word line W
The word line driver WDDV3 for L1 includes a level conversion circuit C22 connected to the row decoder RDEC via an inverter circuit C11, a level conversion circuit C23 directly connected to the row decoder RDEC, and an output buffer circuit C
24. These configurations are the same as those shown in FIG.
Of the word line driver WDDV2.

On the other hand, as shown in FIG. 35L, the word line driver WDDV4 for the second word line WL2 includes a row decoder RDEC, an inverter circuit C11, a level conversion circuit C25, and an output buffer circuit C26. It is configured. The configurations of the level conversion circuit C25 and the output buffer circuit C26 are the same as those of the word line driver WDDV2 of FIG. 35G described above. However, the word line driver W
Since the DDV4 is provided on the right side of the memory cell array MCA, the row decoder RDEC is connected to the word line driver W
Since it cannot be shared with the DDV3, a row decoder RDEC and an inverter circuit C11 are independently provided.

Since the row address signals RADD and WLEN are synchronously input to the row decoder RDEC of the word line driver WDDV3 and the row decoder RDEC of the WDD4, as a result, the word lines synchronized with different voltage amplitudes are input. The driving potential is output.

Note that in FIGS. 35K and 35L,
Although a back gate connection is made in each MOS transistor, this is not always necessary. FIG.
The word line driver WDDV3 shown in FIG.
As shown in FIG. 35M, the p-type MOS transistor PM2
5 and the n-type MOS transistor NM24 can be omitted.

[0140]

According to the present invention as described above, according to the present invention, one memory cell is formed by a simple single transistor having a semiconductor layer of floating, it is possible to reduce the cell size and 4F ^2. The source of the transistor is connected to a fixed potential, and only by controlling the bit line connected to the drain and the word line connected to the gate,
Read, rewrite, and refresh are controlled. By providing a second gate facing the channel body of the transistor and providing a high-concentration layer on a surface portion facing the second gate, the second gate is capacitively coupled to the channel body, thereby achieving "0". The difference between the threshold voltages of "1" and "1" data can be increased.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a basic structure of a memory cell according to a basic concept of the present invention.

FIG. 2 is an equivalent circuit of the same memory cell.

FIG. 3 is a layout when a memory cell array of a DRAM is configured using the same memory cell.

FIG. 4A is a sectional view taken along the line A-A 'of FIG. 3;

FIG. 4B is a sectional view taken along line B-B 'of FIG.

FIG. 5 is a diagram showing a relationship between a word line potential and a channel body potential of the same memory cell.

FIG. 6 is a diagram for explaining a reading method of the memory cell.

FIG. 7 is a diagram for explaining another reading method of the memory cell.

FIG. 8 is a diagram showing operation waveforms of “1” data read / refresh of the DRAM.

FIG. 9 is a diagram showing an operation waveform of “0” data read / refresh of the DRAM.

FIG. 10 shows “1” data read / “0” of the DRAM.
FIG. 6 is a diagram illustrating operation waveforms of data writing.

FIG. 11 shows “0” data read / “1” of the same DRAM.
FIG. 6 is a diagram illustrating operation waveforms of data writing.

FIG. 12 shows “1” by another reading method of the DRAM.
FIG. 6 is a diagram showing operation waveforms of data read / refresh.

FIG. 13 shows “0” by another reading method of the DRAM.
FIG. 4 is a diagram showing operation waveforms of data read / refresh.

FIG. 14 shows “1” by another reading method of the DRAM.
FIG. 9 is a diagram showing operation waveforms of data reading / data writing “0”.

FIG. 15 shows “0” by another reading method of the DRAM.
FIG. 9 is a diagram showing operation waveforms of data reading / “1” data writing.

FIG. 16 is a diagram showing a change in channel body potential by a simulation of “0” write / read of the memory cell.

FIG. 17 is a diagram showing a channel body potential change by a simulation of “1” write / read of the same memory cell.

FIG. 18 is a diagram showing a drain current-gate voltage characteristic when reading “0” and “1” data by the same simulation.

FIG. 19A is a sectional view showing the structure of the memory cell according to the first embodiment of the present invention;

19B is a diagram showing an equivalent circuit of a memory cell array in which the memory cells shown in FIG. 19A are arranged in a matrix.

FIG. 19C is a diagram showing a layout of a memory cell array in which the memory cells shown in FIG. 19A are arranged in a matrix.

FIG. 19D is a sectional view taken along the line A-A ′ of FIG. 19C.

FIG. 19E is a sectional view taken along the line B-B ′ of FIG. 19C.

FIG. 19F is a perspective view showing a modification of the memory cell according to the first embodiment.

FIG. 19G is a sectional view taken along the line AA ′ of the memory cell in FIG. 19F.

FIG. 19H is a cross-sectional view of the memory cell of FIG. 19F along the line BB ′.

FIG. 19I is a diagram showing a layout of a memory cell array in which the memory cells shown in FIG. 19F are arranged in a matrix.

FIG. 19J is a sectional view taken along the line A-A ′ of FIG. 19I.

FIG. 19K is a sectional view taken along the line B-B ′ of FIG. 19I.

FIG. 19L is a sectional view taken along the line C-C ′ of FIG. 19I.

FIG. 19M is a perspective view showing another modification of the memory cell according to the first embodiment;

FIG. 19N is a cross-sectional view of the memory cell of FIG. 19M taken along line BB ′.

FIG. 20 is a sectional view showing the structure of the memory cell according to the second embodiment;

FIG. 21 is a plan view of a memory cell array according to a third embodiment.

FIG. 22 is a sectional view taken along line A-A ′ of FIG. 21;

FIG. 23 is a plan view of a memory cell array according to a fourth embodiment.

24 is a sectional view taken along line A-A 'of FIG.

FIG. 25A is a sectional view showing a structure of a memory cell according to a fifth embodiment.

FIG. 25B is a schematic diagram showing a state of the memory cell in the case where a positive potential is applied to the drain region, a positive potential is applied to the gate, and the source region is connected to the ground in the memory cell shown in FIG. 25A. is there.

25C is a schematic diagram showing a state of the memory cell in the case where a negative potential is applied to the drain region, a positive potential is applied to the gate, and the source region is connected to the ground in the memory cell shown in FIG. 25A. is there.

FIG. 26 is a diagram showing characteristics of the memory cell of the embodiment.

FIG. 27 is a sectional view showing a structure of a memory cell according to a sixth embodiment.

FIG. 28 is a sectional view showing another structure of the memory cell according to the sixth embodiment.

FIG. 29A is a plan view of a memory cell array when a gate offset structure is applied to a memory cell having an SGT structure (Embodiment 6).

FIG. 29B is a diagram of A- of the memory cell array according to FIG. 29A;
It is A 'sectional drawing.

FIG. 30A is a plan view of a memory cell array when a gate offset structure is introduced in a third embodiment (Embodiment 6).

FIG. 30B is a diagram showing A- of the memory cell array according to FIG. 30A.
It is A 'sectional drawing.

FIG. 30C is a plan view of a memory cell array in the case where a gate offset structure is introduced in the fourth embodiment (sixth embodiment).

FIG. 30D is a view A- of the memory cell array shown in FIG. 30C;
It is A 'sectional drawing.

FIG. 31 is a characteristic diagram showing a GIDL current of a MISFET (Embodiment 7).

FIG. 32 is an operation waveform diagram of “1” write / read using a GIDL current.

FIG. 33 is a plan view of a memory cell array according to an eighth embodiment.

34A is a sectional view taken along line A-A ′ of FIG. 33.

34B is a sectional view taken along the line B-B ′ of FIG. 33.

FIG. 35A is a waveform chart showing a write operation of a memory cell when a first gate and a second gate are driven synchronously at different potentials (Embodiment 9).

FIG. 35B is a waveform chart showing a write operation of the memory cell in the case where the first gate and the second gate are driven at the same potential (Embodiment 9).

FIG. 35C is a diagram showing an example of a circuit configuration of a word line driver and a row decoder for generating the write operation waveform of FIG. 35B.

FIG. 35D is a diagram showing a modification of the word line driver shown in FIG. 35C.

FIG. 35E is a diagram showing an example of a layout when the row decoder and the word line driver shown in FIG. 35C or 35D are arranged for a memory cell array (one-sided arrangement).

FIG. 35F is a diagram showing an example of a layout when the row decoder and the word line driver shown in FIG. 35C or 35D are arranged for a memory cell array (both sides are arranged).

FIG. 35G is a diagram showing an example of a circuit configuration of a word line driver and a row decoder for generating the write operation waveform of FIG. 35A.

FIG. 35H is a diagram showing a modification of the word line driver shown in FIG. 35G.

FIG. 35I is a diagram showing an example of a layout when the row decoder and the word line driver shown in FIG. 35G or 35H are arranged for a memory cell array (first)
(A case where a row decoder and a word line driver are alternately provided on the left and right sides of a pair of word lines including the word line and the second word line).

FIG. 35J is a diagram showing an example of a layout when the row decoder and the word line driver shown in FIG. 35G or 35H are arranged for a memory cell array (a row decoder for the first word line on one side) And a word line driver, and a row decoder and a word line driver for a second word line on the other side.

FIG. 35K is a diagram showing an example of a circuit configuration of a first word line row decoder and a word line driver when the layout shown in FIG. 35J is adopted.

FIG. 35L is a diagram showing an example of a circuit configuration of a second word line row decoder and a word line driver when the layout shown in FIG. 35J is adopted;

FIG. 35M is a diagram showing a modification of the word line driver shown in FIG. 35K.

[Explanation of symbols]

 Reference Signs List 10 silicon substrate 11 silicon oxide film 12 p-type silicon layer 13 first gate 14 drain diffusion layer 15 source diffusion layer 20 second gate

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme Court II (Reference) G11C 11/34 352C 354D (72) Inventor Takashi Yamada 8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Prefecture Toshiba Yokohama Business Co., Ltd. In-house (72) Inventor Yoshihisa Iwata 1F, Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa F-term (reference) 5F083 AD69 HA02 LA12 LA16 5F110 AA30 BB04 BB06 CC02 CC09 DD05 DD13 EE30 GG02 GG12 GG31 HM14 NN02 5M024 AA58 BB02 BB35 BB36 BB39 CC20 CC22 CC50 CC70 EE10 HH01 LL04 LL05 LL11 PP01 PP02 PP03 PP04 PP07 PP10

Claims (26)

[Claims] 1. A plurality of MISs for forming a memory cell
A semiconductor memory device having a transistor, wherein each M
An IS transistor includes: a semiconductor layer; a source region formed in the semiconductor layer; and a drain region formed in the semiconductor layer apart from the source region, wherein the drain region is formed between the source region and the drain region. A drain region in which the semiconductor layer is a floating channel body; a first gate for forming a channel in the channel body; and a second gate for controlling a potential of the channel body by capacitive coupling. A high-concentration region formed on the second gate side of the channel body, wherein the high-concentration region has an impurity concentration higher than the impurity concentration of the channel body. Channel body first
And a second data state in which the channel body is set to a second potential and a second data state in which the channel body is set to a second potential. 2. The first data state is written by causing the MIS transistor to operate as a pentode, causing impact ionization near the drain junction, and the second data state is written by the first gate from the first gate. 2. The semiconductor memory device according to claim 1, wherein data is written by applying a forward bias between said channel body to which a predetermined potential is applied by capacitive coupling and said drain region. 3. The semiconductor memory device according to claim 1, wherein said first gate and said second gate are formed separately. 4. The MIS transistor according to claim 1, wherein a plurality of MIS transistors are arranged in a matrix, and a drain region of the MIS transistors arranged in a first direction is a bit line, and a first gate of the MIS transistors arranged in a second direction is a first word line. And the MI
The memory cell array is formed by connecting the source region of the S transistor to a fixed potential and connecting the second gates of the MIS transistors arranged in the second direction to a second word line. Item 4. The semiconductor memory device according to item 3. 5. A semiconductor device comprising: a plurality of MIS transistors arranged in a matrix; a drain region of the MIS transistors arranged in a first direction arranged on a bit line; a first gate of the MIS transistors arranged in a second direction arranged on a word line; The source region of the MIS transistor is set to the first fixed potential,
4. The semiconductor memory device according to claim 3, wherein a second gate of the transistor is connected to a second fixed potential as a common plate of all MIS transistors to form a memory cell array. 6. The semiconductor layer is formed on a semiconductor substrate by being separated by an insulating film, and the first gate is continuously arranged as a first word line on the semiconductor layer. And the second gate is provided below the semiconductor layer in a second direction parallel to the first word line.
4. The semiconductor memory device according to claim 3, wherein the word lines are continuously arranged. 7. The semiconductor device, wherein the semiconductor layer is a columnar semiconductor formed on a semiconductor substrate, the first gate is formed to face one side surface of the columnar semiconductor layer, and the second gate Is formed so as to face the high-concentration region formed on the side surface of the columnar semiconductor layer opposite to the first gate, the drain region is on the upper surface of the columnar semiconductor, and the source region is the columnar semiconductor. The semiconductor memory device according to claim 3, wherein the semiconductor memory device is formed below the semiconductor. 8. The semiconductor memory device according to claim 3, wherein said first gate has a positive amount of overlap with said source region and a negative amount of overlap with said drain region. 9. The semiconductor memory device according to claim 5, wherein said first gate has a positive overlapping amount with respect to said source region and a negative overlapping amount with respect to said drain region. 10. The semiconductor memory device according to claim 7, wherein said first gate has a positive overlapping amount with respect to said source region and a negative overlapping amount with respect to said drain region. 11. A driving circuit for driving the first gate and the second gate, wherein the driving circuit drives the second gate in synchronization with a lower potential than the first gate. 4. The semiconductor memory device according to claim 3, further comprising: 12. The semiconductor memory device according to claim 3, further comprising a drive circuit that drives the first gate and the second gate in synchronization with the same potential. 13. The semiconductor memory device according to claim 1, wherein said first gate and said second gate are configured as a common gate formed in common. 14. The semiconductor memory device according to claim 13, wherein said high-concentration region is formed in a part of said common gate side surface of said channel body. 15. The semiconductor memory device according to claim 14, wherein said high concentration region is in contact with said source region and said drain region. 16. The semiconductor memory device according to claim 14, wherein said high concentration region is not in contact with either said source region or said drain region. 17. The semiconductor device according to claim 17, wherein the semiconductor layer is a columnar semiconductor layer formed on a semiconductor substrate, and the common gate is formed so as to surround a periphery of the columnar semiconductor layer. 14. The semiconductor memory device according to claim 13, wherein the high-concentration region is formed on a side surface, the drain region is formed on an upper surface of the columnar semiconductor, and the source region is formed below the columnar semiconductor. 18. The semiconductor memory device according to claim 17, wherein said common gate has a positive overlapping amount with respect to said source region and a negative overlapping amount with respect to said drain region. 19. The semiconductor layer is a convex semiconductor layer formed on a semiconductor substrate, and the common gate is formed so as to face an upper surface and both side surfaces of the convex semiconductor layer. The high-concentration region is formed on one or more side surfaces of the semiconductor layer opposite to the common gate, and the drain region and the source region are formed on the convex semiconductor layer with the common gate interposed therebetween. 14. The semiconductor memory device according to claim 13, wherein: 20. The first data state is written by a drain leakage current induced by the first gate to which a negative potential is applied, and the second data state is a capacitance from the first gate. 2. The semiconductor memory device according to claim 1, wherein writing is performed by applying a forward bias between the semiconductor layer to which a predetermined potential is applied by coupling and the drain region. 3. 21. A plurality of MIs for forming a memory cell.
A semiconductor memory device having an S transistor, wherein each MIS transistor includes a semiconductor layer, a source region formed in the semiconductor layer, and a drain region formed in the semiconductor layer apart from the source region, The MIS transistor, comprising: a drain region in which the semiconductor layer between the source region and the drain region becomes a floating channel body; and a first gate for forming a channel in the channel body. Has different characteristics between a case where a channel current flows from the source region to the drain region and a case where a channel current flows from the drain region to the source region even when the same potential is applied to the first gate. And the MIS transistor has impact ionization near the drain junction. Or a forward bias current is applied between the drain region and the channel body, with a first data state in which the semiconductor layer is set to a first potential by a drain leak current induced by the first gate. And dynamically storing a second data state in which the semiconductor layer is set to a second potential. 22. The semiconductor memory device according to claim 21, wherein the first gate has a positive overlapping amount with respect to the source region, and has a negative overlapping amount with respect to the drain region. 23. In the MIS transistor, even when the same potential is applied to the first gate, the channel current flowing from the drain region to the source region is larger than the channel current flowing from the source region to the drain region. 23. The semiconductor memory device according to claim 22, wherein the number is larger than the number. 24. The MIS transistor according to claim 21, further comprising a second gate for controlling a potential of said channel body by capacitive coupling, separately from said first gate. Semiconductor memory device. 25. The MIS transistor includes a high-concentration region formed on a surface of the channel body on the second gate side and having the same conductivity type as the channel body and having a higher impurity concentration than the semiconductor layer. The semiconductor memory device according to claim 24, further comprising: 26. A semiconductor device comprising a plurality of MIs for forming a memory cell.
A semiconductor memory device having an S transistor, wherein each MIS transistor includes a semiconductor layer, a source region formed in the semiconductor layer, and a drain region formed in the semiconductor layer apart from the source region, The semiconductor layer between the source region and the drain region includes a drain region serving as a floating channel body, and a gate for forming a channel in the channel body. A forward bias is applied between a first data state in which the semiconductor layer is set to a first potential and the drain region and the channel body by flowing a drain leak current induced by applying a negative potential to the semiconductor layer. A current is supplied to dynamically record the second data state in which the channel body is set to the second potential. To, a semiconductor memory device, characterized in that.