JP2002343094A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform a test depending on a data pattern of a memory cell by equalizing data topology of a memory cell before and after redundancy relieving and to suppress increment of chip area. SOLUTION: When a selected address is a redundant memory cell, a selected address is discriminated, when data topology of a normal memory cell and a redundant memory cell are reversed, data topology is written in equal memory cells by reversing one part of a selected row address. Thereby, when a redundancy discriminating signal SP of a redundancy discriminating circuit 4 is 'high' and a row address signal PA2 is high, a row address signal PA1 is reversed by an exclusive OR circuit EXOR1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device having a redundancy repair function.

[0002]

2. Description of the Related Art In semiconductor memory devices, the pitch of metal wirings has become larger than the word line pitch of memory cells as the design rules have become finer. It has become.
Here, for example, consider a word line drive circuit and its layout as shown in FIG. FIG. 1A shows a pattern layout, and FIG. 1B shows a circuit diagram.

In this layout, one main word line is used as a basic unit, and is arranged to be flipped left and right. This is because the source, gate, contact and the like of the active region are shared with the adjacent cells, and the layout area is minimized. In the figure, WL <0>, WL <1>, W
L <2> and WL <3> are four word lines (sub word lines in the case of the hierarchical word line system). MWL <0>, M
WL <1> is two main word lines. SDA, N
SDA, SDB and NSDB are sub-decode signals.

Next, a memory cell array having a configuration as shown in FIG. 2 will be considered. In FIG. 2, BL
0, / BL0, BL1, / BL1, BL2, / BL2
BL3 and / BL3 are bit lines (data lines), WL1 to W
L9 is a word line, and SWL0 to SWL3 are redundant word lines. PA2 is the lower first bit of the address for selecting the main word line (MWL) (lower 3 bits of the row address).
PA1 indicates the upper bit (lower second bit of the row address) of the 2-bit address for selecting the word line (WL), and PA0 indicates the 2-bit address for selecting the word line. (Lower first bit of the row address).

Here, addresses PA2, PA1, PA0
The relationship between each of the above values and the selected word line is shown below.

(PA2, PA1, PA0) = (0, 0, 0) → WL0 (PA2, PA1, PA0) = (0, 0, 1) → WL1 (PA2, PA1, PA0) = (0, 1, 0) → WL2 (PA2, PA1, PA0) = (0, 1, 1) → WL3 (PA2, PA1, PA0) = (1, 1, 0) → WL4 (PA2, PA1, PA0) = (1, 1) , 1) → WL5 (PA2, PA1, PA0) = (1,0,0) → WL6 (PA2, PA1, PA0) = (1,0,1) → WL7 Also, each value of address PA2, PA1, PA0 The relationship between and the selected redundant word line is shown below.

(PA2, PA1, PA0) = (0, 0, 0) → SWL0 (PA2, PA1, PA0) = (0, 0, 1) → SWL1 (PA2, PA1, PA0) = (0, 1, 0) → SWL2 (PA2, PA1, PA0) = (0, 1, 1) → SWL3 Further, in FIG. 2, the marks “○” and “●” represent the memory cells, and the mark “○” indicates the data supplied from the outside. Represents a memory cell to which data is written without changing the data topology, and a solid circle represents a memory cell to which the data topology is inverted and written inside.

One main word line (MWL) allows four word lines (for example, WL0 to WL3, WL4
ＷＬWL7) will be considered. The word line (W) selected depending on whether the lower one bit (lower third bit of the row address) of the address for selecting the main word line (MWL) is low (“0”) or high (“1”).
L) 2nd lower order bit (lower 2nd bit of row address)
Address in the order of four word lines, (high, high,
Consider the case where the configuration is different from (low, low) and (low, low, high, high). The former corresponds to word lines WL4 to WL7, and the latter corresponds to word lines WL0 to WL3.

Here, the redundant word line is (Row, Row,
Assuming that the addresses are arranged in the order of (high, high), in the configuration in which the redundancy is repaired in units of main word lines, the address of the lower 2 bits is (low, low, high,
(High) four word lines, for example, WL0 to WL3 are (low, low, high, high) redundant word lines SWL0 to SWL.
WL3 or in order (high, high,
4), for example, WL4 to WL7
Is the (low, low, high, high) redundant word line SWL
0 to SWL3.

In this case, for example, four word lines WL0 to WL0
When replacing WL3 with the redundant word lines SWL0 to SWL3, the word lines WL0 to WL3 and the redundant word lines SWL0 to SWL3 have the same data topology. However, when replacing the word lines WL4 to WL7 with the redundant word lines SWL0 to SWL3, the word lines WL4 to WL7 and the redundant word lines SWL0 to SWL3 are used.
Is the opposite of the data topology relationship.

Therefore, it is necessary to adopt a configuration in which the topology of the data written in the redundant cell is inverted or not depending on the address to be repaired.

On the inspection device side, scrambling is performed between the logical address and the physical address, and data is written into the memory cells in consideration of the internal arrangement. However, in the post-assembly inspection, since information about the redundant address is not known, when attempting to write a data pattern suitable for screening for defects such as an all-high or all-row or a checker pattern in a memory cell in the inspection, depending on the address, A problem arises in that the data pattern cannot be written as expected, and it cannot be determined from outside. The information on the redundant address is information indicating which address has been replaced with the redundant address.

In order to solve the problem of inversion of the data topology caused by the different addressing as described above, the word line driving circuit changes the connection of the word line after the occurrence at the connection portion with the memory cell array. By doing so, the data topology written in the redundant memory cell has been matched with the data topology of the normal memory cell.

The difference in addressing means that an external address is 0,
1, 2, 3,..., For example, 1, 0, 2,
As in the case of 3,..., This means a case where the way in which the external address advances and the arrangement order of the memory cells are different.

Next, a description will be given of how the connection of the generated word line is changed at the connection portion with the memory cell array. This is not to simply connect the word line activated by the word line drive circuit to the memory cell, but to replace the word line so that the external address and the memory cell address advance in the same way. Means

[0016]

However, in order to solve the problem of inversion of the data topology due to different addressing, a method for reconnecting word lines at a connection portion with a memory cell array requires an area for reconnection. Therefore, there arises a problem that the layout size of the sub-word line driving circuit cannot be minimized. Since the sub-word line drive circuit is disposed at both ends of each memory sub-array, a small increase in the layout size has a large effect on the entire chip, leading to an increase in chip cost.

Accordingly, an object of the present invention is to detect a defect utilizing interference between memory cells in an inspection without causing any inconvenience, and without increasing the chip size and reducing the chip cost. An object of the present invention is to provide a semiconductor memory device capable of suppressing an increase.

[0018]

As a means for solving the above-mentioned problems, a semiconductor memory device according to the first aspect of the present invention includes a memory cell connected to a word line and a bit line in a matrix, and has a redundant structure. A memory cell array including redundant memory cells connected in a matrix to word lines and bit lines, and a plurality of word line drive circuits provided corresponding to each of the word lines, provided in correspondence with each of the redundant word lines A plurality of redundant word line driving circuits, a row address generating circuit for selecting a word line, and a redundancy determining circuit for selecting a redundant word line. 1
The redundant word line is selected by an internal row address obtained by inverting the state of one or a plurality of bits by an inversion means.

As described above, if the data topology of the redundant cell is different when replaced with the redundant memory cell, the data topology can be inverted and written, so that a desired data pattern can be written in the redundant memory cell at the time of inspection. You will be able to write. That is, in the inspection after assembly, even if data is written from an external inspection device without particularly considering the case of redundancy, if the data topology of the redundant cell is different, the data topology is inverted by the circuit system of the present invention. Therefore, the detection of a defect utilizing the interference between the memory cells in the inspection can be performed without causing any inconvenience. In addition, the chip area is hardly increased, and the chip cost can be reduced.

The semiconductor memory device according to the second to eighteenth aspects will be described below. The operation and effect of the invention are the same as those of the first aspect.

A semiconductor memory device according to a second aspect of the present invention includes a memory cell connected to a word line and a bit line in a matrix, and a redundant memory connected to a redundant word line and a bit line in a matrix. A word line driver including a memory cell array including cells and a plurality of respective word line driving circuits provided corresponding to each of the word lines, and including a plurality of respective redundant word line driving circuits provided corresponding to each of the redundant word lines And a row address generating circuit for selecting a word line, and a redundancy determining circuit for selecting a redundant word line. When a redundant memory cell is selected, a plurality of row addresses are replaced with each other by an internal row address. It is characterized in that a line is selected.

A semiconductor memory device according to a third aspect of the present invention includes a memory cell connected to a sub-word line and a bit line in a matrix, and a redundant memory connected to a redundant sub-word line and a bit line in a matrix. A memory cell array including cells, and a plurality of sub-word line driving circuits provided corresponding to each of the sub-word lines;
A sub-word line driving unit including a plurality of redundant sub-word line driving circuits provided corresponding to each of the redundant sub-word lines;
A main word line selection signal generation circuit for generating a main word line selection signal for selecting a main word line connected to the sub word line drive circuit, a row address generation circuit for selecting a sub word line, and a redundancy sub word line A redundancy judgment circuit, wherein a redundancy sub-word line is selected by an internal row address obtained by inverting the state of one or more bits of a row address by an inversion means when a redundant memory cell is selected. is there.

A semiconductor memory device according to a fourth aspect of the present invention includes a memory cell connected to a sub-word line and a bit line in a matrix, and a redundant memory connected to a redundant sub-word line and a bit line in a matrix. A memory cell array including cells, and a plurality of sub-word line driving circuits provided corresponding to each of the sub-word lines;
A sub-word line driving unit including a plurality of redundant sub-word line driving circuits provided corresponding to each of the redundant sub-word lines;
A main word line selection signal generation circuit for generating a main word line selection signal for selecting a main word line connected to the sub word line drive circuit, a row address generation circuit for selecting a sub word line, and a redundancy sub word line A redundancy determining circuit, wherein a redundant sub-word line is selected by an internal row address which has been replaced by a plurality of row addresses when a redundant memory cell is selected.

According to a fifth aspect of the present invention, in the semiconductor memory device according to the first or third aspect, a bit of a row address to be inverted when a redundant memory cell is selected is replaced with a bit of another bit of the row address. Depending on the condition,
It is designed to switch whether or not to reverse.

According to a sixth aspect of the present invention, there is provided the semiconductor memory device according to the second or fourth aspect, wherein a row address to be replaced when a redundant memory cell is selected is determined by a state of a specific bit of the row address. It is made to switch whether to replace.

According to a seventh aspect of the present invention, there is provided the semiconductor memory device according to the first, third or fifth aspect, wherein the redundancy judging circuit comprises one or more of a row address when a redundant memory cell is selected. It has a function of generating an internal row address with inverted bits.

In the semiconductor memory device according to the eighth aspect of the present invention, in the semiconductor memory device according to the second, fourth or sixth aspect, the redundancy determining circuit replaces a plurality of row addresses when a redundant memory cell is selected. It has a function of generating a row address.

A semiconductor memory device according to a ninth aspect of the present invention includes a memory cell connected to a sub-word line and a bit line in a matrix, and a redundant memory connected to a redundant sub-word line and a bit line in a matrix. A memory cell array including cells, and a plurality of sub-word line driving circuits provided corresponding to each of the sub-word lines;
A sub-word line driving unit including a plurality of redundant sub-word line driving circuits provided corresponding to each of the redundant sub-word lines;
A main word line selection signal generation circuit for generating a main word line selection signal for selecting a main word line connected to the sub word line drive circuit, and a sub word line drive signal for the sub word line drive circuit and the redundant sub word line drive circuit A sub-word line driving signal generating circuit, a row address generating circuit for selecting a sub-word line, and a redundancy determining circuit for selecting a redundant sub-word line, wherein a sub-word line driving signal selected when a redundant memory cell is selected is replaced. And a redundant sub-word line is selected.

According to a tenth aspect of the present invention, in the semiconductor memory device according to the ninth aspect, a sub-word line driving signal to be replaced when a redundant memory cell is selected is changed according to a state of a specific bit of a row address. It is designed to switch whether or not to reverse.

A semiconductor memory device according to an eleventh aspect of the present invention includes a memory cell connected to a word line and a bit line in a matrix, and a redundant memory connected to a redundant word line and a bit line in a matrix. A word line driver including a memory cell array including cells and a plurality of respective word line driving circuits provided corresponding to each of the word lines, and including a plurality of respective redundant word line driving circuits provided corresponding to each of the redundant word lines A row address generating circuit for selecting a word line, a row decode circuit for generating a row address decode signal decoded by a row address, and a redundancy determining circuit for selecting a redundant word line. Sometimes, a redundant word line is selected by exchanging a plurality of row address decode signals by an exchange means. And it is characterized in and.

A semiconductor memory device according to a twelfth aspect of the present invention includes a memory cell connected to a sub-word line and a bit line in a matrix, and a redundant memory connected to a redundant sub-word line and a bit line in a matrix. A memory cell array including cells and a plurality of sub-word line driving circuits provided corresponding to each of the sub-word lines, and a sub-word line driving unit including a plurality of redundant sub-word line driving circuits provided corresponding to each of the redundant sub-word lines And a main word line selection signal generation circuit for generating a main word line selection signal for selecting a main word line connected to the sub word line drive circuit; a row address generation circuit for selecting the sub word line; A row decode circuit for generating a row address decode signal; And a redundancy determination circuit for selecting a word line, is characterized in that it has to select the redundant word line replaced by means interchanging a plurality of row address decode signal when the redundant memory cell selection.

According to a thirteenth aspect of the present invention, in the semiconductor memory device according to the first, third, or fifth aspect, the memory cell array is divided into a plurality of memory cell array blocks, and redundancy judgment is performed for each memory cell array block. And a function of determining whether to invert a row address for each memory cell array block.

According to a fourteenth aspect of the present invention, in the semiconductor memory device according to the second, fourth, sixth, or ninth aspect, the memory cell array is divided into a plurality of memory cell array blocks, and the memory cell array is divided into memory cell array block units. A redundancy determination circuit is provided, and has a function of determining whether or not to replace a row address for each memory cell array block.

According to a fifteenth aspect of the present invention, in the semiconductor memory device according to the first, third, or fifth aspect, the memory cell array is divided into a plurality of memory cell array blocks, and a defective memory cell is provided during redundancy repair. It has a function to rescue a defective memory cell by another memory cell array block different from the existing memory cell array block, and determines whether to invert the row address by the selected address memory cell array block and the rescued memory cell array block corresponding to the defective memory cell. Are different.

In the semiconductor memory device according to the present invention, the memory cell array may be divided into a plurality of memory cell array blocks, and the defective memory may be used during redundancy repair. It has a function of relieving a defective memory cell by a memory cell array different from the memory cell array in which the cell exists, and it differs in whether a selected address memory cell array block corresponding to the defective memory cell and a rescued memory cell array block replace a row address.

According to a seventeenth aspect of the present invention, in the semiconductor memory device of the first, second, third, fourth, fifth, or sixth aspect, a mode register which can be set to an inspection mode by a specific input is provided. A specific inspection state is set by a mode register.

A semiconductor memory device according to a eighteenth aspect of the present invention includes a memory cell connected to a word line and a bit line in a matrix, and a redundant memory connected to a redundant word line and a bit line in a matrix. A word line driver including a memory cell array including cells and a plurality of respective word line driving circuits provided corresponding to each of the word lines, and including a plurality of respective redundant word line driving circuits provided corresponding to each of the redundant word lines A row address generating circuit for selecting a word line, a redundancy determining circuit for selecting a redundant word line, a sense amplifier circuit connected to the bit line,
A data line connected to the sense amplifier; and a write driver circuit for driving the data line, wherein when a redundant memory cell is selected, the data on the data line is inverted by one or a plurality of bits of the row address by the inversion means. It is characterized in that it is made to be.

[0038]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 is a block diagram showing a configuration of a semiconductor memory device according to a first embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a memory cell array having redundant memory cells in addition to normal memory cells. Reference numeral 2 denotes a row decoder / word line drive circuit for controlling word lines in the memory cell array 1. Reference numeral 3 denotes an internal address generation circuit having a function of pre-decoding an external address. Reference numeral 4 denotes a redundancy judgment circuit which has a fuse and has a function of judging a defective address.

Next, the operation of this circuit will be described by taking a memory cell array having the configuration shown in FIG. 2 as an example. FIG. 3 shows a truth table of this circuit operation. When PA3, which is the third lower bit of the row address, attempts to replace a high ("1") address with a redundant address, writing is performed without inverting the data topology.
When 2 is high, an internal row address (lower second bit) PA1A is generated by inverting the lower second bit PA1 of the row address. Here, SPE is a redundancy determination signal. When the redundancy determination signal SPE is high, the normal memory cell is replaced with a redundant cell.

Next, FIG. 4 shows a specific example of the internal address generation circuit. When a circuit is created based on the truth table of FIG. 3, it is as follows. That is, the exclusive-OR circuit outputs the signal at the output node of the AND circuit AND1 which takes the logical product of the lower third bit PA2 of the row address and the redundancy determination signal SPE together with the lower second bit PA1 of the row address. By inputting to EXOR1, when PA2, which is the lower third bit of the row address, is high at the time of redundancy, an internal row address signal PA1A that is the inverse of PA1, which is the lower second bit of the row address, can be generated.
The exclusive OR circuit EXOR1 constitutes an inverting means for inverting PA1 which is the second lower bit of the row address.

When not in the redundancy mode, or when the lower third bit PA2 of the row address is low,
The lower second bit PA1 of the row address is output as it is as the internal row address signal PA1A.

With the above configuration, at the time of repair using the redundant memory cells, data can be written to the redundant memory cells without inverting the data topology, regardless of the memory cells to be redundantly repaired. From this, it is possible to perform a test in which the data topology is important, such as checking for a current leak between memory cells during the test, without any problem. In addition, the chip area is hardly increased, and the chip cost can be reduced.

Although the present embodiment describes the hierarchical word line system, similar configurations and effects can be considered for word line driving systems other than the hierarchical word line system.

(Second Embodiment) FIG. 5 is a circuit diagram showing a configuration of a semiconductor memory device according to a second embodiment of the present invention, particularly, a configuration of a redundancy judgment circuit. In FIG. 5, the signal JUDG
E goes high at the time of the redundancy judgment, and is connected to the gate of the n-type transistor QN1. Also, the signal JUDG
A signal XJUDGE which is a complementary signal of E is connected to the gates of two p-type transistors QP1 and QP2.

The address signals PA2, PA1 and PA0 and their complements XPA2, XPA1 and XPA0 are input to the gates of n-type transistors QN2 to QN7 respectively connected to the fuses F1 to F6 of the fuse block FB1.

The opposite terminals of the fuses F2 to F6 connected to the n-type transistors QN3 to QN7 to which signals other than the address signal PA2 are input are commonly connected to the drain of the p-type transistor QP2. The signal at this node becomes the redundancy determination signal SPE. The n-type transistor QN to which the address signal PA2 is input
2 is connected to the drain of the p-type transistor QP1, and the signal at this node is used as the redundancy judgment signal SP of the address signal PA2.
E.

Further, the redundancy judgment signal SPE and the redundancy judgment signal SPA2 of the address signal PA2 are input to the AND circuit AND2, and the output is output as the signal SPEA2.

Next, the operation of this circuit will be described.
When a certain address is selected and all the fuses (one of F1 to F6) corresponding to the address are not cut, the redundancy judgment signal SPE becomes low. However, when all the corresponding fuses (any one of F1 to F6) have been cut, the redundancy determination signal SPE becomes high.

At this time, when the address signal PA2 is high,
When replacing with a redundant memory cell, the signal SPEA2 goes high because the redundancy judgment signal SPA2 of the address signal PA2 goes high. Other than this combination, the signal SPEA2 outputs low.

By inverting the internal row address signals PA1 and XPA1 with the signal SPEA2, specifically, the SPEA2 and PA1 are input to the exclusive OR circuit, and the output is used to specify the address for selecting the word line. , The topology of the data to be written to the redundant memory cell is inverted.

With the above configuration, as in the first embodiment, at the time of repair using the redundant memory cells, regardless of the memory cells to be redundantly repaired, the redundant memory cells can be replaced without inverting the data topology. You will be able to write data. Inspections in which data topology is important, such as checking for current leak between memory cells during inspection, can be performed without any problem.

(Third Embodiment) FIG. 6 is a block diagram showing a configuration of a semiconductor memory device according to a third embodiment of the present invention. In FIG. 6, in the semiconductor memory device, a first word line drive circuit 1 and a second word line drive circuit 2 are arranged at both ends of a memory cell array 11. In this configuration, as in the first embodiment, if four word lines are selected by one main word line, the first and second word line driving circuits 12 and 13 may be used. It is ４ decoded.

More precisely, the first word line drive control signal generation circuit 14 and the second word line drive control signal generation circuit 15 arranged beside the word line drive circuits 12 and 13 have address information. Word line drive control signal SD0
To SD3, decoding is performed.

The control circuit 16 controlled by the internal row address signal PA2 and the redundancy judgment signal SPE
Is input to the first word line drive circuit 12 and the second word line drive circuit 13 via the first word line drive signal generation circuit 14 and the second word line drive signal generation circuit 15. 17 is a sense amplifier.

Next, FIG. 7 shows specific circuits of the first word line drive signal generation circuit 14, the second word line drive signal generation circuit 15, and the control circuit 16, and the circuit operation will be described. The word line WL (a + 4) in FIG.
x) is selected by a signal SDa (where a is 0, 1, 2, or 3 and x is an arbitrary integer).

As in the first embodiment, when replacing a memory cell selected when the internal row address signal PA2 is high with a redundant cell, the data topology can be inverted to make it the same as a normal memory cell. From
First, the control circuit 16 inputs two signals to the AND circuit AND3 to detect the redundant state and the high state of PA2, and outputs the output of the AND circuit AND3 to the first word line drive signal generation circuit 14. And input to the second word line drive signal generation circuit 15.

In word line drive signal generating circuits 14 and 15, predecode signal PSDa of the word line drive control signal is provided.
(a is 0 to 3) and the control signal of the control circuit 16 are input to exclusive OR circuits EXOR2 to EXOR5.

Thus, when the memory cell is replaced with a redundant memory cell, the data topology at the time of redundancy can be inverted by switching the word line drive control signal selected by the internal row address portion PA2. The feature of this circuit is that the sense amplifier 17 and the word line driving circuit 1
The point that all of the intersections sandwiched between 2 and 13 are provided with this circuit.

(Fourth Embodiment) FIG. 8 is a circuit diagram showing a configuration of a semiconductor memory device according to a fourth embodiment of the present invention. In FIG. 8, internal row address signals PA1, P
The output signal of the decoder 21 for decoding A0 is connected to exclusive OR circuits EXOR6 to EXOR9 that generate predecode signals PSD0 to PSD3 of the word line drive signal. The output signal of the AND circuit AND4 to which the internal row address signal PA2 and the redundancy judgment signal SPE are input is the above-described predecode signals PSD0 to PSD.
Exclusive OR circuits EXOR6 to EXO generating 3
It is input to the other gate of R9. The decoder 21 includes inverters IN1 and IN2 and a NAND circuit NAND1.
To NAND4. The exclusive OR circuits EXOR6 to EXOR9 constitute a means for exchanging addresses.

With this configuration, when redundancy is performed and the internal row address signal PA2 is high, the predecode signal of the activated sub-word line drive transistor can replace the internal row address signal PA1. Thereby, when replacing the memory cell of the address where the internal row address signal PA2 is high with the redundant memory cell, the topology of the data to be written is inverted, and an arbitrary data pattern can be written in the inspection. As a result, the same effects as in the first embodiment can be obtained.

(Fifth Embodiment) FIG. 9 is a circuit diagram showing a configuration of a semiconductor memory device according to a fifth embodiment of the present invention. In FIG. 9, reference numeral 31 denotes a NAND circuit NAND5.
To internal NAND address signal PA
1, a decoder for decoding PA0. In this semiconductor memory device, after decoding the internal row address signals PA0 and PA1, the internal decode address is switched by the internal row address signal PA2 when a redundant memory cell is selected. Switching of the internal decode address is performed by the switch 32.
Done by That is, when the redundant memory cell is selected and the internal row address signal PA2 is high, the switch 32 is switched to the cross state, and otherwise, the switch 32 is switched to the straight state.

FIG. 10 is a circuit diagram showing a specific circuit configuration of the switch 32. In FIG. 10, NAND 9
Is a NAND circuit, IN3 is an inverter, and TG1 to TG
4 is an N-type transistor.

Referring to FIG. 10, internal row address signal P
A2 and the redundancy judgment signal SPE are connected to a NAND circuit NAND9.
Has been entered. The output of the NAND circuit NAND9 is input to the inverter IN3 and the transfer gate n-type transistors TG1 and TG2. The output of the inverter IN3 is input to the transfer gate n-type transistors TG3 and TG4.

N-type transistor TG1 is a transfer gate between decode addresses PXPA0PA1 and XPA0PA1, and n-type transistor TG2 is PXPA0PA1.
Transfer gate between 0XPA1 and XPA0XPA1. The n-type transistor TG3 is PXPA0PA
1 and the transfer gate between XPA0 and XPA1, and the n-type transistor TG4 is connected to XPA0XPA1 and XPA0.
Transfer gate between A0PA1.

The signals PPA0PA1, PPA0XP
Although not shown, four n-type transistors having the same configuration as the n-type transistors TG1 to TG4 are provided for switching A1.

The operation of this circuit is such that when the redundancy judgment signal SPE is low, the output of the NAND circuit NAND9 is always high, the n-type transistors TG1 and TG2 are always on, and the n-type transistors TG3 and TG4 are always off. Become.

Next, when the redundancy judgment signal SPE is high, that is, when a redundant memory cell is used, the internal row address signal PA
It depends on the condition of 2. Internal row address signal PA2
Is low, the n-type transistors TG1 and TG2 are turned on, the n-type transistors TG3 and TG4 are turned off, and the decode address is output as it is.

However, when the redundancy judgment signal SPE is high and the internal row address signal PA2 is high, the n-type transistors TG1 and TG2 are off and the n-type transistor TG
3, TG4 is turned on, and the decode address is exchanged between PA1 and XPA1 and output.

With the above configuration, the internal decode address is replaced by the internal row address signal PA2, and the lower second bit of the row address is replaced this time, so that the internal row address signal PA2 is When the memory cell of the high address is redundantly repaired, the lower 2 bits of the row address of the redundant cell are replaced and written. As a result, it is possible to invert and write the data topology.
Therefore, effects similar to those of the above embodiment can be obtained.

(Sixth Embodiment) FIG. 11 is a block diagram showing a configuration of a semiconductor memory device according to a sixth embodiment of the present invention. In FIG. 11, the semiconductor memory device is
In units of memory cell array blocks BLK0 to BLK3,
Redundancy determination / row decoders (including fuses) DEC0 to DEC0 incorporating a redundancy determination circuit as described in the previous embodiment.
It is characterized by having DEC3.

The redundancy judgment circuit is indicated by, for example, reference numeral 41 in FIG. This redundancy judgment circuit 41 has a configuration similar to that of the redundancy judgment circuit shown in FIG. The difference is that the internal row address signal PA2 and other signals are connected to different p-type transistors in FIG. 5, but are connected to the same p-type transistor QP1 in FIG.

In this configuration, in the case where the redundancy determination circuit 41 shown in FIG. 12 performs redundancy determination on an address whose least significant bit of the address for selecting the main word line is "1" at the same time as the redundancy determination, the above-described first address is used. This embodiment is combined with the circuit for inverting the topology of the data to be written into the redundant memory cell as described in the third to third embodiments.

In FIG. 12, in combination with the first embodiment, it is determined whether or not to perform the topology inversion based on the internal row address signal PA2 after the redundancy determination. When the topology inversion is performed, the internal row address signal PA1 is inverted. 1 shows the configuration.

According to this configuration, when replaced by a redundant memory cell, the selected word line drive control signal is switched by the internal row (pre-decode) address signal PA2, thereby lowering the lower two bits of the row address of the redundant memory cell to be written. The bit can be inverted and input.
Thereby, the data topology at the time of redundancy can be inverted. Further, since the redundancy judgment circuit is provided for each memory cell array block, the degree of freedom in changing the memory capacity can be increased.

(Seventh Embodiment) FIG. 13 is a block diagram showing a configuration of a semiconductor memory device according to a seventh embodiment of the present invention. In FIG. 13, each memory cell array BLK
0 to BLK3 include an internal row address and a redundancy determination signal S.
PE0 to SPE3 and a block selection signal SBLK0
To SBLK3 are input.

Here, consider a case where the degree of freedom of redundancy is improved, that is, a case where a defective memory cell can be replaced with a redundant cell of a memory cell array block different from the block where the defective memory cell exists. Further, the memory cell array blocks are not arranged without rotation or inversion, and as shown in FIG. 13, no inversion / rotation (R0) and Y-axis inversion (MY) are alternately arranged. Think about it.

Now, the memory cell array (block) BL
It is assumed that K0 includes a plurality of memory cells that can be repaired in redundancy, including from other blocks. Memory cell array BLK
1 (when PA2 is high) among the redundant memory cells of the memory cell array BLK0,
It is assumed that address 2 is rescued by "0". in this case,
Since the data topology of the memory cell before redundancy and the data topology of the memory cell after redundancy are inverted, the inversion of the data topology by performing address replacement or the like as described in the first to sixth embodiments does not occur. Will be needed.

FIGS. 14A and 14B are specific circuit diagrams of the redundancy judgment circuit. FIG. 7A shows a circuit when SPA2 = 0, and FIG. 7B shows a circuit when SPA2 = 1. EXOR10 and EXOR11 are exclusive OR circuits, and AND5 and AND6 are AND circuits. In the circuit of FIG. 14, not only a fuse for setting a redundant address but also a fuse for setting a memory cell array block are provided, and an n-type transistor is added correspondingly.

When there is a fuse block for each redundant word line, as shown in FIG. 14, whether the address of the lower 2 bits of the word line to be repaired is replaced by the lower 3 bits (PA2 and XPA2) of the row address is determined. Has been determined. Then, depending on the arrangement of the redundant word line, the determination is made based on the redundant address SPA2 as either PA2 or XPA2.

Further, each fuse block has a fuse fuse1 for indicating the arrangement information of the memory cell array.
Is prepared. This is because if the memory cell array block in which redundant memory cells are arranged as described above is different from the memory cell array block to be replaced due to a defect (R0 and MY, for example), the data topology may be inverted. It is.

In the case where SPA2 is low in FIG. 14 as an example, when the arrangement of the memory cell array blocks is different before and after redundancy, fuse fuse1 is cut. By inputting the determination signal of the fuse fuse1 (which is high in this case) and the redundant inversion signal of the row address signal PA2 to the exclusive OR circuit EXOR10, the output of the exclusive OR circuit EXOR10 becomes the row address. This is the same as the inverted signal of the signal PA2. Conversely, if the arrangement of the memory cell array blocks is the same before and after the redundancy, the fuse fuse
1 does not cut. The determination signal of the fuse fuse1 (currently low) and the redundant inverted signal of the row address signal PA2 are input to the exclusive OR circuit EXOR10,
The output of the exclusive OR circuit EXOR10 becomes the same signal as the row address signal PA2.

The same applies to the case where SPA2 is high.

As described above, when redundancy repair is performed in different memory cell array blocks in order to improve the degree of redundancy, the data topology of the redundant memory cell is determined based on the address of the redundant memory cell and the block. By inverting, it becomes possible to perform an inspection in which the data topology of the memory cell is important.
Other effects are similar to those of the previous embodiment.

(Eighth Embodiment) FIG. 15 is a block diagram showing a configuration of a semiconductor memory device according to an eighth embodiment of the present invention. In FIG. 15, reference numeral 1 denotes a memory cell array having redundant memory cells, and reference numeral 2 denotes a row decoder / driver including a row decoder for controlling a word line in the memory cell array 1 and a word line driving circuit. The internal address generating circuit 3 has a function of pre-decoding an external address and applying the pre-decoded to the row decoder / driver 2. The redundancy judgment circuit 4 has a fuse and has a function of judging a defective address. Further, a mode register 5 is provided, the output of which is input to the internal address generating circuit 3.

FIG. 16 is a circuit diagram showing a specific circuit configuration of internal address generating circuit 3. Referring to FIG. In FIG.
D7 is an AND circuit, and the rest is the same as FIG.
In the case of redundancy (redundancy determination signal SPE is high) and internal row address signal PA2 is high, mode register 5
Then, when TE = high is output, an internal row address signal PA1A obtained by inverting the internal row address signal PA1 is output.

With the above configuration, the internal decode address is replaced by the internal row address signal PA2, and the lower second bit of the row address is replaced this time. Therefore, the address of PA2 = 1 is set. When the memory cell is redundantly rewritten, the lower 2 bits of the row address of the redundant cell are replaced and then written.

Further, by selectively using this operation depending on the test mode, the address of the present invention is replaced for a test for detecting a defect related to a memory cell, that is, a test in which the data topology in the memory cell array becomes important. By using the mode, it is possible to use a normal data path at the time of a normal operation or a function test of a memory.

As shown in FIG. 17, test mode signal TE from mode register 5 and redundancy determination signal SPE
Are high, the same effect can be obtained in a configuration in which the decode address is switched according to the state of the internal row address signal PA2. In FIG. 17, AND8 is a logical product circuit, and the rest is the same as FIG.

(Ninth Embodiment) FIG. 18 is a block diagram showing a configuration of a semiconductor memory device according to a ninth embodiment of the present invention. In FIG. 18, reference numeral 1 denotes a memory cell array having redundant memory cells, and reference numeral 2 denotes a row decoder / driver comprising a row decoder for controlling a word line in the memory cell array 1 and a word line driving circuit. The internal address generation circuit 3 has a function of predecoding an external address and applying the predecoded external address to the row decoder / driver 2. The redundancy judgment circuit 4 has a fuse and has a function of judging a defective address. Reference numeral 6 denotes a write driver for writing data to a memory cell. The write driver 6 is controlled by a redundancy judgment signal and a specific row address.

FIG. 19 shows a specific circuit diagram of the write driver. Write data lines DLW0, DLW1,.
Are input to exclusive OR circuits EXOR12 to EXOR14. The exclusive OR circuit EXOR12
To EXOR14 are output as write global data lines GIOW0, GIOW2,. The exclusive OR circuits EXOR12 to EXOR14
The other input of the AND circuit AND receives the row-related redundancy determination signal SPER and the internal row address signal PA2.
This is the output of D9. 7 is a control circuit.

The configuration of the memory cell array will be described in which the data topology of the redundant cell needs to be inverted when the internal row address signal PA2 is high or low as shown in FIG. When a row-type redundant cell is used (SPE
When R = high) and the internal row address signal PA2 is high, the data topology of the redundant memory cell needs to be inverted from that of the normal memory cell. Therefore, the write data line and the row-related redundancy determination signal SP
ER and the internal row address signal PA2 are ANDed with the AND circuit AN.
D9, and output the exclusive OR circuit EXOR1
2 to EXOR14, and the AND circuit AND
When the output of 9 is high, the value of the data bus can be inverted and input.

Further, similarly to the eighth embodiment, there may be a case where this embodiment is applied only in the test mode.

[0094]

As described above, inverting the data topology from that of a normal memory cell when it is replaced by a redundant memory cell is performed by determining the internal address at the time of redundancy, for example, by writing the lower 2 bits of the redundant address. This is realized by inverting the eyes, so that a desired data pattern can be written to the redundant memory cell at the time of inspection. That is, when the accessed memory cell is replaced by a redundant cell and the data topology needs to be inverted before and after the replacement, the present invention can automatically determine the inversion / non-inversion and write the data internally. As a result, it is possible to execute the detection of a defect utilizing interference between memory cells in the inspection without giving any inconvenience. Further, since the layout of the word line driving circuit can be minimized, cost reduction can be realized by reducing the chip size.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a main part of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a schematic diagram showing a configuration of a memory cell array according to a conventional technique and a first embodiment of the present invention.

FIG. 3 is a truth table illustrating an operation of the semiconductor memory device according to the first embodiment of the present invention.

FIG. 4 is a circuit diagram showing a configuration of a main part of the semiconductor memory device according to the first embodiment of the present invention;

FIG. 5 is a circuit diagram showing a configuration of a main part of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration of a main part of a semiconductor memory device according to a third embodiment of the present invention.

FIG. 7 is a circuit diagram showing a configuration of a main part of a semiconductor memory device according to a third embodiment of the present invention.

FIG. 8 is a circuit diagram showing a configuration of a main part of a semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 9 is a circuit diagram showing a configuration of a main part of a semiconductor memory device according to a fifth embodiment of the present invention.

FIG. 10 is a circuit diagram showing a configuration of a main part of a semiconductor memory device according to a fifth embodiment of the present invention.

FIG. 11 is a block diagram showing a configuration of a main part of a semiconductor memory device according to a sixth embodiment of the present invention.

FIG. 12 is a circuit diagram showing a configuration of a main part of a semiconductor memory device according to a sixth embodiment of the present invention.

FIG. 13 is a block diagram showing a configuration of a main part of a semiconductor memory device according to a seventh embodiment of the present invention.

FIG. 14 is a circuit diagram showing a configuration of a main part of a semiconductor memory device according to a seventh embodiment of the present invention.

FIG. 15 is a block diagram showing a configuration of a main part of a semiconductor memory device according to an eighth embodiment of the present invention.

FIG. 16 is a circuit diagram showing a configuration of a main part of a semiconductor memory device according to an eighth embodiment of the present invention.

FIG. 17 is a circuit diagram showing a configuration of a main part of a semiconductor memory device according to an eighth embodiment of the present invention.

FIG. 18 is a block diagram showing a configuration of a main part of a semiconductor memory device according to a ninth embodiment of the present invention.

FIG. 19 is a circuit diagram showing a configuration of a main part of a semiconductor memory device according to a ninth embodiment of the present invention.

20A is a layout diagram showing a conventional technique of a semiconductor memory device, and FIG. 20B is a circuit diagram thereof.

[Explanation of symbols]

 Reference Signs List 1 memory cell array 2 row decoder / driver 3 internal address generation circuit 4 redundancy judgment circuit 5 mode register 6 write driver 7 control circuit 11 memory cell array 12 first word line drive circuit 13 second word line drive circuit 14 first word line drive signal Generation circuit 15 Second word line drive signal generation circuit 16 Control circuit 17 Sense amplifier

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 27/10 481 H01L 27/10 681F 27/108 F-term (Reference) 5B015 HH01 HH03 JJ14 JJ31 KA23 KA24 KA28 KB52 MM09 NN09 PP01 PP06 RR01 RR06 5F083 AD00 BS00 LA01 LA05 ZA10 5L106 CC02 CC08 CC13 CC16 CC17 CC21 CC32 DD12 DD25 EE02 FF04 FF05 GG05 5M024 AA23 AA58 AA75 BB07 BB10 BB35 BB36 CC22 MM35 DD30 MMDD PP02 PP03 PP04 PP10 QQ02

Claims (18)

[Claims] 1. A memory cell array including memory cells connected to a word line and a bit line in a matrix, and including a redundant word line and a redundant memory cell connected to the bit line in a matrix, and each of the word lines A word line drive unit including a plurality of each word line drive circuits provided corresponding to each of the plurality of redundant word line drive circuits provided corresponding to each of the redundant word lines; and a row address for selecting the word line. A generation circuit; and a redundancy judgment circuit for selecting the redundancy word line, wherein the redundancy word line is inverted by an internal row address obtained by inverting the state of one or more bits of the row address when the redundancy memory cell is selected. A semiconductor memory device characterized by being selected. 2. A memory cell array including a memory cell connected to a word line and a bit line in a matrix, and including a redundant word line and a redundant memory cell connected to the bit line in a matrix, and each of the word lines A word line drive unit including a plurality of each word line drive circuits provided corresponding to each of the plurality of redundant word line drive circuits provided corresponding to each of the redundant word lines; and a row address for selecting the word line. A generating circuit, and a redundancy determining circuit for selecting the redundant word line, wherein the redundant word line is selected by an internal row address obtained by replacing a plurality of row addresses with each other when the redundant memory cell is selected. A semiconductor memory device characterized by the following. 3. A memory cell array including memory cells connected to a sub-word line and a bit line in a matrix, and including a redundant sub-word line and a redundant memory cell connected to the bit line in a matrix, and each of the sub-word lines A plurality of sub-word line driving circuits provided corresponding to each of the sub-word line driving circuits, each including a plurality of each of the redundant sub-word line driving circuits provided corresponding to each of the redundant sub-word lines; and A main word line selection signal generation circuit for generating a main word line selection signal for selecting a main word line to be selected, a row address generation circuit for selecting the sub word line, and a redundancy judgment circuit for selecting the redundant sub word line. One or more bits of a row address when the redundant memory cell is selected The semiconductor memory device being characterized in that so as to select the redundant word line by an internal row address by inverting the state. 4. A memory cell array including memory cells connected to a sub word line and a bit line in a matrix, and including a redundant sub word line and a redundant memory cell connected to the bit line in a matrix, and each of the sub word lines A plurality of sub-word line driving circuits provided corresponding to each of the sub-word line driving circuits, each including a plurality of each of the redundant sub-word line driving circuits provided corresponding to each of the redundant sub-word lines; and A main word line selection signal generation circuit for generating a main word line selection signal for selecting a main word line to be selected, a row address generation circuit for selecting the sub word line, and a redundancy judgment circuit for selecting the redundant sub word line. A plurality of row addresses are exchanged with each other when the redundant memory cell is selected. The semiconductor memory device being characterized in that so as to select the redundant word line by parts row address. 5. The method according to claim 1, wherein a bit of a row address to be inverted when the redundant memory cell is selected is switched according to a state of another bit of the row address. Semiconductor storage device. 6. The semiconductor memory device according to claim 2, wherein whether or not a row address to be replaced when said redundant memory cell is selected is switched according to a state of a specific bit of said row address. 7. The redundancy judgment circuit according to claim 1, wherein said redundancy judgment circuit has a function of generating an internal row address obtained by inverting one or more bits of a row address when said redundancy memory cell is selected. 6. The semiconductor memory device according to 5. 8. The semiconductor memory device according to claim 2, wherein said redundancy judgment circuit has a function of generating an internal row address in which a plurality of row addresses are exchanged when said redundant memory cell is selected. . 9. A memory cell array including memory cells connected to a sub-word line and a bit line in a matrix, and including a redundant sub-word line and a redundant memory cell connected to the bit line in a matrix, and each of the sub-word lines A plurality of sub-word line driving circuits provided corresponding to each of the sub-word line driving circuits, each including a plurality of each of the redundant sub-word line driving circuits provided corresponding to each of the redundant sub-word lines; and Main word line selection signal generation circuit for generating a main word line selection signal for selecting a main word line to be selected, and a sub word line drive signal for generating a sub word line drive signal applied to the sub word line drive circuit and the redundant sub word line drive circuit A generation circuit, and a row address generation for selecting the sub-word line And a redundancy determination circuit for selecting the redundant sub-word line, wherein the redundant sub-word line is selected by exchanging a sub-word line drive signal selected when the redundant memory cell is selected. Semiconductor storage device. 10. The semiconductor memory device according to claim 9, wherein whether or not the sub-word line drive signal to be replaced when the redundant memory cell is selected is inverted depending on the state of a specific bit of a row address. 11. A memory cell array including memory cells connected in a matrix to word lines and bit lines, and including redundant memory cells connected in a matrix to said bit lines, and each of said word lines A word line drive section including a plurality of each word line drive circuits provided corresponding to each of the plurality of redundant word line drive circuits provided corresponding to each of the redundant word lines; and a row address for selecting the word line. A plurality of row address decode circuits when the redundant memory cell is selected, comprising: a generation circuit; a row decode circuit that generates a row address decode signal decoded by the row address; Wherein the redundant word line is selected by exchanging signals. . 12. A memory cell array including memory cells connected to a sub-word line and a bit line in a matrix, including a redundant sub-word line and a redundant memory cell connected to the bit line in a matrix, and each of the sub-word lines A sub-word line drive unit including a plurality of sub-word line drive circuits provided corresponding to the plurality of sub-word line drive circuits, and a plurality of redundant sub-word line drive circuits provided corresponding to each of the redundant sub-word lines; A main word line selection signal for generating a main word line selection signal for selecting a main word line, a row address generation circuit for selecting the sub word line, and a row address decode signal decoded by the row address Selecting a row decode circuit and the redundant sub-word line The semiconductor memory device and a redundancy determination circuit, is characterized in that so as to select the redundant word lines replace the plurality of row address decode signal when said redundant memory cell selection for. 13. The memory cell array is divided into a plurality of memory cell array blocks, includes the redundancy judgment circuit for each of the memory cell array blocks, and has a function of judging whether to invert a row address for each of the memory cell array blocks. The semiconductor memory device according to claim 1, 3 or 5, wherein: 14. The memory cell array according to claim 1, wherein the memory cell array is divided into a plurality of memory cell array blocks, the redundancy judgment circuit is provided for each of the memory cell array blocks, and a function of judging whether to replace a row address for each of the memory cell array blocks is provided. Claims 2 and 4,
10. The semiconductor memory device according to 6 or 9. 15. The memory cell array is divided into a plurality of memory cell array blocks, and has a function of relieving the defective memory cell by another memory cell array block different from the memory cell array block in which the defective memory cell exists at the time of redundancy rescue. 6. The semiconductor memory device according to claim 1, wherein whether a row address is inverted is different depending on a selected address memory cell array block corresponding to the defective memory cell and a repaired memory cell array block. 16. The memory cell array according to claim 1, wherein said memory cell array is divided into a plurality of memory cell array blocks and has a function of relieving said defective memory cell by a memory cell array different from a memory cell array in which a defective memory cell exists at the time of redundancy rescue. 10. The semiconductor memory device according to claim 2, wherein whether a row address is replaced is different depending on a selected address memory cell array block and a relief memory cell array block corresponding to the above. 17. The apparatus according to claim 1, further comprising a mode register capable of setting an inspection mode by a specific input, wherein a specific inspection state is set by said mode register. Semiconductor storage device. 18. A memory cell array including memory cells connected to a word line and a bit line in a matrix, and including a redundant word line and a redundant memory cell connected to the bit line in a matrix, and each of the word lines A word line drive section including a plurality of each word line drive circuits provided corresponding to each of the plurality of redundant word line drive circuits provided corresponding to each of the redundant word lines; and a row address for selecting the word line. A generation circuit; a redundancy determination circuit for selecting the redundant word line; a sense amplifier circuit connected to the bit line; a data line connected to the sense amplifier; and a write for driving the data line. A driver circuit, and when the redundant memory cell is selected, one or more bits of a row address The semiconductor memory device being characterized in that the data line so as to invert.