JP2002341845A - Image display device, image display method, and control program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To display a plurality of images from one arbitrary image supply source in parallel by easy operation. SOLUTION: An image which is supplied from a prescribed image supply source and is displayed on a display screen at present is taken into an image memory in response to operation of a prescribed switch, and the taken-in image and images which are successively supplied from the prescribed image supply source after operation of the switch are displayed on the display screen in parallel.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display control technique, and more particularly to an image display control technique suitable for making a presentation.

[0002]

2. Description of the Related Art In a conventional presentation format, a presentation material is stored in an OHP (Overhead Project).
r) In general, the sheet was processed into a sheet and enlarged and projected by an OHP. In the form of this presentation, the explanation is made while sequentially projecting the prepared OHP sheets, and for the sake of explanation, if it is desired to simultaneously display the prepared OHP sheets in another order, the purpose and The simultaneous display can be realized by arranging the OHP sheets to be displayed, which is a very effective method for giving a presentation.

[0003] In recent years, the form of directly displaying personal computer data and the like using an image display device such as a liquid crystal projector capable of displaying a large screen has been increasing. In this form, the presentation material can be displayed as it is, without processing the presentation material into a sheet form such as OHP, and the presentation material can be created by the application software of the personal computer. So very convenient.

FIG. 6 is a block diagram showing a signal processing circuit of a conventional dot matrix type image display device. The signal processing circuit comprises an AD converter 10 and a dot clock reproducing unit 1.
1, scan converter 20, image memory 21, read clock generation unit 22, conversion circuit 30, image display unit 40,
It has a control unit 50 and an operation unit 60.

[0005] A dot clock reproducing unit 11 reproduces a dot clock from the input horizontal synchronizing signal 2, and the input image signal 1 is converted into a digital signal by the AD converter 10 using the dot clock. The digitally converted image signal is temporarily stored in the image memory 21 via the reduction interpolation processing unit 20a of the scan converter 20 according to the dot clock. The image signal once stored in the image memory 21 is read via the enlargement interpolation processing unit 20b of the scan converter 20 according to the read clock.

[0006] Through this series of processing, scan conversion is performed to convert the resolution of the input image so as to match the resolution of the image display unit (included in the image display unit 40) at the output destination. The scan-converted image signal is converted by the conversion circuit 30 into a signal suitable for display on the image display unit, and then output to the image display unit 40 and displayed on the image display unit. In such a configuration, while the writing of the input image to the image memory 21 is stopped, the image memory 2
Displaying the image data in 1 indicates that the display screen has been frozen.

FIG. 7 is a block diagram showing a signal processing circuit of a dot matrix type image display device having a so-called picture-in-picture function for simultaneously displaying images input from a plurality of image sources. An AD converter 12 and a dot clock reproducing unit 1
3, a scan converter 23, an image memory 24, a read clock generator 25 are added, and a conversion circuit 30
, A composition conversion circuit 31 is provided.

That is, this signal processing circuit has two systems of AD converters 10 and 12, scan converters 20 and 23, and image memories 21 and 24 corresponding to two inputs. The signals 1 and 3 are input to the synthesis conversion circuit 31 after being subjected to digital conversion and scan conversion processing. After the screen is synthesized by the synthesis conversion circuit 31 and converted into a signal suitable for display by the image display unit, the signal is output to the image display unit 40 and displayed by the image display unit.

With this configuration, it is possible to simultaneously display images from two different image sources, but it is not possible to capture a plurality of images from the same image source and display them in parallel.

As described above, a plurality of images from the same image source cannot be displayed in parallel in terms of hardware. However, when displaying images on a personal computer, "new window is opened" by the function of application software. Open ",
By further “aligning”, as shown in FIG.
It was possible to display multiple images from the same image source in parallel.

[0011]

However, as described above, a plurality of images from the same application software (same image supply source) can be obtained by "opening a new window" and "arranging" by the function of the application software. Are displayed in parallel in parallel with the mouse operation, the procedure is complicated, and it depends on the function of the application software itself.

A DVD (Digital Video)
o In the case of displaying images without using the application software of a personal computer such as an image source such as Disk),
There has been no method for displaying a plurality of images on the image source (image recording medium) in parallel.

SUMMARY OF THE INVENTION The present invention has been made in view of such problems of the prior art, and a problem thereof is to enable a plurality of images from the same arbitrary image source to be displayed in parallel with a simple operation. It is in.

[0014]

In order to solve the above-mentioned problems, an image display apparatus according to the present invention operates an image supplied from a predetermined image source and currently displayed on a display screen by operating a predetermined operation means. Capturing means for capturing in response to the image, and displaying the image captured by the capturing means and an image sequentially supplied from the predetermined image source after the operation of the operation means in parallel on the display screen. Control means.

[0015] The image display method according to the present invention further comprises a capturing step of capturing an image supplied from a predetermined image source and currently displayed on a display screen in response to an operation of a predetermined operation means. A display control step of displaying, on the display screen, an image captured in the capturing step and an image sequentially supplied from the predetermined image supply source after the operation of the operation unit.

The control program according to the present invention captures an image supplied from a predetermined image supply source and currently displayed on a display screen in response to an operation of a predetermined operation means. After the operation of the operating means, the image sequentially supplied from the predetermined image supply source is displayed in parallel on the display screen.

[0017]

Embodiments of the present invention will be described below in detail with reference to the drawings.

[First Embodiment] FIG. 1 shows a first embodiment of the present invention.
It is a block diagram showing a schematic structure of an image display device concerning an embodiment.

In FIG. 1, 5 is an input digital image signal, 6 is an input dot clock, 20 and 23 are scan converters, 21 and 24 are image memories, 22 and 25 are read clock generators, 31 is a synthesis conversion circuit, 40 Denotes an image display unit, 50 denotes a control unit, and 60 denotes an operation unit.

The scan converter 20 has a reduction interpolation processing circuit 20a and an enlargement interpolation processing circuit 20b, and the scan converter 23 has a reduction interpolation processing circuit 23a and an enlargement interpolation processing circuit 23b. Further, the control unit 50
It has a PU 50a, a ROM 50b, and a RAM 50c, and the CPU 50a performs image display processing and the like corresponding to the flowchart shown in FIG. 2 based on a control program stored in the ROM 50b. At this time, the CPU 50a
Uses the RAM 50c as a work area or the like.

Next, the operation when the normal image display processing is performed will be described. When performing a normal image display process, the scan converter 23 and the image memory 24 are used.
Does not particularly work.

The input digital image signal 5 is input to the scan converter 20 according to the input dot clock 6. The image signal input as a digital signal may be an image signal obtained by digitally converting an analog signal by an AD converter in a previous stage. In this case, the AD conversion clock is reproduced by the dot clock reproducing unit from the horizontal synchronization signal, and the reproduced dot clock becomes the input dot clock 6.

The scan converter 20 temporarily stores the input digital image signal 5 in the image memory 21 via the reduction interpolation processing circuit 20a. At this time, when the input digital image signal 5 is reduced and displayed on a display unit (included in the image display unit 40), the input digital image signal 5 is reduced by the reduction interpolation processing circuit 20a and then stored in the image memory 21. Store.

Then, the input digital image signal 5 stored in the image memory 21 is read based on the read clock generated by the read clock generator 22, and is input to the synthesis conversion circuit 31 via the enlargement interpolation processing circuit 20b. At this time, when the input digital image signal 5 is enlarged and displayed on the display unit, the input digital image signal 5 is enlarged by the enlargement interpolation processing circuit 20b and input to the synthesis conversion circuit 31.

As described above, the reduction interpolation processing circuit 20a of the scan converter 20 or the enlargement interpolation processing circuit 20b
By performing reduction processing or enlargement processing,
Scan conversion will be performed. For example, if the resolution of the input digital image signal 5 is SVGA (800 × 60
0) and the resolution of the image display unit is XGA (1024 ×
768), the input digital image signal 5
Is stored in the image memory 21 at the resolution of SVGA, read out by the read clock, and X is output by the enlargement interpolation processing circuit 20b.
Enlarge and convert to GA resolution.

Conversely, if the resolution of the input digital image signal 5 is XGA (1024 × 768) and the resolution of the image display unit is SVGA (800 × 600),
The input digital image signal 5 is reduced and converted to the resolution of SVGA by the reduction interpolation processing circuit 20a, stored in the image memory 2, and read with the read clock at the resolution of SVGA.
Of course, if neither reduction nor enlargement is required, there is no need to perform the above scan conversion.

The scan-converted digital image signal is converted by the synthesizing conversion circuit 3 into a signal format suitable for display on the image display unit 40,
0 is output and displayed.

Next, an image display process unique to the first embodiment will be described with reference to a flowchart shown in FIG.

The input digital image signal 5 is input to the scan converter 20 in accordance with the input dot clock 6 and is also input to the scan converter 23.

When an instruction to capture a screen is issued from the operation unit 60 (step S11), the control unit 50 issues control signals to the scan converters 20, 23 and the synthesizing conversion circuit 31. The scan converters 20 and 23 have a screen size for displaying the signal 5 in a half display area of the image display unit.
Are respectively set (step S12).

Then, the control section 50 outputs a chip select signal to the image memory 24, thereby enabling the input digital image signal 5 to be written into the image memory 24 (step S13). Note that the chip select signal given to the image memory 24 is a pulse signal, and the input digital image signal 5 is written into the image memory 24 only when the chip select signal as this pulse signal is input. On the other hand, the pulse-like chip select signal as described above is not supplied to the image memory 21. For example, a chip select signal that enables the image memory 21 to be constantly accessed when the power is turned on is supplied.

Next, the control unit 50 controls the synthesizing conversion circuit 31, and as shown in FIG.
The output image (screen A) from the second scan converter 23 is displayed on the left (or right) display area of the image display unit, and the output image (screen B) from the second scan converter 23 is displayed on the right (or left) display area of the image display unit. And converts the synthesized image signal into a signal format suitable for input to the image display unit 40 (step S1).
4). Then, the image signal synthesized and converted by the synthesis conversion circuit 31 is output to the image display unit 40 and displayed.

When the instruction to capture the screen is released from the operation unit 60 (step S11), the control unit 50 sets the screen size of the scan converter 20 to the normal screen display size so that the captured image and the main stream can be displayed. The parallel display with the image is released (step S15), and step S1 is performed.
Proceed to 4.

By such processing, in response to an instruction from the operation unit 60, the display image at the time of the instruction is captured and displayed in parallel with the main image. That is, as shown in the middle part of FIG. 3, the display image (screen B) at the time of operating the operation unit 60 is fixedly displayed, for example, on the right side of the display screen, and the image (screen B) input thereafter is displayed. A) is sequentially displayed on the left side of the display screen, for example.

Therefore, the operation section 60 is constituted by, for example, a mechanical switch, and this switch is provided on the front surface of the image display device, that is, on the same surface as the surface on which the display screen on the housing of the image display device is formed. By arranging them, simply turning on the switch when a desired image is displayed allows the desired image to be displayed in a fixed manner and subsequent input images from the same input source to be sequentially displayed in parallel. It becomes possible.

The input images from the same input source include an image generated by the same application software,
Examples include images recorded on the same image recording medium such as a DVD. In this case, since the image display device has the above-described scan conversion function and synthesis conversion function, the type of the input image signal is not limited and has general versatility.

[Second Embodiment] FIG. 4 shows a second embodiment of the present invention.
It is a block diagram showing a schematic structure of an image display device concerning an embodiment. The present image display device is a dot matrix type image display device having a so-called picture-in-picture function, which simultaneously displays images from a plurality of input sources, according to the first embodiment shown in FIG. The image display device has a configuration in which a first switch 70, a second switch 71, an input digital image signal 7, and an input dot clock 8 are added.

Next, the operation of the second embodiment when a normal image display is performed will be described.

When a normal image display is performed, the first and second switches 70 and 71 are connected to the input digital image signal 7 and the input dot clock 8, respectively. The input image signal 7 is sent to the scan converter 20 according to the input dot clock 6.
Is input to the second scan converter 23 according to the input dot clock 8. Here, the image signal input as a digital signal may be a signal obtained by digitally converting an analog signal by an AD converter in a preceding stage. in this case,
The AD conversion clock is reproduced from the horizontal synchronization signal by the dot clock reproducing unit, and the reproduced dot clocks become the input dot clocks 6 and 8, respectively.

The scan converters 20 and 23 include reduction interpolation processing circuits 20a and 23a and enlargement interpolation processing circuits 20b and 23b, respectively.
The image data is temporarily stored in the image memories 21 and 24 via 23a. At this time, when the input digital image signals 5, 7 are reduced and displayed on a display unit (included in the image display unit 40), the input digital image signals 5, 7 are reduced by the reduction interpolation processing circuits 20a, 23a. After that, they are stored in the image memories 21 and 24.

Then, the input digital image signals 5 and 7 stored in the image memories 21 and 24 are read out based on the read clocks generated by the read clock generators 22 and 25, and synthesized via the enlargement interpolation processing circuits 20b and 23b. Input to the conversion circuit 31. At this time, when the input digital image signals 5 and 7 are enlarged and displayed on the display unit, they are enlarged by the enlargement interpolation processing circuits 20b and 23b and input to the synthesis conversion circuit 31.

As described above, the reduction interpolation processing circuits 20a, 2
3a, the reduction processing or the enlargement interpolation processing circuit 20
By performing the enlargement process by b and 23b, scan conversion is performed. For example, the resolution of the input digital image signals 5 and 7 is SVGA (800 × 600) and the resolution of the image display unit is XGA (1024 × 76).
8), the input digital image signals 5, 7
Is stored in the image memories 21 and 24 at the resolution of SVGA,
At the same time as reading by the read clock, the enlargement interpolation processing circuit 20
b, 23b, the image is enlarged and converted to the XGA resolution.

Conversely, if the resolution of the input digital image signals 5, 7 is XGA (1024 × 768) and the resolution of the image display unit is SVGA (800 × 600), the input digital image signals 5, 7 are reduced and interpolated. The processing circuits 20a and 23a reduce and convert the resolution to the SVGA resolution and store it in the image memories 21 and 24.
Read at the same resolution. Of course, if neither reduction nor enlargement is required, there is no need to perform the above scan conversion.

The synthesis conversion circuit 31 selects one of the digital image signals scanned and converted by the scan converters 20 and 23, and converts the digital image signal into a signal format suitable for displaying on the image display unit 40, or Combine the digital image signals scanned and converted by the scan converters 20 and 23 into one screen,
The signal is converted into a signal format suitable for displaying on the image display unit 40.

In the case of performing composite display in this manner, the scan converters 20 and 23 display the input digital image signals 5 and 7 in two divided display areas of the image display unit, respectively, or use one of them as a main screen. The image size is set so that one is displayed as a child screen. The output signal from the synthesis conversion circuit 31 is input to the image display unit 40 and displayed as an image.

Next, an operation specific to the second embodiment will be described with reference to a flowchart shown in FIG.

When a screen capture instruction is issued from the operation unit 60 (step S21), the control unit 50 switches the switch 7
0, 71, the control signals are sequentially output to the scan converters 20, 23, and the synthesis conversion circuit 31. That is, the control unit 50
First, a connection switching signal is output to the switches 70 and 71 to connect them to the input digital image signal 5 and the input dot clock 6, respectively (step S22).

Next, the control unit 50 outputs a screen size setting signal to the scan converters 20 and 23, and controls the scan converters 20 and 23 so that the screen size is such that the input digital image signal 5 is displayed in half of the image display unit. It is set (step S23).

Then, the control section 50 outputs a chip select signal to the image memory 24, thereby enabling the input digital image signal 5 to be written into the image memory 24 (step S24). Note that the chip select signal given to the image memory 24 is a pulse signal, and the input digital image signal 5 is written into the image memory 24 only when the chip select signal as this pulse signal is input. On the other hand, the image memory 21 is not supplied with the above-described pulse-shaped chip select signal, but is supplied with a chip select signal that makes the image memory 21 always accessible after the operation unit 60 is operated, for example. .

Next, the control unit 50 controls the synthesizing conversion circuit 31, and as shown in FIG.
The output image (screen A) from the image display unit is synthesized on the left (or right) of the image display unit, and the output image (screen B) from the scan converter 23 is synthesized on the right (or left) of the image display unit. The composite image signal is converted into a signal format suitable for input to the image display unit 40 (step S25). Then, the synthesis conversion circuit 3
The image signal synthesized and converted in step 1 is output to the image display unit 40 and displayed.

When the instruction to capture the screen is released from the operation unit 60 (step S21), the control unit 50 connects the switches 70 and 71 to the input image signal 7 and the input dot clock 8, respectively (step S21). S26),
By setting the screen size of the scan converters 20 and 23 to the normal screen display size, the parallel display of the captured image and the main stream image is released (step S27), and the process proceeds to step S25.

By such processing, in response to an instruction from the operation unit 60, the image related to the input digital image signal 5 displayed at the time of the instruction is captured, and the mainstream image related to the input digital image signal 5 is acquired. Is displayed in parallel with.
That is, as shown in the middle part of FIG. 3, a display image (screen B: a captured image related to the input digital image signal 5) at the time of operating the operation unit 60 is fixedly displayed on the right side of the display screen. The mainstream image (screen A) relating to the input digital image signal 5 input thereafter is sequentially displayed on the left side of the display screen.

Therefore, the operation unit 60 is constituted by, for example, a mechanical switch, and this switch is placed on the front surface of the image display device, that is, on the same surface as the surface on which the display screen on the housing of the image display device is formed. If it is arranged, simply turning on the switch at the time when the desired image related to the input digital image signal 5 is displayed, the desired image is displayed in a fixed manner, and the subsequent input from the same input source is performed. Input images (images related to the input digital image signal 5) can be sequentially displayed in parallel.

The input images from the same input source include images generated by the same application software,
Examples include images recorded on the same image recording medium such as a DVD. In this case, since the image display device has the above-described scan conversion function and synthesis conversion function, the type of the input image signal is not limited and has general versatility.

Note that the present invention is not limited to the above embodiment, and for example, an image to be fixedly displayed and an image to be sequentially displayed are displayed in a display area divided into two parts. However, as shown in the lower part of FIG. 3, each image can be displayed in a display area of a different size.

Further, as in the above-described embodiment, one read clock generator is provided for each of the two scan converters 20 and 23 without providing read clock generators 22 and 25 individually. The generator may be configured to be shared by the two scan converters 20 and 23. Also, in view of actively using the function of taking in images and displaying them in parallel, it is desirable that the aspect ratio of the display screen is 16: 9.

[0057]

As described above, according to the present invention,
With a simple operation, a plurality of images from the same arbitrary image source can be displayed in parallel.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic structure of an image display device according to a first embodiment of the present invention.

FIG. 2 is a flowchart showing an image display process unique to the first embodiment of the present invention.

FIG. 3 is a diagram for explaining an image display state unique to the first and second embodiments of the present invention.

FIG. 4 is a block diagram showing a schematic structure of an image display device according to a second embodiment of the present invention.

FIG. 5 is a flowchart showing an image display process unique to the second embodiment of the present invention.

FIG. 6 is a block diagram illustrating a schematic configuration of a conventional image display device.

FIG. 7 is a block diagram illustrating a schematic configuration of a conventional image display device with a picture-in-picture function.

FIG. 8 is a view for explaining a conventional simultaneous display processing of a plurality of images.

[Explanation of symbols]

 5, 7: input digital image signal 6, 8: input dot clock 20, 23: scan converter 20a, 23a: reduction interpolation processing circuit 20b, 23b: expansion interpolation processing circuit 21, 24: image memory 22, 25: read clock generation Unit 31: Synthesis conversion circuit 40: Image display unit 50: Control unit 50a: CPU 50b: ROM 50c: RAM 60: Operation unit 70, 71: Switch

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 5/14 G06F 3/14 350A 5/36 G09G 5/00 520V 5/391 5/36 520E // G06F 3/14 350 F term (reference) 5B050 AA10 BA06 BA16 CA07 EA12 EA19 FA02 5B057 AA20 BA02 CA12 CA16 CB12 CB16 CC01 CD05 CE08 5B069 AA01 AA20 BA01 BA04 BB16 BC02 CA13 5C082 AA01 AA03 BA02 BA12 BA26 BC33 DA76 DA86 DA89 EA15 MM02 MM05 MM09

Claims (14)

[Claims] An image capturing unit that captures an image supplied from a predetermined image supply source and currently displayed on a display screen in response to an operation of a predetermined operation unit; and an image captured by the capturing unit. An image display device comprising: a display control unit configured to display, on the display screen, an image sequentially supplied from the predetermined image supply source after operating the operation unit. 2. The image display device according to claim 1, wherein said operation means comprises a mechanical switch. 3. The image processing apparatus according to claim 1, wherein the operation unit is disposed on the same surface as the surface on which the display screen is formed on a housing of the image display device. Image display device. 4. The display control unit according to claim 1, wherein the image captured by the capture unit and an image sequentially supplied from the predetermined image source after the operation of the operation unit are arranged in parallel at substantially the same size. The image display device according to claim 1, wherein the image is displayed on the display screen. 5. The display control unit according to claim 1, wherein the display control unit displays the image captured by the capture unit and an image sequentially supplied from the predetermined image supply source after the operation of the operation unit in different sizes. The image display device according to claim 1, wherein the image is displayed on a screen. 6. An image display apparatus comprising: a first scan conversion unit for converting a resolution of a supplied digital image signal into an arbitrary resolution; a second scan conversion unit; and the first scan conversion unit. A first image storage unit and a second image storage unit that are respectively used for scan conversion processing in the second scan conversion unit, and outputs from the first scan conversion unit and the second scan conversion unit And synthesizing means for synthesizing the obtained image signal and converting the image signal into a signal suitable for display on the display screen, wherein the capturing means operates the second operating means only when the predetermined operating means is operated. The display control means permits the storage processing in the first image storage means even after the predetermined operation means is operated, whereby the combining conversion processing is performed. Wherein the image to be combined is controlled so as to be a fixed image at the time when the predetermined operation means is operated and an image sequentially supplied from the same image source after the operation. The image display device according to claim 1. 7. The image according to claim 6, wherein an image supplied from the same image supply source is always input to the first scan conversion unit and the second scan conversion unit. Display device. 8. Normally, images supplied from different image sources are input to the first scan conversion means and the second scan conversion means, and after the predetermined operation means is operated, The image display device according to claim 6, wherein images supplied from the same image supply source are input. 9. The apparatus according to claim 6, wherein both the first scan conversion means and the second scan conversion means have a reduction interpolation processing function and an enlargement interpolation processing function. Image display device. 10. An aspect ratio of the display screen is 16:
The image display device according to claim 1, wherein the image display device is an image display device. 11. An image capturing step of capturing an image supplied from a predetermined image supply source and currently displayed on a display screen in response to an operation of a predetermined operation unit, and an image captured by the capturing step. A display control step of displaying, on the display screen, an image sequentially supplied from the predetermined image supply source after the operation of the operation means. 12. The display control step includes the step of parallelly setting the image captured in the capturing step and the image sequentially supplied from the predetermined image supply source after the operation of the operation means in substantially the same size. The image display method according to claim 11, wherein the image is displayed on the display screen. 13. The display control step, wherein the image captured in the capturing step and the image sequentially supplied from the predetermined image source after the operation of the operating means are displayed in parallel in different sizes. The image display method according to claim 11, wherein the image is displayed on a screen. 14. An image supplied from a predetermined image supply source and currently displayed on a display screen is fetched in response to an operation of a predetermined operation means, and the fetched image and the predetermined image are operated after the operation of the operation means. A control program having contents for displaying images sequentially supplied from an image supply source on the display screen in parallel.