JP2002335234A - Serial data transmitting method and transmission interface circuit using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a one-wire type serial data transmitting method and a transmission interface circuit using the same without lowering the noise margin of data transmission. SOLUTION: On a transmitting side, data DA are transmitted while being mixed with a clock signal CL and on a receiving side, a transmitting side data bit string is reconstituted by extracting clock timing c1. In such a transmitting method, in the case of transmitting from the transmitting side, a chip select signal CS of H level continued for a long period, one return zero type clock signal CL after this chip select signal CS and data bit by bit successive from the top bit of transmitting data DA to the final bit are alternately transmitted and when the chip select signal CS is received on the receiving side, the clock timing c1 is extracted from following data. Then, transmitting data are written in a buffer memory bit by bit at write timing w1 delayed from the timing c1 for predetermined time.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a serial data transmission method for performing serial data transmission on a single transmission line and a transmission interface circuit using the method, and more particularly to a semiconductor integrated circuit having an interface circuit.

[0002]

2. Description of the Related Art In recent years, with the miniaturization of semiconductor devices, many functions have been integrated into a single-chip semiconductor integrated circuit (hereinafter abbreviated as IC), and as a result, the number of pins of a package has been increasing. On the other hand, there are conflicting technical demands for smaller packages and a smaller number of pins. In particular, this is a major problem for ICs that require digital signal control such as output voltage control in power supply ICs with a small number of pins. Describing the interface circuits for controlling digital signals such as these power supply ICs, changing from a parallel interface circuit (for example, 8 bits) to a serial interface circuit reduces the data transfer speed, but reduces the number of pins of the interface circuit. Since the data transfer rate can be reduced, a serial interface circuit has come to be frequently used in portable devices that do not require a data transfer speed.

However, in FIG. 12, even though a serial interface circuit is used, a line (the number of pins) necessary for controlling transmission to a transmission line according to the prior art generally includes a chip selection signal CS and a clock signal. Signal CLK and data DATA
And a read / write control signal R / W. On the other hand, in recent years, a three-wire or two-wire serial data transmission method has emerged for this line, which contributes to a reduction in the number of IC pins, that is, a reduction in the package. In the three-wire serial data transmission method, the control line can be deleted by taking in the read / write control signal R / W as a part of the data. In the two-wire serial data transmission method, the control lines can be further deleted by detecting the state of the data DATA and the clock CLK and realizing the chip select signal CS. Among such two-wire serial data transmission methods, in particular, Philips I2L is well known and infiltrated.

Japanese Patent Application Laid-Open No. 7-95248, entitled "Time-division data communication system" discloses a one-wire serial data transmission method. In FIG. 12, the horizontal axis is the time axis, and the vertical axis is the transmission data DA, clock signal CL, intermediate potential,
FIG. 4 shows a waveform diagram in which a transmission output 1c to the transmission line 1 and the transmission data DA are restored by removing the clock signal CL by a separation circuit on the reception side. That is, in the illustrated example, the transmission data 1c is H, H, L, L, H, H,
When L, L, H, H, ... are output, the power supply voltage Vcc (= 5V) is output as the intermediate potential output when the transmission data is at the H level, and the intermediate potential is output when the transmission data is at the L level. Power supply voltage Vcc is divided by resistors R1 and R2 as output, for example, 1/2 V
Outputs cc (= 2.5V). This intermediate potential is applied to the clock signal CL
The transmission output is output to the transmission line 1 by modulating the signal.
As a result, when the transmission data is at the H level, a square wave 1c having an amplitude of 5V-PP is output, and when the transmission data is at the L level, a square wave 1c having an amplitude of 2.5V-PP is output to the transmission line. Therefore,
In the receiving unit 4, for example, when the serial data is determined using a threshold value of 3V, when the transmission data DA is H, the amplitude is 5V.
-Detects the square wave of -PP and 0V when the transmission data DA is L
Can be detected. That is, since the receiving side 4 can simultaneously perform the reception processing of the transmission data DA and the clock signal CL, the synchronization processing of the reception signal can be performed.

[0005]

In the present invention, in order to reduce the number of transmission lines and the number of pins,
It provides a one-wire interface. Also,
In the serial data transmission method disclosed in Japanese Patent Application Laid-Open No. 7-95248, "Time-division data communication method", serial data is transmitted by superimposing a clock signal on transmission data, and a predetermined threshold value is determined from the received serial data. By the identification, the transmission data and the clock signal can be easily separated and restored. However, when the transmission data is at the L level, the difference between the identification threshold and the L level is small, so that the noise margin when viewed as a whole data transmission system may be lower than that of a normal system.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to solve the above-mentioned problems and to reduce the data transmission noise margin without reducing the one-line serial data transmission method and the method. An object of the present invention is to provide a transmission interface circuit using the method.

[0007]

In order to achieve the above object, according to the present invention, data is mixed with a clock signal on a transmitting side and transmitted, and a clock timing is extracted on a receiving side and serially received. A serial data transmission method for reconstructing a data bit sequence on a transmission side from a transmission signal,
When transmitting data to the transmission line, the transmitting side outputs a chip selection signal (CS) that outputs an H level that lasts longer than the clock signal and then outputs an L level, and after this chip selection signal, returns zero ( (RZ) type one clock signal and serial data obtained by alternately selecting and converting return zero (RZ) type data of the transmission data, one bit at a time from the first bit to the last bit. The transmission side receives the chip selection signal (C
When S) is received, the clock timing is extracted from the subsequent serial data, and the transmission data of the serial data is written into the buffer memory one bit at a time at a write timing delayed by a predetermined time from the extracted clock timing. .

According to such a transmission method, each one of the transmission data is
Since there is a one-bit return zero (RZ) type transmission clock before the bit data, a predetermined clock timing is extracted from this return zero (RZ) type transmission clock, and the subsequent transmission data is reliably generated. Transmission data of 1 bit at a time can be written to the buffer memory at the write timing at which H and L can be determined. That is, the timing of the transmission clock can be extracted from the transmitted serial data, and the transmission data can be written to the memory at regular intervals in synchronization with this timing.

[0009] Further, the transmission side mixes the data with the clock signal and transmits the data, and the reception side extracts the clock timing,
A serial data transmission method for reconstructing a data bit sequence on a transmission side from a transmission signal received serially, wherein the transmission side outputs an H level that lasts longer than a clock signal when transmitting data to a transmission path. After that, a chip selection signal (CS) that outputs an L level, a clock signal of a return zero (RZ) type after this chip selection signal, and one bit of transmission data from the first bit to the last bit in order. The non-return zero (NRZ) type data and the serial data obtained by alternately selecting the non-return zero (NRZ) type data are transmitted.
When a chip select signal (CS) is received from a transmission signal transmitted on the transmission line, clock timing is extracted from the subsequent serial data, and the serial data is written at a predetermined time delay write timing from the extracted clock timing. Is written to the buffer memory one bit at a time.

With this transmission method, similarly to the case where the transmission data is return zero (RZ) type data, the clock timing position extracted from the return zero (RZ) type transmission clock to be extracted and the write to write into the buffer memory Although there is a difference in the timing position, from the extracted clock timing, the following transmission data is reliably H,
The transmission data for each bit can be written to the buffer memory at the write timing at which L can be determined. That is, the timing of the transmission clock can be extracted from the transmitted serial data, and the transmission data can be written to the memory at regular intervals in synchronization with this timing.

The transmission data is a chip selection signal (CS)
And a pulse width signal for measuring a clock pulse width between the data and the serial data. According to such a transmission method, after receiving the chip select signal (CS), the receiving side measures the pulse width signal of the transmission clock signal to be transmitted subsequently, and multiplies the measured pulse width by a magnification determined in advance for each transmission method. , The time from the extracted clock timing to the write timing can be known. Therefore, by controlling the delay time of the write timing with this time, serial data transmission can be performed without being aware of the transmission clock cycle on the transmission side.

In a transmission interface circuit using the above-described serial data transmission method, an internal clock circuit, a frequency dividing circuit for dividing the internal clock to form a transmission clock, and a transmission line controlled by the transmission clock A transmission unit that outputs a transmission signal to a transmission line, a reception unit that receives a transmission signal transmitted from a transmission line by an internal clock, restores transmission data on the transmission side, and writes the data in a buffer memory, and a transmission unit and a transmission unit. Connection means for connecting to a path, the transmission unit includes a transmission data buffer memory, a chip selection signal forming circuit, and, after transmitting the chip selection signal, transmitting a transmission clock and transmission data in the buffer memory one bit at a time. And a control circuit for alternately selecting and outputting the transmission signal. A chip selection signal detection circuit for detecting a chip selection signal, a clock extraction means for extracting a clock timing from subsequent serial data when the chip selection signal is detected, and A timing forming circuit that outputs a write timing pulse with a predetermined timing delay, and a reception data buffer memory that writes transmission data of serial data received by the timing pulse of the timing formation circuit bit by bit are provided. .

With this configuration, when the transmission interface circuit receives a transmission request from a partner device, or receives a transmission request from an information processing device in its own device and transmits data to the transmission path, the transmission unit connects The means is switched to the transmission side, and a chip selection signal is transmitted from the chip selection signal forming circuit via the control circuit based on the transmission clock formed by dividing the internal clock, and then the control circuit transmits the transmission clock and the transmission data buffer. The serial data can be transmitted by alternately selecting and controlling the data in the memory one bit at a time.

When there is no transmission request, the connection unit is switched to the receiving side to stand by, and the receiving unit monitors the presence or absence of a chip selection signal transmitted to the transmission path. In this state, when the chip selection signal detection circuit detects the chip selection signal, the clock extraction means extracts the clock timing from the subsequent serial data, and the timing formation circuit writes the data with a predetermined timing delay from the extracted clock timing. A timing pulse is output, and the transmission data of the serial data received from the transmission path by this timing pulse can be written into the reception data buffer memory one bit at a time.

In the transmission interface circuit using the above serial data transmission method, an internal clock circuit, a frequency dividing circuit for dividing the internal clock to form a transmission clock, and a transmission line controlled by the transmission clock A transmission unit that outputs a transmission signal to a transmission line, a reception unit that receives a transmission signal transmitted from a transmission line by an internal clock, restores transmission data on the transmission side, and writes the data in a buffer memory, and a transmission unit and a transmission unit. Connection means for connecting to a channel, the transmission section outputs a clock pulse width measurement signal after transmitting the transmission data buffer memory, the chip selection signal forming circuit, and the chip selection signal.
A control circuit for alternately selecting and outputting the transmission clock and the transmission data in the buffer memory one bit at a time, wherein the reception unit comprises: a chip selection signal that keeps the transmission signal received from the transmission line at the H level for a predetermined time. And a pulse width detection circuit that measures a clock pulse width when the chip selection signal is detected,
Clock timing extracting means for extracting clock timing from subsequent serial data, a timing forming circuit for outputting a write timing pulse with a predetermined timing delay corresponding to the output of the clock timing extracting means, And a reception data buffer memory for writing transmission data of serial data received by the timing pulse one bit at a time.

With this configuration, when the transmission interface circuit receives a transmission request from a partner device, or receives a transmission request from an information processing device in its own device and transmits data to a transmission path, the transmission unit establishes a connection. The means is switched to the transmission side, and a chip selection signal is transmitted from the chip selection signal forming circuit via the control circuit based on the transmission clock formed by dividing the internal clock, and then the control circuit transmits the transmission clock and the transmission data buffer. The serial data can be transmitted by alternately selecting and controlling the data in the memory one bit at a time.

When there is no transmission request, the connection unit is switched to the receiving side to stand by, and the receiving unit monitors the presence or absence of a chip selection signal transmitted to the transmission path. In this state, when the chip selection signal detection circuit detects the chip selection signal, the pulse width detection circuit measures the clock pulse width and sets the timing delay time of the timing forming circuit. Subsequently, the clock extracting means extracts the clock timing from the subsequent serial data, and the timing forming circuit outputs a write timing pulse with the set timing delay time from the extracted clock timing, and this timing pulse outputs the write timing pulse from the transmission line. The transmission data of the received serial data can be written to the reception data buffer memory one bit at a time.

Further, the control circuit of the transmission interface circuit selects data in the transmission data buffer memory one bit at a time using a transmission clock formed by dividing the internal clock, and takes a logical product with the transmission clock. A first control circuit for alternately selecting and outputting a logical product output and the transmission clock can be provided. With this configuration, the transmission data of the serial data can be configured as return zero (RZ) type data.

The control circuit of the transmission interface circuit alternately selects a transmission clock formed by dividing the internal clock and data in the transmission data buffer memory one bit at a time using the transmission clock. A selector circuit (second control circuit) for outputting can be provided. With this configuration, the transmission data of the serial data can be configured as non-return zero (NRZ) type data.

The control circuit of the transmission interface circuit has a first control circuit or a second control circuit, and after transmitting the chip select signal, transmits only the first transmission clock by two transmission clocks, and then transmits the transmission data buffer. A logical value circuit for alternately selecting transmission data from the memory one bit at a time. With this configuration, a transmission clock for pulse width measurement can be inserted between the chip selection signal and the serial data.

The clock extracting means for extracting the clock timing from the serial data, when the transmission data of the transmission signal is composed of return zero (RZ) type data, extracts the clock at the rising timing of the serial data clock. The predetermined write timing pulse of the timing forming circuit can be output with a 5/2 transmission clock pulse width delay from the rising timing of the extracted clock.

The clock extracting means for extracting the clock timing from the serial data, when the transmission data of the transmission signal is composed of non-return-to-zero (NRZ) type data, the clock rising at the central part of the clock of the serial data. A clock is extracted at the falling edge of the clock, and the predetermined write timing pulse of the timing forming circuit may be output with a delay of two transmission clock pulse widths with respect to the extracted changing timing of the central portion of the clock. it can.

Further, the clock extracting means and the timing forming circuit of the transmission interface circuit are provided in a predetermined manner.
A down counter for the number of internal clocks corresponding to the 5/2 transmission clock pulse width or 2 transmission clock pulse widths is provided. The number of internal clocks is set in this down counter at the clock timing extracted by the clock extraction means, and the internal clock counts down. Thus, a flag is set with a count value of zero, and the transmission data of serial data can be written to the reception data buffer memory one bit at a time using this flag.

Further, the transmission interface circuit sets the clock pulse width detected by the clock pulse width detection circuit to 5/2.
Double or double, set the number of clocks of this value in the down counter, count down with the internal clock,
A flag is set with a count value of zero, and the transmission data of serial data can be written to the reception data buffer memory one bit at a time using this flag.

With this configuration, after receiving the chip select signal (CS), the receiving side measures the pulse width signal of the transmission clock signal transmitted subsequently, and determines the measured pulse width in advance for each transmission method. The time from the extracted clock timing to the write timing can be known by multiplying the obtained magnification. Therefore, by controlling the delay time of the write timing with this time, serial data transmission can be performed without being conscious of the transmission clock on the transmission side.

The receiving section includes a chip selection signal detection circuit for detecting a chip selection signal in which the transmission signal received from the transmission path keeps the H level for a predetermined time, and when detecting the chip selection signal, A memory counter that measures the clock pulse width of the transmission clock, a count value of the memory counter, a shift register that shifts the set value by one bit and performs a 演算 operation, and counts up the internal clock. Pulse width with reset function (P
w) a counter, a comparator that compares the count value of the memory counter calculated by a half of the shift register with the count value of the pulse width (Pw) counter, and resets the count value of the up counter with the output of this comparator. A counter for counting the comparator output in quinary, a shift register for generating a write timing pulse delayed by 5/2 clock width from the clock timing, and sequentially writing serial data transmission data with the write timing pulse. be able to.

[0027]

FIG. 1 is a transmission waveform diagram illustrating a serial data transmission method according to a first embodiment of the present invention, FIG. 2 is a transmission waveform diagram illustrating a serial data transmission method according to a second embodiment, and FIG. FIG. 4 is a transmission waveform diagram having a pulse width measurement signal in the first embodiment, FIG. 4 is a transmission waveform diagram having a pulse width measurement signal in the second embodiment, and FIG. FIG. 6 is a timing operation diagram for restoring
FIG. 7 is a timing operation diagram for restoring transmission data from the serial data of the second embodiment in the receiving section, FIG. 7 is a block diagram of the transmission interface circuit of the first and second embodiments, and FIG. 8 is a pulse width detection circuit of the transmission clock And FIG. 9 is a block diagram of a transmission interface circuit according to an embodiment of the present invention.
10 is an operation waveform diagram illustrating the operation of one embodiment, FIG. 11 is a configuration diagram illustrating the configuration of the transmission signal transmitted on the transmission line according to the present invention, the same functional members corresponding to FIGS. Are denoted by the same reference numerals. (Embodiment 1) In FIG. 1, the serial data transmission method according to the present invention uses the data DA (= D7, D6,... D1, D0) on the transmission side.
, A clock signal (CL, CL, CL,...) Is mixed and transmitted, and a clock timing c1 (see FIG. 5 (B)) is extracted on the receiving side, and the transmission signal (CS = (CL , D7, CL, D6 ...
CL, D1, CL, D0))) to the data bit string (D7, D6 ...
D1, D0), a serial data transmission method for reconstructing
On the transmission side, when transmitting the data (1c) to the transmission line 1, a chip selection signal CS that outputs an H level that lasts longer than the clock signal CL and then outputs an L level, , H, L levels appear half each within one clock Return-zero (RZ) type one clock signal CL
And the first bit (D7) of the transmission data (D7, D6 ... D1, D0)
, And return-zero (RZ) type data (D7, D6,..., D1, D0) for each bit from the first bit to the last bit (D0) in order from (B) in FIG.
As shown in the figure, serial data (CL, D7, CL, D6... CL, D0) alternately selected and converted are transmitted.

On the receiving side, when the chip selection signal CS is received from the transmission signal (1b) transmitted to the transmission line 1, the clock timing is determined from the subsequent serial data (CL, D7, CL, D6... CL, D0). c1 and transmit data (D7, D6) from the serial data (CL, D7, CL, D6, CL, D0) at a write timing w1 delayed by a predetermined time (T1) from the extracted clock timing c1. .. D1, D0) can be written and controlled bit by bit in the buffer memory (44).

With this transmission method, the transmission data (D7, D6
..Because each one-bit data (Dj) of D1, D0) is preceded by a one-bit return zero (RZ) type transmission clock CL, a predetermined one is determined from the return zero (RZ) type transmission clock CL. The clock timing c1 (for example, the rising portion of the transmission clock CLK in FIG. 5A) is extracted, and the next transmission data (Dj) can be reliably determined to be H or L at the write timing (for example, (B) in FIG. 5). The transmission data Dj of each bit can be written into the buffer memory (44) at the H (L) level of the transmission data indicated by w1). That is, the serial data (CL, D7, CL, D6 ...
(CL, D0) to extract the timing c1 of the transmission clock CL, and synchronize the timing c1 with the timing of a constant interval (T1).
The transmission data (D7, D6... D1, D0) can be written to the memory 44 by w1. (Embodiment 2) In FIG. 2, the serial data transmission method according to the present invention uses the data DA (= D7, D6,.
D1, D0) mixed with a clock signal (CL, CL, CL,...) And transmitted, and the receiving side extracts clock timing c2 (see (B) in FIG. 6) and transmits the serially received transmission signal. (CS = (CL,
D7, CL, D6 ... CL, D1, CL, D0)) is a serial data transmission method for reconstructing the data bit string (D7, D6 ... D1, D0) on the transmission side from the transmission side. When transmitting 1c) to the transmission line 1, the chip selection signal CS that outputs an H level that lasts longer than the clock signal CL and then outputs an L level
After the chip selection signal CS, one return zero (RZ) type clock signal CL and the last bit (D0) of the transmission data (D7, D6... D1, D0) in order from the first bit (D7) from the first bit (D7) As shown in FIG. 2B, non-return zero (NRZ) type data (D7, D6... D1, D0) in which the H and L levels of each bit up to one bit last for one clock , And serial data (CL, D7, CL, D6... CL, D0) alternately selected and converted.

On the receiving side, when receiving the chip selection signal CS from the transmission signal (1b) transmitted to the transmission line 1, the clock timing from the subsequent serial data (CL, D7, CL, D6... CL, D0) c2, and transmit data (D7, D6) from the serial data (CL, D7, CL, D6, CL, D0) at a write timing w2 delayed by a predetermined time (T2) from the extracted clock timing c2. .. D1, D0) can be written and controlled bit by bit in the buffer memory (44).

According to such a transmission method, each one-bit data of the transmission data (D7, D6,..., D1, D0) is similar to the transmission data of the return zero (RZ) type described in the first embodiment.
Since there is a one-bit return zero (RZ) type transmission clock CL before (Dj), a predetermined clock timing c2 (for example, (A) in FIG. 6) is obtained from the return zero (RZ) type transmission clock CL. ) Falling edge of the transmission clock CLK)
At the write timing at which the next transmission data (Dj) can be reliably determined to be H or L (for example, at the center of the H or L level indicated by w1 in the transmission data of FIG. 6B). Transmission data Dj for each bit can be written to the buffer memory (44). That is, the serial data (CL, D
7, CL, D6 ... CL, D0) to transmission clock CLK timing c
2 is extracted and synchronized at a certain interval (T
The transmission data (D7, D6... D1, D0) can be written in the memory 44 in 2). (Embodiment 3) In addition, in FIGS.
(D7, D6 ... D1, D0) must have a pulse width signal Pw for measuring the clock pulse width between the chip select signal CS and the serial data (CL, D7, CL, D6 ... CL, D0). Can be.

According to this transmission method, after receiving the chip select signal (CS), the receiving side measures the pulse width signal Pw of the transmission clock signal to be transmitted subsequently. By multiplying by a predetermined magnification (5/2 times, 2 times) for each transmission method of mode 2, the time (T1 or t1) from the extracted clock timing (c1 or c2) to the write timing (w1 or w2) T2). Therefore, by setting and controlling the write timing delay time at this time (T1 or T2), serial data transmission can be performed without being aware of the cycle of the transmission clock CL on the transmission side.

[0033]

EXAMPLE 1 Example 1 will be supplemented with reference to FIGS. 1, 5 and 7. In FIG. 7, a transmission interface circuit 2 (2A, 2B) using the serial data transmission method according to the present invention has a hardware configuration used in the first and second embodiments.
A frequency dividing circuit 22 that divides the internal clock clk to form a transmission clock CL, and a transmitting unit 3 (3A, 3A, 3A) that outputs a transmission signal 1a (= 1c) to the transmission line 1 under the control of the transmission clock CL.
3B) and the transmission signal 1a (= 1b) transmitted from the transmission path 1.
Receiving section 4 (4) which receives the internal clock clk, restores the transmission data 1c on the transmission side, and writes the data in the buffer memory 44.
A, 4B) and connection means 13 represented by a switch for connecting the transmission unit 3 and the reception unit 4 to the transmission line 1.

The transmission unit 3 (3A, 3B) is provided with a central processing unit (C) of a device in which the transmission interface circuit 2 (2A, 2B) is housed.
PU) 5, a transmission data buffer memory 33 for temporarily storing transmission data, a chip selection signal forming circuit 31, and after transmitting this chip selection signal (CS) 31a, a transmission clock CL and transmission data 33a in the buffer memory 33 are transmitted. And a control circuit 32 (32A, 32B) for alternately selecting and outputting 1 bit by 1 bit.

With this configuration, when the transmission interface circuit 2 (2A, 2B) receives a transmission request from the communication partner device, or receives a transmission request from the central processing unit 5 in its own device, the data 1c is transmitted to the transmission line 1. (= 1a)
The transmission unit 3 (3A, 3B) switches the connection means 13 to the transmission side (1c) and divides the internal clock clk to form a transmission clock.
Based on CL, a chip selection signal (CS) 31a is transmitted from the chip selection signal forming circuit 31 via the control circuit 32 (32A, 32B).
Subsequently, the control circuit 32 (32A, 32B) transmits the transmission clock CL and the transmission data (D7, D6,..., D1, D0) of the transmission data buffer memory 33.
And alternately select and control the serial data (C
L, D7, CL, D6 ... CL, D1, CL, D0) are transmitted. This operation waveform is shown in FIG.

In FIG. 1, the horizontal axis represents the time axis from left to right. In FIG. 1A, the transmission clock CL, the transmission data DA (= D7, D6... D1, D0) and the transmission clock CL and the transmission data DA (D7, D6. Is controlled alternately one bit at a time, and serial data (CL, D7, CL, D6
・) Indicates the state of transmission control. This control circuit 32 (32A)
Although not shown, the transmission clock CL formed by dividing the internal clock clk is used to select the transmission data 33a in the transmission data buffer memory 33 bit by bit, and AND the transmission data CL with the transmission clock CL. , And a first control circuit 32A for alternately selecting and outputting the logical product output and the transmission clock CL. Alternatively, for example, it can be configured by alternately selecting the H level and the transmission data DA of the buffer memory 33 one bit at a time and taking the logical product of the selected data and the transmission clock CL.

With this configuration, the control circuit 32A can configure the transmission data DA of the serial data as return zero (RZ) type data. The transmission signal 1c thus formed can be transmitted to the transmission line 1 as shown in FIG. The transmission data (D7, D6... D1, D0) in the illustrated example is (1, 0, 1,
(0,0,0,1,1) is transmitted, and since the time axis flows to the right, the leading end of the transmission signal 1c to the transmission line 1 is headed by the left chip selection signal (CS). is there.

Next, returning to FIG. 7, the receiving unit 4 (4A, 4B)
Is a chip selection signal detection circuit 41 for detecting a chip selection signal CS in which a transmission signal 1b (= 1a) received from the transmission line 1 keeps the H level for a predetermined time,
When CS is detected, the subsequent serial data (CL, D7, CL,
D6 ...) to clock timing (c1 shown in Fig. 5)
Clock extraction means 42 (42A, 42B) for extracting the clock signal and write timing pulses w1, with a predetermined timing delay (T1, T2) corresponding to the outputs c1, c2 of the clock extraction means 42 (42A, 42B). Timing formation circuit 43 (43A, 4
3B) and the serial data (CL, D7, CL, CL) received by the timing pulses w1, W2 of the timing forming circuit 43 (43A, 43B).
..) Is written one bit at a time, and a reception data buffer memory 44 for writing the transmission data DA (= D7, D6...) One bit at a time.

With this configuration, when there is no transmission request, the connection unit 13 is switched to the receiving side to wait, and the receiving unit 4
Monitors the presence or absence of a chip select signal CS transmitted to the transmission path 1. In this state, when the chip selection signal detection circuit 41 detects the chip selection signal CS, the clock extraction means 42 (4
2A) extracts the clock timing c1 shown in FIG. 5 for each clock CL from the subsequent serial data (CL, D7, CL, D6...), And the timing forming circuit 43A preliminarily extracts the clock timing c1 from the extracted clock timing c1. Set timing delay
The write timing pulse w1 is output at T1, and the serial data (C
The transmission data (D7, D6,...) Of L, D7, CL, D6,...) Is written into the reception data buffer memory 44 bit by bit, and the reception data DA can be passed from the buffer memory 44 to the central processing unit 5.

In FIG. 5, the horizontal axis represents the time axis from left to right. In FIG. 5A, the transmission clock CL, transmission data DA (= D7, D6... D1, D0), and serial data (CL, D7, CL, D6...) Indicates reception status. Also,
FIG. 5B shows a state in which the write timing pulse w1 is output with a predetermined timing delay T1 from the clock timing c1.

Here, the serial data (CL, D7, CL, D6
The clock extraction means 42A that extracts the clock timing c1 from the transmission data DA (= D7, D6
When (1, D0) is composed of return zero (RZ) type data, the clock c1 is extracted at the rising edge of the clock in the serial data (illustrated by the upward arrow of the serial data), and the clock c1 is extracted by the timing forming circuit 43A. The predetermined write timing pulse w1 can be output (w1) with a delay of 5/2 transmission clock pulse width (T1 = 5 / 2Pw) from the rising timing c1 of the extracted clock. By selecting the delay time T1 of the timing forming circuit 43 in this manner, the transmission data (D7, D6,..., D1, D0)
Writing to the buffer memory 44 can be performed at the central portion of the L-level significant data, and the receiving unit 4 can be configured to be resistant to fluctuations in the cycle of the internal clock cl and noise. FIGS. 5C and 5D show the case where the transmission clock is delayed by a half cycle of the transmission clock cycle. In this case as well, the clock extracting means 42A operates at the timing of the rising edge of the clock in the serial data. Similarly, by extracting the clock c1, the transmission data DA (= D7, D6,...) Of the serial data (CL, D7, CL, D6,. The received data DA can be written to the received data buffer memory 44 and passed from the buffer memory 44 to the central processing unit 5. (Example 2) The description of Embodiment 2 will be supplemented with reference to Figs. In FIG. 7, the difference between the transmission interface circuit 2 according to the present invention and the first embodiment is that the transmission data (D7,
D6... D1, D0) are constituted by non-return zero type data. Therefore, here, the control circuit 32B of the transmitting unit 3 and the clock extracting unit of the receiving unit 4 are different from those of the first embodiment.
The following mainly describes the timing control circuit 42 and the timing forming circuit 43.

The transmission section 3 (3B) includes a transmission data buffer memory 33 for temporarily storing transmission data from the central processing unit (CPU) 5 of the device in which the transmission interface circuit 2 (2B) is stored, A signal forming circuit 31 and a control circuit 32 (32B) for alternately selecting and outputting the transmission clock CL and the transmission data 33a in the buffer memory 33 one bit at a time after transmitting the chip selection signal (CS) 31a. Be composed.

With this configuration, when the transmission interface circuit 2 (2B) receives a transmission request from the communication partner device, or receives a transmission request from the central processing unit 5 in its own device, the data 1c (= 1a), the transmitting section 3 (3B) switches the connection means 13 to the transmitting side (1c), and based on the transmission clock CL formed by dividing the internal clock clk, generates a signal from the chip selection signal forming circuit 31. Chip select signal (CS)
31a is transmitted via the control circuit 32 (32). Subsequently, the control circuit 32 (32B) alternately controls the transmission clock CL and the data (D7, D6,..., D1, D0) of the transmission data buffer memory 33 bit by bit to serial data (CL, D7, CL, D6 ... CL, D1, C
L, D0). This operation waveform is shown in FIG.

In FIG. 2, the horizontal axis represents the time axis from left to right. 2A, the transmission clock CL, the transmission data DA (= D7, D6... D1, D0) and the transmission clock CL and the transmission data DA (D7, D6...) Is controlled alternately one bit at a time, and serial data (CL, D7, CL, D6
・ ・) Indicates the state of transmission control. This control circuit 32B
Although not shown, the transmission clock CL formed by dividing the internal clock clk and the transmission data 33a in the transmission data buffer memory 33 by this transmission clock CL are sequentially and alternately bit by bit. A selector circuit (second control circuit) 32B for selecting and outputting can be provided.

With this configuration, the transmission data of the serial data can be configured as non-return zero (NRZ) type data. The transmission signal 1c thus formed can be transmitted to the transmission line 1 as shown in FIG. The transmission data (D7, D6,..., D1, D0) in the illustrated example indicates a state in which (1,0,1,0,0,0,1,1) has been transmitted, and since the time axis flows to the right, , The head of the transmission signal 1c to the transmission path 1 is the left chip selection signal
(CS) is first.

Next, returning to FIG. 7, the receiving unit 4 (4B) detects the chip selection signal CS in which the transmission signal 1b (= 1a) received from the transmission line 1 keeps the H level for a predetermined time. The chip select signal detection circuit 41 detects the serial data (CL, D7, CL, D6
Clock extracting means 42B for extracting a clock timing (c2 shown in FIG. 6) from
Predetermined timing delay corresponding to output c2 of 42B
(T2), a timing forming circuit 43B that outputs a write timing pulse w2, and the serial data (CL, D7, CL, D6) received by the timing pulse w2 of the timing forming circuit 43B.
..) For writing the transmission data DA (= D7, D6...) One bit at a time.

With this configuration, when there is no transmission request, the connection unit 13 is switched to the receiving side to stand by, and the receiving unit 4
(4B) monitors the presence or absence of the chip selection signal CS transmitted to the transmission path 1. In this state, the chip selection signal detection circuit
When 41 detects the chip select signal CS, the clock extraction means
42B extracts the clock timing c2 shown in FIG. 6 for each clock CL from the subsequent serial data (CL, D7, CL, D6...), And the timing forming circuit 43B determines the clock timing c2 from the extracted clock timing c2 in advance. Timing delay
At T2, a write timing pulse w2 is output, and at this timing pulse w2, serial data (C
The transmission data DA (= D7, D6,...) Of L, D7, CL, D6,...) Is written to the reception data buffer memory 44 bit by bit, and the reception data Data is passed from the buffer memory 44 to the central processing unit 5. it can.

In FIG. 6, the horizontal axis represents the time axis from left to right. 6A, the transmission clock CL, the transmission data DA (= D7, D6... D1, D0), and the serial data (CL, D7, CL, D6...) Indicates reception status. Also,
FIG. 6B shows a state in which the write timing pulse w2 is output with a predetermined timing delay T2 from the clock timing c2.

Here, the serial data (CL, D7, CL, D6
The clock extracting means 42B for extracting the clock timing c2 from the transmission data DA (= D7, D6
When (1, D0) is composed of non-return-to-zero (NRZ) type data, the clock is clocked at the rising or falling edge of the clock at the center of the serial data clock (illustrated by the upward or downward arrow of the serial data). c2, and the predetermined write timing pulse w2 of the timing forming circuit 43B is output with a delay of two transmission clock pulse widths (T2 = 2Pw) with respect to the extracted timing at which the central portion of the clock changes. Can be. By selecting the delay time T2 of the timing forming circuit 43B in this manner, the transmission data (D7, D6,..., D1, D0)
Writing can be performed to the buffer memory 44 at the central part of the L level, and the receiving unit 4B that is resistant to fluctuations in the cycle of the internal clock cl and noise can be configured. FIG.
(C) and (D) show the state in which the transmission clock CL is delayed by half the transmission clock period, and in this case also, the clock extracting means 42B detects the clock c2 at the timing of the rising edge of the clock in the serial data. By extracting, similarly, the transmission data DA (= D7, D6) of the serial data (CL, D7, CL, D6...) Received from the transmission path 1 with the timing pulse w2
..) is written into the reception data buffer memory 44 bit by bit, and the reception data Data can be passed from the buffer memory 44 to the central processing unit 5.

The clock extracting means 42 (42A, 4A) of the transmission interface circuit 2 (2A.2B) of the first or second embodiment
2B) and the timing forming circuit 43 (43A, 43B) have a predetermined 5/2 transmission clock pulse width ((5/2) Pw; 42A, 43A).
Alternatively, a down counter of the number of internal clocks clk corresponding to 2 transmission clock pulse widths (2Pw; 42B, 43B) is provided, and the internal clock is supplied to this down counter at clock timings c1, c2 extracted by the clock extraction means 42 (42A, 42B). Set the number, count down with the internal clock clk, set the flag F with a count value of zero, and use this flag F to store the serial data (CL, D7, CL, D6 ...) in the receive data buffer memory 44.
) Can be written bit by bit.

In such a configuration, generally, the transmission side and the reception side are configured so that the period of the internal clock clk is selected to be substantially the same value, and the transmission for synchronization must be performed before transmission data. There is a clock, and this clock extraction point c
Data may be written with a certain timing period T1, T2 shifted from 1, c2. Therefore, the timing periods T1, T2
Can have a very rough configuration, so that the circuit can be easily configured with a down counter. Embodiment 3 The description of Embodiment 3 will be supplemented with reference to FIGS. 3, 4, and 8. In FIG. 8, a transmission interface circuit 2 (2C, 2D) according to the present invention comprises an internal clock circuit 21, a frequency divider 22 for dividing the internal clock clk to form a transmission clock CL, and a transmission clock CL. A transmitting unit 3 (3C, 3D) that is controlled and outputs a transmission signal 1c to the transmission path 1;
The transmission signal 1b transmitted from the transmission path 1 is used as an internal clock.
clk and transmit data DA (D7, D6 ...
(D1, D0) is restored and written into the buffer memory 44.
(4C, 4D), transmitting unit 3 (3C, 3D) and receiving unit 4 (4C, 4D)
And connection means 13 for connecting the transmission line 1 to the transmission line 1.

The transmitting section 3 (3C, 3D) outputs the clock pulse width measurement signal Pw after transmitting the transmission data buffer memory 33, the chip selection signal forming circuit 31, and the chip selection signal CS, and then outputs the clock pulse width measurement signal Pw. , And a control circuit 32 (32C, 32D) for alternately selecting and outputting the transmission clock CL and the data DA (D7, D6... D1, D0) of the buffer memory 33 one bit at a time.

The receiving unit 4 (4C, 4D) includes a chip selection signal detection circuit 41 for detecting a chip selection signal CS in which the transmission signal 1b received from the transmission line 1 keeps the H level for a predetermined time. When the chip selection signal CS is detected, a pulse width detection circuit 45 that measures the clock pulse width Pw, and serial data (CL,
D7, CL, D6 ... CL, D1, CL, D0) to clock timing c1, c
Clock timing extraction means 42 (42A, 42B) for extracting 2
And predetermined timings (T1, T2) corresponding to the outputs c1, c2 of the clock timing extracting means 42 (42A, 42B).
The timing forming circuit 43 (43A, 43B) which outputs the write timing pulses w1, w2 with a delay, and the serial data (CL, D7, CL, CL) received by the timing pulses w1, w2 of the timing forming circuit 43 (43A, 43B). D6,... CL, D1, CL, D0) transmission data (D7, D6,... D1, D0) are written one bit at a time.

With this configuration, when the transmission interface circuit 2 (2C, 2D) receives a transmission request from the partner device, or receives a transmission request from the central processing unit 5 in its own device, the data (D7 , D6... D1, D0), the transmitting unit 3 (3C, 3D) switches the connection means 13 to the transmitting side, and divides the internal clock clk to form a transmission clock.
Based on CL, the chip select signal forming circuit 31 transmits a chip select signal CS, transmits a clock pulse width (Pw) signal,
Subsequently, the control circuits 32C and 32D store the transmission clock CL and the data (D7, D6... D1, D0) in the transmission data buffer memory 33 by one.
Select and control the bits of the serial data (CL, D7, C
L, D6... CL, D1, CL, D0) can be transmitted.

The control circuit 32 (32C, 32D) is a first control circuit 32A of the first embodiment or a second control circuit of the second embodiment.
After transmitting chip select signal CS, transmit clock
The transmission data 33a (D
7, D6... D1, D0) can be configured to include a delay circuit (not shown) for one transmission clock CL in a logical value circuit for alternately selecting one bit at a time.

With this configuration, a signal is provided between the chip select signal CS and the serial data (CL, D7, CL, D6... CL, D1, CL, D0).
The transmission clock Pw for pulse width measurement can be inserted. In addition, when there is no transmission request, the connection unit 13 is switched to the receiving side to stand by, and the receiving unit 4 (4C, 4D) monitors the presence or absence of the chip selection signal CS transmitted to the transmission path 1. . In this state, when the chip selection signal detection circuit 41 detects the chip selection signal CS, the pulse width detection circuit 45 measures the clock pulse width Pw and sets the timing delay times T1 and T2 of the timing forming circuit 43. Subsequently, the clock extracting means 42 (42A, 42B) outputs the subsequent serial data (CL, D7, CL, D6
···), the clock timings c1 and c2 are extracted, and the timing forming circuit 43 (43C, 43D) extracts the measured clock pulse width Pw from the extracted clock timings c1 and c2 in the first and second embodiments. The write timing pulses w1 and w2 are output at the timing delay times T1 and T2 set in the down counter described in the above section, and the serial data (CL, D7, CL, D6,.・)
The transmission data (D7, D6... D1, D0) can be written into the reception data buffer memory 44 bit by bit. That is, the clock pulse width detected by the clock pulse width detection circuit 45
Pw is multiplied by 5/2 or 2 times, the number of clocks of this value is set in the down counter D-CNT, the countdown is performed with the internal clock clk, the flag F is set with the count value of zero,
With this flag F, the transmit data (D7, D6,..., D1, D6) of the serial data (CL, D7, CL, D6,...) Is stored in the receive data buffer memory 44.
0) can be written bit by bit.

With this configuration, after receiving the chip select signal CS, the receiving side transmits the transmission clock signal transmitted subsequently.
CL pulse width signal Pw is measured, and the measured pulse width Pw
Is multiplied by a multiplication factor ((5/2), 2) determined in advance for each of the transmission methods of the first and second embodiments, thereby obtaining a time T1 from the extracted clock timings c1 and c2 to the write timings w1 and w2. , T2. Therefore, this measurement time
By controlling the delay time between the write timings w1 and w2 by T1 and T2, serial data transmission can be performed without being conscious of the transmission clock CL on the transmission side. (Embodiment 4) FIG. 11 shows an example of the configuration of transmission data.
FIG. 11A shows the configuration of transmission data according to the present invention, which is composed of a chip selection signal CS and a serial data section.
For example, in part of the transmission data of the serial data portion,
When the read / write command (R / W) is assigned, for example, the central processing unit (CPU) 5 of the apparatus shown in FIGS. 7 and 8 reads this read / write command (R / W), and the transmission interface circuit 2 This read / write command (R / W) from the processing unit (CPU) 5
In response, the connection means 13 can be switched and connected.
Therefore, serial data transmission can be performed in a one-wire system, instead of a two-wire to four-wire system as in the related art.

Also, of the transmission data consisting of the chip selection signal CS and the serial data part, the serial data part is divided into test data having a control data part, a data body and, if necessary, an error detection / correction means. And a part. With such a configuration, the header portion is composed of a chip selection signal CS as a start-up / synchronization signal, and a control data portion having address data and various control information, and is used for general data transmission such as a data bus configuration. can do. In this transmission method, a 1-bit clock signal is inserted before the transmission data, and the synchronization timing is set by this signal. Therefore, the transmission speed is reduced, but the data with high reliability of the clock synchronization is obtained. The transmission can be configured. (Embodiment 5) In FIGS. 9 and 10, a receiving unit 4E according to an embodiment of the present invention
A chip selection signal detection circuit 41 for detecting a chip selection signal CS in which 1b continues the H level for a predetermined time, and when detecting the chip selection signal CS, measures a clock pulse width Pw of the next transmission clock CL. A memory counter G16,
Set the count value of this memory counter G16,
A shift register G17 for shifting the set value by 1 bit to perform a halving operation, a pulse width (Pw) counter G18 with a reset function for up-counting the internal clock clk,
The comparator G19 compares the value obtained by calculating the value of the memory counter G16 by the shift register G17 by one-half and the count value of the PW counter G18, and the output of the comparator G19.
The counter G21 resets the count value of the Pw counter G18, and the counter G21 counts the output of this comparator G19 in quinary.
And with clock timing c1 to 5/2 clock width
Generates a write timing pulse w1 delayed by ((5/2) Pw), and this write timing pulse w1 transmits data from serial data (CL, D7, CL, D6 ... CL, D1, CL, D0).
Shift register G22 for sequentially writing DA (D7, D6 ... D1, D0)
And can be configured.

When the transmission data (D7, D6... D1, D0) written in the shift register G22 has a long data length, the shift registers G23, G24,
G25... And further to the central processing unit 5 for parallel data transfer. Also, a chip selection signal detection circuit
Reference numeral 41 denotes a counter G3 that counts with the internal clock clk from the internal clock circuit 21 and monitors an H level that continues for a longer period than the transmission clock signal CL, and includes a NOT element G1, an OR element G2, and an OR element G6. Transmission signal 1b from path 1
The reset circuit (47) resets the count value of the counter G3 and the like with the L level signal of the transmission signal 1b, and counts with the internal clock clk at the H level that continues for a long period of time. Flag F by value
And a differential operation element G4 that receives the flag F, outputs a reset signal reset to the reset circuit (47) with one internal clock clk, and resets the counter G3.

With this configuration, the counter G3 counts up with the internal clock clk while receiving the H level that continues for a long time from the transmission line 1, and sets the flag F when the counter G3 reaches a predetermined count value. Then, the differential operation element G4 outputs a chip selection signal (CS) 4c for one internal clock clk. This output 4c is fed back to the OR element G6 to form a reset signal reset and reset the counter G3. Thereafter, the flag F of the counter G3 is not output until an H-level signal that continues for a longer period than the transmission clock signal CL is received again as a transmission signal.

On the other hand, the output 4c of the differential operation element G4 sets the RS flip-flop G5,
The set signal 4c, the counter G7 and the differential operation element G4
Reset pulse 4b delayed by two clock periods
With this, a pulse output 4a is formed. This pulse output 4a is A
The ND element G9 ANDs the received signal 1b and forms a pulse 4d having a transmission clock width (Pw) shown in FIG. This pulse 4d is, on the one hand, a flip-flop G12 and an AND element G1
3, and the circuit of flip-flop G14 and AND element G15 forms pulses 4e, 4f of one internal clock clk width which are continuously output immediately after the output of pulse 4d goes to L level. On the other hand, the pulse 4d is applied to the internal clock clk by the AND element G11.
Is input to the memory counter G16, and the transmission clock width Pw is counted by counting up the period of the transmission clock width Pw. This count value is stored in the shift register (SR) G17
Is shifted by one bit with the above-mentioned pulses 4e and 4f, so that half of the count value of the memory counter G16 ((1/2)
Pw) is set in the shift register (SR) G17, and a half of the Pw transmission clock is received until the next chip selection signal CS, that is, an H level that is longer than the transmission clock signal CL is received.
The count value of ((1/2) Pw) can be held in the shift register (SR) G17.

The count value ((1/2) Pw) held in the shift register G17 is compared with the count value counted by the Pw counter G18 counted up by the internal clock clk by the comparator G19. G19 is (1/2) P from reset signal reset
A pulse 4g is output every w period and counted and delayed by the quinary counter G21 to form a delay time of T1 = (5/2) Pw. That is, the reset signal reset is output at the timing c1 extracted by the clock timing extracting means, and T1 = (5 /
2) At the time when the delay time of Pw has elapsed, the strobe signal STB is output, and the H and L levels of the serial data are
2 to transmit data (D7, D6 ... D1, D0)
Can be restored.

The above operation waveform is shown in FIG.
In FIG. 10, the time axis flows from left to right on the horizontal axis. The transmission signal 1a (= 1b), which is transmitted to the transmission path 1 in order from the top on the vertical axis,
The operation timing waveforms of the respective circuit portions are illustrated from the chip selection signals (CS) such as the set signal 4c, the reset pulse 4b, and the G5 pulse output 4a. FIG. 10 (B) shows the period of waveform 4f.
The (CL, D7) part is zoomed up, and the period (CL, D7) of the received data 1b is sequentially
clk, and then the input waveform 4g of the quinary counter G21 and the output waveform STB of the quinary counter G21 are illustrated. With this STB signal, the data D7 of the received data 1b can be written to the shift register G22.

In the first to fourth embodiments, the transmission signal received via the transmission line 1 is used as the clock timing extracting means.
The method of detecting the predetermined rising or falling position of the transmission clock during 1a (= 1b) has been described using the rising or falling edge for the sake of simplicity. From a viewpoint, practically, data can be written into the RS-FF by the internal clock clk using the RS flip-flop (RS-FF).

In the transmission method of the present invention, a 1-bit clock signal is inserted before transmission data, and the synchronization timing is set by this signal. Therefore, the transmission speed is reduced, but the clock synchronization is not performed. Highly reliable data transmission can be configured. Further, by using the serial data transmission method described in the third embodiment and the transmission interface circuit described in the third embodiment, the period of the transmission clock of the transmission data can be appropriately changed, so that the third party from the transmission line 1 can be used. To prevent wiretapping.

[0066]

As described above, according to the present invention, in a one-wire serial data transmission method and a transmission interface circuit using the method, data transmission can be performed without lowering the noise margin, and The number of pins can be reduced.

[Brief description of the drawings]

FIG. 1 is a transmission waveform diagram illustrating a serial data transmission method according to a first embodiment of the present invention.

FIG. 2 is a transmission waveform diagram illustrating a serial data transmission method according to a second embodiment.

FIG. 3 is a transmission waveform diagram having a pulse width measurement signal in the first embodiment.

FIG. 4 is a transmission waveform diagram having a pulse width measurement signal in the second embodiment.

FIG. 5 is a timing operation diagram for restoring transmission data from serial data of the first embodiment in a receiving unit.

FIG. 6 is a timing operation diagram for restoring transmission data from serial data of the second embodiment in a receiving unit.

FIG. 7 is a block diagram of a transmission interface circuit according to the first and second embodiments.

FIG. 8 shows a first example having a pulse width detection circuit of a transmission clock.
-Block diagram of the transmission interface circuit of the second embodiment

FIG. 9 is a block diagram of a transmission interface circuit according to another embodiment.

FIG. 10 is an operation waveform diagram illustrating an operation of another embodiment.

FIG. 11 is a configuration diagram illustrating a configuration of a transmission signal transmitted on a transmission path according to the present invention.

FIG. 12 is an explanatory diagram of a conventional 4-wire serial data transmission method.

FIG. 13 is a waveform diagram of a conventional time-division data communication system.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Transmission line 1a, 1b, 1c Transmission signal 13 Connection means 2, 2A, 2B, 2C Transmission interface circuit 21 Internal clock circuit 22 Divider circuit 3, 3A, 3B, 3C Transmitter 31 Chip selection signal forming circuit 32A, 32B, 32C, 32D control circuit 33 Transmission data buffer memory 4, 4A, 4B, 4C receiver 41 Chip selection signal detection circuit 42 Clock timing extraction means 43 Timing formation circuit 44 Received data buffer memory 45 Pulse width detection circuit 5 Central processing unit CL transmission clock clk internal clock DA, D7, D6 ... D1, D0 transmission data Pw transmission clock pulse width c1, c2 transmission clock timing w1, w2, STB write timing T1, T2 delay time G1, G2, G6, G9, G11 , G13, G15, G20 Logic element G3, G7, G16, G18, G21 Counter G4, G8 Differential operation element G5, G12, G14 Flip-flop G17, G22 Shift register G19 Comparator 4a, 4b, 4c, 4d, 4e, 4f , 4g signal

Claims (13)

[Claims] 1. A serial data transmission method in which a transmission side mixes a data with a clock signal and transmits the data, a reception side extracts a clock timing, and reconstructs a transmission side data bit string from a serially received transmission signal. When transmitting data to the transmission path, the transmitting side outputs a chip selection signal (CS) that outputs an H level that lasts longer than the clock signal and then outputs an L level, and after this chip selection signal, Serial data obtained by alternately selecting and converting one return zero (RZ) type clock signal and one return bit (RZ) type data from the first bit to the last bit of the transmission data. When the receiving side receives the chip select signal (CS) from the transmission signal transmitted on the transmission path, it extracts the clock timing from the subsequent serial data, and The transmitted data is written in the serial data bit by bit buffer memory at write timing a predetermined time delay from the clock timing, the serial data transmission method characterized by. 2. A serial data transmission method in which a clock signal is mixed with data on a transmission side and transmitted, a clock timing is extracted on a reception side, and a data bit string on the transmission side is reconstructed from transmission signals received serially. When transmitting data to the transmission path, the transmitting side outputs a chip selection signal (CS) that outputs an H level that lasts longer than the clock signal and then outputs an L level, and after this chip selection signal, Serial data obtained by alternately selecting one return zero (RZ) type clock signal and non-return zero (NRZ) type data of transmission data, one bit at a time from the first bit to the last bit. When the receiving side receives the chip select signal (CS) from the transmission signal transmitted on the transmission path, it extracts the clock timing from the subsequent serial data, and The transmitted data is written in the serial data bit by bit buffer memory at write timing a predetermined time delay from the clock timing, the serial data transmission method characterized by. 3. The serial data transmission method according to claim 1, wherein the transmission data includes a pulse width signal for measuring a clock pulse width between the chip selection signal (CS) and the serial data. A serial data transmission method, comprising: 4. A transmission interface circuit using the serial data transmission method according to claim 1 or 2, wherein: an internal clock circuit; a frequency dividing circuit for dividing the internal clock to form a transmission clock; A transmission unit controlled by the transmission clock to output a transmission signal to a transmission line, a reception unit receiving the transmission signal transmitted from the transmission line by an internal clock, restoring transmission data on the transmission side, and writing the data into a buffer memory; Connection means for connecting a transmission unit and a reception unit to a transmission line, the transmission unit comprising: a transmission data buffer memory; a chip selection signal forming circuit; and, after transmitting the chip selection signal, the transmission clock and the buffer memory. And a control circuit for alternately selecting and outputting the transmission data in the data bit by bit. A chip selection signal detection circuit for detecting a chip selection signal that keeps the H level for a predetermined time, a clock extraction means for extracting a clock timing from the subsequent serial data when the chip selection signal is detected, A timing forming circuit for outputting a write timing pulse with a predetermined timing delay corresponding to the output of the means, and a reception data buffer memory for writing transmission data of serial data received by the timing pulse of the timing formation circuit one bit at a time And a transmission interface circuit. 5. A transmission interface circuit using the serial data transmission method according to claim 1 or 2, wherein an internal clock circuit and a component for dividing the internal clock to form a transmission clock. A transmission circuit which is controlled by the transmission clock and outputs a transmission signal to a transmission path, receives the transmission signal transmitted from the transmission path by an internal clock, restores transmission data on the transmission side, and writes the data in a buffer memory A receiving unit, and a connecting unit for connecting the transmitting unit and the receiving unit to a transmission line, the transmitting unit comprising: a transmission data buffer memory; a chip selection signal forming circuit; and a clock after transmitting the chip selection signal. A pulse width measurement signal is output, and the transmission clock and the transmission data in the buffer memory are alternately selected and output one bit at a time. And a receiving unit, wherein the receiving unit detects a chip selection signal detection circuit for detecting a chip selection signal in which a transmission signal received from the transmission path keeps the H level for a predetermined time, and when detecting the chip selection signal, A pulse width detection circuit for measuring a clock pulse width; clock timing extraction means for extracting clock timing from subsequent serial data; and a write timing pulse delayed by a predetermined timing corresponding to the output of the clock timing extraction means. A timing forming circuit to be output, and transmitting data of serial data received by a timing pulse of the timing forming circuit to 1
A transmission interface circuit, comprising: a reception data buffer memory for writing bit by bit. 6. The transmission interface circuit according to claim 4, wherein the control circuit selects data in the transmission data buffer memory one bit at a time by a transmission clock formed by dividing an internal clock. And a first control circuit that takes a logical product with the transmission clock and alternately selects and outputs the logical product output and the transmission clock. 7. The transmission interface circuit according to claim 4, wherein the control circuit comprises: a transmission clock formed by dividing an internal clock; and a data in a transmission data buffer memory using the transmission clock. And a selector circuit (second control circuit) for alternately selecting and outputting one bit at a time. 8. The transmission interface circuit according to claim 5, wherein the control circuit has a first control circuit or a second control circuit,
A transmission interface, comprising: a logical value circuit that transmits two chip clocks of only the first transmission clock after transmitting the chip selection signal, and then alternately selects transmission data bit by bit from a transmission data buffer memory. circuit. 9. The transmission interface circuit according to claim 4, wherein the clock extracting means for extracting clock timing from the serial data is configured such that transmission data of a transmission signal is return zero (RZ) type data. Clock, the clock is extracted at the rising timing of the serial data clock, and the predetermined write timing pulse of the timing forming circuit is delayed by 5/2 transmission clock pulse width with respect to the extracted clock rising timing. A transmission interface circuit for outputting the data. 10. The transmission interface circuit according to claim 4, wherein the clock extracting means for extracting clock timing from the serial data is configured such that transmission data of a transmission signal is non-return-to-zero (NRZ) type data. The clock is extracted at the rising or falling timing of the clock in the central part of the serial data clock, and the predetermined write timing pulse of the timing forming circuit is used to change the extracted timing of the central part of the clock. 2. The transmission interface circuit according to claim 1, wherein the output is delayed by two transmission clock pulse widths. 11. The transmission interface circuit according to claim 9, wherein the clock extracting means and the timing forming circuit have an internal circuit corresponding to a predetermined 5/2 transmission clock pulse width or 2 transmission clock pulse widths. A down counter for the number of clocks is provided. At the clock timing extracted by the clock extracting means, the number of the internal clocks is set in the down counter, the internal clock counts down, a flag is set at a count value of zero, and the reception data is set at the flag. A transmission interface circuit which writes transmission data of serial data to a buffer memory one bit at a time. 12. The transmission interface circuit according to claim 5, wherein the clock pulse width detected by the clock pulse width detection circuit is multiplied by 5/2 or 2 and the number of clocks of this value is down-counted. Set to
A transmission interface circuit which counts down by an internal clock, sets a flag with a count value of zero, and writes serial data transmission data one bit at a time in a reception data buffer memory using the flag. 13. The transmission interface circuit according to claim 5, wherein the receiving section detects a chip selection signal in which a transmission signal received from the transmission path keeps the H level for a predetermined time. When this chip selection signal is detected, a memory counter for measuring the clock pulse width of the next transmission clock and the count value of this memory counter are set, and the set value is shifted by one bit to perform a 1/2 operation. A shift register, a pulse width (Pw) counter with a reset function for up-counting the internal clock, and comparing the count value of the memory counter calculated by half of the shift register with the count value of the pulse width (Pw) counter. And the output of this comparator reset the count value of the up-counter. And a shift register that generates a write timing pulse delayed by 5/2 clock width from the clock timing, and sequentially writes transmission data of serial data with the write timing pulse. Transmission interface circuit.