JP2002330435A - Encoding circuit and encoding method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provides an encoding method and an encoding circuit, which consumes a reduced power at the variable length coding. SOLUTION: This encoding circuit includes an EOB detector 105 between a quantizer 101 and an encoder 104, for detecting the rearmost non-zero quantized coefficients in a processing target block and outputting the position of the detected end as a control signal 110. The encoder 104 performs a variable length coding process for the quantized coefficients up to the position indicated by the control signal, added an EOB code, and pauses the variable length coding process.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an encoding circuit in a digital signal recording / reproducing apparatus such as a video tape recorder or a video disk recorder for digitally recording and reproducing a video signal and an audio signal, and a method of encoding the same. The present invention relates to an encoding circuit in a digital signal recording / reproducing apparatus for performing transmission and accumulation using variable length encoding, and an encoding method thereof.

[0002]

2. Description of the Related Art In order to reduce the size of a digital signal recording / reproducing apparatus, it is necessary to compress and record an enormous amount of information of a digital video signal input to the apparatus. As a method of compressing (encoding) a digital video signal, motion compensation prediction, orthogonal transform, particularly, discrete cosine transform (DCT), a method of band division, a sampling by quantization, Furthermore, Variable Length Coding such as Huffman coding (Variable Length C)
oding: VLC), arithmetic coding, and the like. The digital signal recording / reproducing apparatus transmits or accumulates a digital video signal compressed by the above-described compression method.

[0003] FIG. 15, FIG. 13 (a), FIG.
An encoding circuit in the conventional digital signal recording / reproducing apparatus will be described with reference to FIG. FIG. 15 is a diagram showing a configuration of a conventional encoding circuit.
FIG. 13A is a diagram illustrating an output order when block-wise data is output in a horizontal direction, and FIG. 13B is a diagram illustrating a scan order when zigzag scanning is performed on data in block units. .

[0004] As shown in FIG.
T501, a quantizer 502, a memory 503, and an encoder 504. First, input data is DCT50.
1, the DCT 501 converts the input data to DC
After performing the T processing, the DCT coefficient is output to the quantizer 502 at the subsequent stage. Then, the quantizer 502 quantizes the DCT coefficients and outputs the quantized DCT coefficients to the memory 503 in the output order shown in FIG. The memory 503 is a single-port memory having a two-bank configuration. When the quantized coefficients for one block are accumulated, the memory 503 is automatically toggled. Output
The next one block of quantized coefficients sequentially transmitted is stored.

[0005] The quantized coefficient for one block output from the memory 503 is encoded by an encoder 504 as shown in FIG.
As shown in (b), after data is rearranged by zigzag scanning in block units, the number (runs) of leading zero quantized coefficients, the value (level) of nonzero quantized coefficients, and Are subjected to two-dimensional variable length coding,
Further, an EOB (End Of Block) code indicating the end of valid data in the block is added to the last non-zero quantized coefficient in the block.
Note that here, the memory 503 is a single-port memory having a two-bank configuration, but may be a dual-port memory having a one-bank configuration.

[0006]

However, when the conventional digital signal recording / reproducing apparatus has a configuration as shown in FIG. 15, when the encoder 504 performs two-dimensional variable length coding, it always blocks. If the zigzag scan is not performed until the end of the block, the last non-zero quantization coefficient in the block cannot be determined, so that there is much waste in terms of power consumption. The present invention has been made in view of such a problem, and provides an encoding method capable of reducing power consumption when performing variable-length encoding or performing quantization, and an encoding circuit thereof. The purpose is to:

[0007]

In order to solve the above-mentioned problems, an encoding circuit according to the present invention (claim 1) comprises a frequency conversion means for converting data of a processing target block into a frequency component; , And encoding means for performing variable-length encoding of the quantized frequency components in a predetermined scanning order. EOB detection means for detecting the position of the quantized frequency component in the predetermined scan order, and outputting the position as a control signal to the encoding means, wherein the encoding means indicates the control signal indicated by the control signal. The quantized frequency component up to the position in the predetermined scan order is subjected to variable length coding, an EOB code indicating the final position of the effective component is added, and the variable length coding process is performed. It is intended to pause.

The encoding circuit according to the present invention (claim 2) is the encoding circuit according to claim 1, wherein
The OB detecting means is provided between the memory for temporarily storing the quantized frequency components of the processing target block from the quantizing means and outputting the quantized frequency components in the predetermined scanning order, and the encoding means. A counter for detecting the position of the quantized frequency component input from the memory; a comparator for comparing whether the quantized frequency component is 0; A buffer for storing a value of the frequency component; and a register for holding a position of the quantized frequency component other than 0 based on a result of the comparator.

Further, the encoding circuit according to the present invention (claim 3) is the encoding circuit according to claim 1, wherein
The OB detecting means is provided between the quantizing means and a memory for temporarily storing the quantized frequency components of the block to be processed from the quantizing means. A counter for detecting the position of the quantized frequency component, a first comparator for comparing whether or not the quantized frequency component is 0, and a value of the quantized frequency component , A conversion table for converting the value of the counter into a value in the predetermined scanning order, and a result of the first comparator,
A register for holding a position of the non-zero quantized frequency component in a predetermined scan order, and a position held in the register being the last non-zero quantized frequency component of the processing target block. And a second comparator for comparing whether or not the position is in a predetermined scanning order.

Further, the encoding circuit according to the present invention (claim 4) is the encoding circuit according to claim 1, wherein
The OB detection means is provided between the frequency conversion means and the quantization means, and detects a position of a frequency component inputted from the frequency conversion means, the frequency component, and the quantification means. A first comparator that compares a quantized value that is a divisor for dividing the frequency component, a conversion table that converts the value of the counter into a value in the predetermined scan order, Based on the result, a register that holds the position of the non-zero quantized frequency component in a predetermined scan order, and a position that is held in the register is the last non-zero quantized frequency component of the processing target block. And a second comparator for comparing whether or not the frequency components are located in the predetermined scanning order.

Further, the encoding circuit according to the present invention (claim 5) comprises a frequency conversion means for frequency-converting the data of the block to be processed into a frequency component; a quantization means for quantizing the frequency component; Encoding means for performing variable-length encoding of the converted frequency components in a predetermined scan order, wherein the predetermined non-zero quantized frequency component at the end of the processing target block is And EOB detection means for detecting the position in the scan order as a control signal and outputting the position as a control signal to the quantization means and the encoding means, wherein the quantization means comprises: , Quantizes the frequency component up to the position of, and suspends the quantization process. And variable-length coding to the frequency components, adding EOB code indicating the end position of the active ingredient is for pausing the variable length coding process.

Further, the encoding circuit according to the present invention (claim 6) is the encoding circuit according to claim 5, wherein
The OB detection means is provided between the frequency conversion means and the quantization means, and temporarily holds the frequency components of the processing target block from the frequency conversion means and outputs the frequency components in the predetermined scan order. Memory, a counter for detecting the position of the frequency component input from the memory in the predetermined scan order, A first comparator to be compared, a buffer for storing the value of the frequency component, and a position of the non-zero quantized frequency component in a predetermined scan order based on the result of the first comparator. Holding registers.

The encoding method according to the present invention (claim 7) includes a frequency conversion step of frequency-converting data of a processing target block into a frequency component, a quantization step of quantizing the frequency component, and the quantization step. An EOB detection step of determining whether or not the quantized frequency component is zero, and detecting the position of the tail of the processing target block in a predetermined scan order of the non-zero quantized frequency component; An EOB code indicating that the quantized frequency component up to the position in the predetermined scanning order of the frequency component detected in the EOB detection step is variable-length coded to indicate the final position of the effective component. And add
And an encoding step for suspending the variable-length encoding process.

Further, in the encoding method according to the present invention (claim 8), a frequency conversion step of frequency-converting the data of the processing target block into a frequency component, and dividing the frequency component in the quantization process with the frequency component. An EOB detection step of comparing a quantized value which is a divisor to detect the position of the last non-zero quantized frequency component in the predetermined scan order at the end of the processing target block; And a variable length encoding of the quantized frequency component up to a position in the predetermined scan order of the frequency component detected in the EOB detection step, and a final position of the effective component And an encoding step of suspending the variable length encoding process by adding an EOB code indicating that

The encoding method according to the present invention (claim 9) includes a frequency conversion step of frequency-converting the data of the processing target block into a frequency component;
In the quantization process, the position of the last non-zero quantized frequency component in the predetermined scan order is detected by comparing with a quantized value which is a divisor for dividing the frequency component. An EOB detection step;
A quantization step of quantizing the frequency components up to a position in the predetermined scan order of the frequency components detected in the B detection step, and suspending the quantization process; and a predetermined scan order of the frequency components. An encoding step of performing variable-length encoding on the quantized frequency component up to the position of, adding an EOB code indicating the final position of the effective component, and suspending the variable-length encoding process; It has.

The encoding program according to the present invention (Claim 10) allows a computer to frequency-convert and quantize data of a block to be processed and to convert the quantized frequency components into variable length data in a predetermined scanning order. An encoding program for executing a process of encoding, wherein a frequency conversion step of frequency-converting the data of the processing target block into a frequency component, a quantization step of quantizing the frequency component, and An EOB detection step of determining whether or not the frequency component is zero, and detecting a position of the last non-zero quantized frequency component in the predetermined scan order at the end of the processing target block; Variable for the quantized frequency component up to a position in the predetermined scan order of the frequency component detected in the detection step By encoding adds EOB code indicating the end position of the active ingredient, it is intended to include a coding step of pausing the variable length coding process.

The encoding program according to the present invention (claim 11) allows a computer to frequency-convert and quantize data of a processing target block and to convert the quantized frequency components into variable-length data in a predetermined scanning order. An encoding program for executing an encoding process, comprising: a frequency conversion step of frequency-converting data of a processing target block into a frequency component; and a divisor for dividing the frequency component in the quantization process. An EOB detecting step of comparing a non-zero quantized frequency component at the end of the block to be processed in the predetermined scan order by comparing the quantized value with a certain quantized value; And a quantization step, wherein the frequency component detected in the EOB detection step is located up to a position in a predetermined scanning order. And variable length coding with respect to Coca frequency component, E indicating the end position of the active ingredient
A coding step of adding an OB code and suspending the variable-length coding process.

The encoding program according to the present invention (claim 12) allows a computer to perform frequency conversion and quantization on data of a block to be processed and to convert the quantized frequency components into variable length data in a predetermined scanning order. An encoding program for executing an encoding process, a frequency conversion step of frequency-converting data of a processing target block into a frequency component, and a divisor for dividing the frequency component and the frequency component in the quantization process. An EOB detecting step of comparing the quantized value with the quantized value to detect a position of the last non-zero quantized frequency component in the predetermined scan order, and an EOB detecting step. The frequency components up to the position of the frequency component in the predetermined scanning order are quantized, and the quantization process is paused. And a variable length encoding of the quantized frequency component up to a position in the predetermined scanning order of the frequency component, and adding an EOB code indicating the final position of the effective component. And an encoding step for pausing the variable length encoding process.

[0019]

Embodiments of the present invention will be described with reference to the drawings. (Embodiment 1) An encoding circuit according to Embodiment 1 will be described below with reference to the drawings. FIG. 1 is a diagram illustrating a configuration of an encoding circuit according to Embodiment 1 of the present invention, and FIG. 2 is a diagram illustrating a detailed configuration of an EOB detector in FIG.

As shown in FIG. 1, the encoding circuit according to the first embodiment performs a DCT process on data.
T101, a quantizer 102 for quantizing data from the DCT 101, a memory 103 for temporarily holding data from the quantizer 102 and outputting the data in a zigzag order, and a last non-zero value in the processing target block EOB detector 10 which detects the position of and outputs it as control signal 110
5 and an encoder 104 for performing variable-length encoding.

As shown in FIG. 2, the EOB detector 105 according to the first embodiment includes a comparator 1051 for comparing whether input data is 0 or not, and a number of input data from the beginning. A counter 1052 for counting whether the data is eye data, a selector 1053 for selecting a value to be held in the register 1055 based on a result of the comparator 1051, and an N-stage shift for storing data input from the memory 103 for one block. A register 1054;
It is provided with.

Next, FIGS. 3, 13 (a) and 13
The operation of the encoding circuit according to the first embodiment will be described with reference to (b) and FIG. FIG. 3 is a flowchart showing a series of operations of the encoding circuit according to the first embodiment. FIG. FIG.
FIG. 2B is a diagram illustrating an example of a case where data of one block is scanned in a zigzag order. Here, the data input to the encoding circuit is a digital video signal in which one block is composed of N pixel data.

First, the data input to the encoding circuit is:
DCT 101 converts the data into DCT coefficients (step s11). Then, the DCT coefficients output from the DCT 101 in the horizontal feed order indicated by the arrow in FIG. 13A are quantized in the quantizer 102 (A in FIG. (Step s
13).

This memory 103 is a single-port memory having a two-bank configuration. When one block of the quantized coefficient quantized by the quantizer 102 is accumulated, the memory is switched, and the data of the next block data sequentially input is stored. The quantization coefficients are stored in the switched bank. And
At the same time, the quantization coefficients for one block stored in the memory 103 are read in a zigzag order indicated by an arrow in FIG. The state of writing and reading of data in the memory 103 is shown in FIG.

In the EOB detector 105, first, the memory 10
3 is output to the counter 1052, the comparator 1051, and the N-stage shift register 1054. Then, the counter 1052 counts the number of the read data from the top of the block to be processed, and the comparator 1051 counts the value of the data read from the memory 103 one pixel at a time. Is compared with zero (step s1).
4) The result is output to the selector 1053, and the N-stage shift register 1054 holds the read data.

Here, when the read data is zero in the comparator 1051 (when “0” is output from the comparator 1051), the selector 1053 selects the value held in the register 1055. On the other hand, when the read data is not zero in the comparator 1051 (when “1” is output from the comparator 1051), the selector 1053 selects the value of the counter 1052 at that time and holds the value in the register 1055. (Step s15).

That is, in the first embodiment, the quantization coefficients are read from the memory 103 in a zigzag order and
Since it is input to the OB detector 105, the counter 1052
Is input to the register 1055, the counter 10
The value of 52 indicates the zigzag order from the beginning of the block of the read data, whereby the encoder 104 that scans in the zigzag order and performs variable-length encoding on the zigzag order has the zero at the end of the block. Can be indicated.

Whether the read data is the last data of the block to be processed is determined here because one block is composed of N pieces of pixel data. (Step s16), and when the data is not the last data (when the value of the counter 1052 is ≠ N), the process returns to Step s14 again to repeat the above-described operation, and when the read data is the last data of the block ( Counter 1052
, The value held in the register 1055 at that time is output to the encoder 104 as the control signal 110 (step s17). At the same time, the one-block quantized coefficients held in the N-stage shift register 1054 are output to the encoder 104 (step s).
17). At the same time, the value of the counter 1052 and the value of the register 1055 are set to 1 and initialized.

In the encoder 104, the EOB detector 1 is used.
The variable length coding is performed on the quantized coefficients for one block output from the block 05. At this time, the position of the last non-zero quantized coefficient in the block is detected from the control signal 110 output from the EOB detector 105, and the variable-length encoding process is performed up to the quantized coefficient at the detected position. , After variable-length encoding of the last non-zero quantized coefficient,
An OB (End Of Block) code is added, and the operation of the encoder 104 is stopped until data of the next block is input from the EOB detector 105 (step s).
18). This eliminates the need for the encoder 104 to perform variable-length encoding on all data in one block, thereby reducing power consumption of the encoding circuit.

As described above, according to the first embodiment,
An EOB detector 105 is provided between the memory, 103, and the encoder 104. The EOB detector 105 detects the last non-zero quantized coefficient in the block to be processed, and detects the last zero. Is not a quantized coefficient,
A value indicating the number of data in the zigzag order from the head of the block is output to the encoder 104 as a control signal 110, and the encoder 104 outputs the last data from the control signal 110 based on the control signal 110. When the position of the non-zero quantized coefficient is detected, variable-length coding is performed on the quantized coefficient up to the detected position, an EOB code is added to the last non-zero quantized coefficient, and Since the operation is suspended until the quantized data is input from the EOB detector 105, it is possible to reduce power consumption when performing variable-length encoding in the encoder 104. As a result, power consumption can be reduced in the encoding circuit without adversely affecting image quality.

Although the memory 103 is a single-port memory having a two-bank configuration in the first embodiment, the same effect can be obtained even if the memory 103 is a dual-port memory having a one-bank configuration. Can be further,
In the first embodiment, DCT processing has been described as an example of a method of frequency-converting data input to the encoding circuit. However, the present invention is not limited to this. Any method may be used as long as it performs frequency conversion. Further, in the first embodiment, an example is described in which the scan order when quantizing data after DCT processing is performed in a zigzag order, but any scan order may be used. What is necessary is just to select the scan order according to the characteristics of the data input to the circuit.

(Embodiment 2) An encoding circuit according to Embodiment 2 will be described below with reference to the drawings. In the first embodiment, the case where the EOB detector 105 is provided between the memory 103 and the encoder 104 has been described. In the second embodiment, the EOB detector is a quantizer and a memory. A description will be given of the case provided between.

First, the configuration of the encoding circuit according to the second embodiment will be described with reference to FIGS. FIG.
5 is a diagram illustrating a configuration of an encoding circuit according to Embodiment 2 of the present invention, and FIG. 5 is a diagram illustrating a detailed configuration of an EOB detector in FIG. As shown in FIG. 4, the encoding circuit according to the second embodiment performs
A DCT 201 for performing a CT process, a quantizer 202 for quantizing data from the DCT 201, an EOB detector 205 for detecting the position of the last non-zero value in the processing target block and outputting the detected position as a control signal 220; It comprises a memory 203 for temporarily storing data from the quantizer 202 and outputting the data in a zigzag order, and an encoder 204 for performing variable length coding.

Then, as shown in FIG. 5, the EOB detector 205 according to the second embodiment includes a first comparator 2051 for comparing whether input data is 0 or not, and an input data A counter 2052 for counting the number of data from the beginning of the block to be processed,
A data processing order-zigzag order conversion table 2 for converting the read order from the first data of the horizontally fed output data to the order when read in the zigzag order from the first data
056 and a second value for selecting a larger value from the input values.
And a selector 2053 for selecting a value to be held in the register 2055 based on the result of the first comparator 2051.

Next, referring to FIG. 6 and FIG.
The operation of the encoding circuit according to the second embodiment will be described. FIG. 6 is a flowchart showing a series of operations of the encoding circuit according to the second embodiment, and FIG.
Is the data processing order and the corresponding zigzag order, DC
9 is a table showing T coefficients and values held in registers at that time.

Here, the data input to the encoding circuit is a digital video signal in which one block is composed of N pixels, and the data processing order-zigzag order conversion table 2056 is, for example, as shown in FIG. ) In the upper two rows. For example, the data order from the head is converted such that the third data from the head is the data in the horizontal feed and the sixth data from the head in the zigzag order. Is what you do.

First, the data input to the encoding circuit is converted into DCT coefficients in the DCT 201 (step s21). Then, the DCT coefficients output from the DCT 201 in the output order of the horizontal feed indicated by the arrow in FIG. Are output to the EOB detector 205 and the memory 203 (A in FIG. 4). This memory 203 is a single-port memory having a two-bank configuration,
Is stored in one bank for one block of quantized coefficients, and then the banks are switched to sequentially store data.

In the EOB detector 205, first, the quantizer 2
02 is output to the counter 2052 and the first comparator 2051. And counter 2
At 052, the number of the read data from the beginning of the block to be processed is counted, and the first comparator 2051 reads one pixel at a time from the quantizer 202. A comparison is made as to whether the data value is zero (step s23), and the result is output to the selector 2053.

When the read data is zero in the first comparator 2051 (when “0” is output from the first comparator 2051), the data is held in the register 2055 in the selector 2053. If the read data is not zero in the first comparator 2051 (the first comparator 2
If “1” is output from the address 051), the value of the counter 2052 at that time is converted in a zigzag order using the data processing order-zigzag order conversion table 2056 (step s).
24), the second comparator 2054 compares the converted zigzag order with the value held in the register 2055 and selects the larger value (step s2).
5) At that time, the value selected by the second comparator 2054 is held in the register 2055 (step s26).

That is, in the second embodiment, since the quantized coefficients are output from the quantizer 202 in the traverse order as shown by the arrow in FIG. This indicates the horizontal feed order from the top of the block of data that has been set. On the other hand, the encoder 20
In 4, the data of one block is scanned in zigzag order as indicated by the arrow in FIG. Therefore, in order to indicate to the encoder 204 the position of the last non-zero quantized coefficient in the block, the value of the counter 2052 must be converted in the corresponding zigzag order.

Therefore, when the data read from the quantizer 202 is not zero in the first comparator 2051, the value of the counter 2052 is converted in a zigzag order by using the conversion table 2056. Because the value read first in the zigzag order may be read later in the horizontal feed order due to the difference in the scan order for the blocks in the zigzag order and the horizontal feed order, the second comparator 2054 holds the value in the register 2055. The selected value is compared with the value converted by the conversion table 2056, and the larger value is selected.
055, whereby the encoder 204 that scans in zigzag order and performs variable-length encoding can detect the position of the non-zero quantization coefficient at the end of the block.

Whether or not the read data is the final data of the block to be processed is determined by determining whether the value of the counter 2052 is N since one block is composed of N pixel data. If not (step s27), if the data is not the last data (if the value of the register 2055 is ≠ N), the process returns to step s23 again and repeats the above-described operation. If the read data is the last data of the block In the case of (the value of the register 2055 = N), the value held in the register 2055 at that time is output to the encoder 204 as the control signal 210 (step s28). At the same time, the counter 10
The value of the register 52 and the value of the register 1055 are set to 1 for initialization.

In the memory 203 in which the data for one block is stored from the quantizer 202, the quantization coefficient of the data of the next block which is sequentially input by performing bank switching is stored, and at the same time, the stored data is stored. The quantized coefficients for one block are read out in a zigzag order indicated by an arrow in FIG. 13B and output to the encoder 204 (B in FIG. 4). FIG. 14 shows a state of writing and reading data in the memory 203.

In the encoder 204, the quantized coefficients for one block output from the memory 203 are variable-length coded. At this time, the position of the last non-zero quantized coefficient in the block is detected from the control signal 210 output from the EOB detector 205, and variable-length coding is performed on the quantized coefficient at that position. Then, an EOB code is added to the last value subjected to the variable length coding, and the encoder 204 is stopped until the data of the next block is input from the EOB detector 205 (step s29). ). By doing so, the encoder 204 will be 1
It is not necessary to perform variable-length encoding on all data of the block, and the power consumption of the encoding circuit can be reduced.

As described above, according to the second embodiment,
An EOB detector 205 is provided between the quantizer 202 and the memory 203. The EOB detector 205 detects the position of the last non-zero quantization coefficient in the block to be processed in the zigzag order. Is output to the encoder 204 as a control signal 210. When the encoder 204 detects the position of the last non-zero quantization coefficient by the control signal 210, the detected position Variable-length coding is performed on the quantized coefficients up to and
Since the OB code is added and the operation is suspended until the quantized data of the next block is input from the quantizer 202, the consumption at the time of performing the variable length encoding in the encoder 204 is performed. Power can be reduced, and as a result, power consumption can be reduced in the encoding circuit without adversely affecting image quality.

In the second embodiment, the memory 203 is a single-port memory having a two-bank configuration. However, the same effect can be obtained even if the memory 203 is a dual-port memory having a one-bank configuration. Can be

Further, according to the second embodiment, DC input is performed as a method of frequency-converting data input to the encoding circuit.
Although the T process has been described as an example, the present invention is not limited to this, and any method may be used as long as it performs frequency conversion on data input to the encoding circuit. Also, the encoder 20
The scan order for variable-length encoding in 4 is as follows.
Here, an example in which zigzag order is performed has been described, but any scan order may be used, and a scan order according to the characteristics of data input to the present encoding circuit may be selected. In this case, the conversion table 2056 in the EOB detector 205 needs to be a table that converts the value of the counter 2052 (data processing order) into a scan order according to data characteristics.

(Embodiment 3) An encoding circuit according to Embodiment 3 will be described below with reference to the drawings. In the third embodiment, a case where the EOB detector is provided between the DCT and the quantizer will be described.

First, the configuration of the encoding circuit according to the third embodiment will be described with reference to FIGS. FIG.
FIG. 8 is a diagram illustrating a configuration of an encoding circuit according to Embodiment 3, and FIG. 8 is a diagram illustrating a detailed configuration of an EOB detector in FIG.

As shown in FIG. 7, the encoding circuit according to the third embodiment includes a DCT 301 for performing DCT processing on input data, and a control signal indicating the position of the last non-zero value in the processing target block. An EOB detector 305 output as 310, a quantizer 302 for quantizing the data from the DCT 301, and a quantizer 302
And a coder 304 for temporarily storing data from and outputting the data in a zigzag order, and an encoder 304 for performing variable length coding.

Then, as shown in FIG. 8, the EOB detector 305 according to the third embodiment includes a data read from the DCT 301 and a quantized value 311 which is a divisor when the quantizer 302 quantizes the data. , A counter 3052 for counting the number of the read data from the head of the processing target block, and a counter 3052 for counting the data output in the horizontal feed order. A data processing order-zigzag order conversion table 3056 for converting the order of reading from the first data to the order when reading is performed in the zigzag order from the first data;
Second comparator 3 for selecting a larger value from the input values
054 and a selector 3 for selecting a value to be held in the register 3055 based on the result of the first comparator 3051
053).

Next, the operation of the encoding circuit according to the third embodiment will be described with reference to FIG. FIG. 9 is a flowchart showing a series of operations of the encoding circuit according to the third embodiment.

Here, the data input to the encoding circuit is a digital video signal in which one block is composed of N pixels. ) In the upper two rows. For example, the data order from the head is converted such that the third data from the head is the data in the horizontal feed and the sixth data from the head in the zigzag order. Is what you do.

First, the data input to the encoding circuit is converted into DCT coefficients in the DCT 301 (step s31). Then, the DCT coefficients output from the DCT 301 in the horizontal feed output order indicated by the arrow in FIG. 13A are input to the EOB detector 305 and the quantizer 302 (A in FIG. 7).

In the EOB detector 305, first, the DCT 30
The data read from 1 is output to the counter 3052 and the first comparator 3051. The counter 3052 counts the number of the read data from the top of the processing target block, and the first comparator 3051 checks the DCT3
The value of data read one pixel at a time from 01 is a quantized value 31 which is a divisor for dividing the data in the quantization process.
A comparison is made as to whether it is 1 or more (step s32), and the result is output to the selector 3053.

The reason why the first comparator 3051 compares the read data with the quantized value 311 is that the quantized value 311 is used to quantize the read data when quantizing the read data. Since the value of the read data is greater than the quantized value 311, the quantizer 302 in the subsequent stage
When quantized at and input to the encoder 304,
This is because it can be determined that the read data is not zero.

If the data read out by the first comparator 3051 is smaller than the quantized value 311 (“0” is output from the first comparator 3051), the register 3055 is output from the selector 3053.
Is stored in the first comparator 3051. On the other hand, the data read out by the first comparator
If the value is 1 or more (when "1" is output from the first comparator 3051), the value of the counter 3052 at that time is converted in a zigzag order using the data processing order-zigzag order conversion table 3056 (step s33). ), The second comparator 3054 compares the converted zigzag order with the value held in the register 3055 and selects the larger one (step s34). At that time, the second comparator 3054 In the register 30
55 (step s35).

That is, in the third embodiment, DC
Since the DCT coefficient is output from T301 in the order of horizontal feed as indicated by the arrow in FIG. 13A, the value of the counter 3052 indicates the order of horizontal feed from the top of the read data block. . However, the encoder 30
In No. 4, the data of one block is scanned in a zigzag order as indicated by the arrow in FIG. 13B and variable length coding is performed. In order to indicate the position of the conversion coefficient, the value of the counter 3052 must be converted in the corresponding zigzag order. Therefore, the third embodiment
, The read data is stored in the first comparator 3
If the quantization value is equal to or more than 311 in 051, the value of the counter 3052 at that time is converted in a zigzag order using the conversion table 3056, and the second comparator 305
4, the value read first in the zigzag order may be read later in the zigzag order due to the difference in the scan order for the blocks between the zigzag order and the horizontal feed order. The larger value is selected by comparing the value converted by the conversion table 3056 and held in the register 3055.

Therefore, the data read out from the first comparator 3051 is the DC value equal to or greater than the quantized value 311.
The T coefficient is detected, and the position of the DCT coefficient in the block to be processed in the horizontal feed order is detected by the counter 3052.
In the conversion table 3056, the horizontal feed order is replaced in a zigzag order, and the second comparator 3054 always holds a large value in the register 3055. , The position of the non-zero quantized coefficient at the end of the block can be detected.

Whether or not the read data is the final data of the block to be processed is determined by determining whether the value of the counter 3052 is N since one block is composed of N pixel data. If not (step s36), if the data is not the final data (if the value of the register 3055 is ≠ N), the flow returns to step s32 again to repeat the above-described operation, and the read data is the final data of the block. If (the value of the register 3055 is N), the value held in the register 3055 at that time is output to the encoder 304 as the control signal 310 (step s37). At the same time, the counter 30
The value of the register 52 and the value of the register 3055 are set to 1 for initialization.

The DCT coefficients output from the DCT 301 are input to the quantizer 302 one pixel at a time, quantized, and stored in the memory 303. This memory 3
03 is a single-port memory having a two-bank configuration,
After storing the quantized coefficients quantized by the quantizer 302 for one block in one bank, the bank is switched to accumulate the quantized coefficients of the data of the next block that is sequentially input, and at the same time, the storage is performed. The quantized coefficients for one block are read out in a zigzag order indicated by an arrow in FIG. 13B and output to the encoder 304 (B in FIG. 7). The state of writing and reading of data in the memory 303 is shown in FIG.

In the encoder 304, the quantized coefficients for one block output from the memory 303 are variable-length coded. At this time, the position of the last non-zero quantized coefficient in the block is detected from the control signal 310 output from the EOB detector 305, and variable-length coding is performed on the quantized coefficient at that position. To add the EOB code to the last value subjected to the variable-length coding, and stop the encoder 304 until data of the next block is input from the EOB detector 305 (step s38). This eliminates the need for the encoder 304 to perform variable-length encoding on all data of one block, and can reduce the power consumption of the encoding circuit.

As described above, according to the third embodiment,
An EOB detector 305 is provided between the DCT 301 and the quantizer 302. In the EOB detector 305, the position of the last non-zero quantization coefficient in the block to be processed in the zigzag order is detected. The value is output to the encoder 304 as a control signal 310. When the encoder 304 detects the position of the last non-zero quantization coefficient by the control signal 310, the detected position The variable length coding is performed on the quantization coefficients up to and an EOB code is added thereto.
Since the operation is paused until the data of the next block from 3 is input, it is possible to reduce the power consumption when performing variable-length encoding in the encoder 304, and as a result, In the circuit, power consumption can be reduced without adversely affecting image quality.

In the third embodiment, the memory 303 is a single-port memory having a two-bank configuration. However, similar effects can be obtained even if the memory 303 is a dual-port memory having a one-bank configuration. It is.

Further, in the third embodiment, as a method of frequency-converting data input to the encoding circuit, DC
Although the T process has been described as an example, the present invention is not limited to this, and any method may be used as long as it performs frequency conversion on data input to the encoding circuit. Also, the encoder 30
The scan order for variable-length encoding in 4 is as follows.
Here, an example in which zigzag order is performed has been described, but any scan order may be used, and a scan order according to the characteristics of data input to the present encoding circuit may be selected. In this case, the conversion table 3056 in the EOB detector 305 needs to be a table that converts the value of the counter 3052 (data processing order) into a scan order according to data characteristics.

(Embodiment 4) An encoding circuit according to Embodiment 4 will be described below with reference to the drawings. In the fourth embodiment, as in the third embodiment, the EO
Another configuration in the case where the B detector is provided between the DCT and the quantizer will be described. First, the configuration of the encoding circuit according to the fourth embodiment will be described with reference to FIGS.

FIG. 10 is a diagram showing a configuration of an encoding circuit according to the fourth embodiment, and FIG.
It is a figure showing the detailed composition of a detector. As shown in FIG. 10, the encoding circuit according to Embodiment 4 performs DCT processing on input data and outputs the position of the last non-zero value in the processing target block as control signal 410. An EOB detector 405 that performs quantization and a quantizer 40 that quantizes data from the DCT 401.
2 and an encoder 404 for performing variable-length encoding.

As shown in FIG. 11, the EOB detector 405 according to the fourth embodiment includes a memory 4054 for temporarily storing data output from the DCT 401 in the transverse direction and outputting the data in a zigzag order, A first comparator 4051 for comparing a DCT coefficient read from the data block 4054 with a quantized value 411 which is a divisor when quantizing the data in the quantizer 402; A counter 4052 for counting the number of data from the head, a selector 4053 for selecting a value to be held in a register 4055 based on the result of the first comparator 4051,
N for storing one block of data input from 054
And a stage shift register 4056. Note that the memory 4054 is a single-port memory having a two-bank configuration.

Next, the operation of the encoding circuit according to the fourth embodiment will be described with reference to FIG. FIG.
FIG. 14 is a flowchart showing a series of operations of the encoding circuit according to the fourth embodiment. Here, it is assumed that the data input to the encoding circuit is a digital video signal in which one block includes N pixels.

First, the data input to the encoding circuit is converted into DCT coefficients in the DCT 401 (step s41). Then, the DCT coefficient output from the DCT 401 is input to the EOB detector 405.

In the EOB detector 405, first, the memory 40
At 54, the data of one block read from the DCT 401 is written in the horizontal feed order shown by the arrow in FIG. 13A (A in FIG. 10), and By outputting in the zigzag order shown (B in FIG. 10), the data is rearranged (step s42). FIG. 14 shows the state of writing and reading of data in the memory 4054. Further, the memory 4054
Accumulates one block of quantization coefficient in one bank,
By performing bank switching, the quantization coefficients of the data of the next block sequentially input are accumulated.

Next, the data read from the memory 4054 in zigzag order is output to the counter 4052, the N-stage shift register 4056, and the first comparator 4051. The counter 4052 counts the number of the read data from the top of the processing target block, and the N-stage shift register 4056 holds the read data. In the first comparator 4051, the memory 40
The value of the data read pixel by pixel from 54 is a quantized value 41 which is a divisor for dividing the data in the quantization process.
A comparison is made as to whether it is 1 or more (step s43), and the result is output to the selector 4053.

The reason why the first comparator 4051 compares the read data with the quantized value 411 is for the same reason as described in the third embodiment.

In the first comparator 4051, when the read data is smaller than the quantized value 411 (when “0” is output from the first comparator 4051), the selector 4053 405
5 is selected. On the other hand, when the read data is equal to or more than the quantized value 411 in the first comparator 4051 (“1” is output from the first comparator 4051). ) Is the counter 405 at that time
The value of 2 is selected and held in the register 4055 (step s44).

That is, in the fourth embodiment, in the memory 4054, the DCT 401
DCT output in horizontal feed order as indicated by the arrow in FIG.
Since the coefficients are rearranged in the zigzag order shown in FIG. 13B and output, the value of the counter 4052 indicates the zigzag order from the top of the block of the read data, and the first The comparator 4051 detects a DCT coefficient that is equal to or more than the quantized value 411, and the position at that time is detected by the counter 4052 and stored in the register 4055. For 404, the position of the last non-zero quantized coefficient of the block can be indicated.

Whether or not the read data is the final data of the block to be processed is determined by determining whether the value of the counter 4052 is N since one block is composed of N pixel data. If it is not the final data (if the value of the register 4055 is （N), the above operation is repeated, while if the read data is the final data of the block (the value of the register 4055) (= N), the value held in the register 4055 at that time is output as the control signal 410 to the quantizer 402 and the encoder 404 (step s46). At the same time, the DCT coefficient for one block held in the N-stage shift register 4056 is output to the quantizer 402, and the value of the counter 4052 and the value of the register 4055 are set to 1 for initialization.

The quantizer 402 quantizes the DCT coefficients input from the N-stage shift register 4056 in zigzag order pixel by pixel. At that time, the position of the last non-zero DCT coefficient in the block is detected from the control signal 410 output from the EOB detector 405, and quantization is performed up to the DCT coefficient at that position. The quantizer 402 is stopped until the data of the next block is input from the EOB detector 405 (step s47).

Further, the encoder 404 performs variable-length encoding on the quantized coefficients for one block output from the quantizer 402. At this time, the position of the last non-zero quantization coefficient in the block is detected from the control signal 410 output from the EOB detector 405, and variable-length coding is performed on the quantization coefficient at that position. Then, an EOB code is added to the last value subjected to the variable-length encoding, and the encoder 404 is stopped until the data of the next block is input from the quantizer 402 (step s48). ). By doing so, the quantizer 4
02 and the encoder 404 do not need to perform quantization or variable length encoding on all data of the processing target block, and can further reduce the power consumption of the encoding circuit.

As described above, according to the fourth embodiment,
An EOB detector 405 is provided between the DCT 401 and the quantizer 402. The EOB detector 405 detects the position of the last non-zero quantized coefficient in the block to be processed in a zigzag order, The value is output to the quantizer 402 and the encoder 404 as a control signal 410. When the quantizer 402 detects the position of the last non-zero quantized coefficient by the control signal 410, DCT to the detected position
After quantizing the coefficients, the operation is suspended, and the encoder 404 outputs the control signal 410
When the position of the last non-zero quantized coefficient is detected, the variable-length coding is performed on the quantized coefficient up to the detected position and an EOB code is added. The operation is suspended until the data of the quantizer 402 is input.
, The power consumption when quantizing, and the encoder 4
04, the power consumption when performing variable length coding can be reduced, and as a result, the coding circuit can achieve a greater reduction in power consumption without adversely affecting image quality.

Although the memory 4054 is a single-port memory having a two-bank configuration in the fourth embodiment, the same effect can be obtained even if the memory 4054 is a dual-port memory having a one-bank configuration. Can be

Further, in the fourth embodiment, DC input is used as a method of frequency-converting data input to the encoding circuit.
Although the T process has been described as an example, the present invention is not limited to this, and any method may be used as long as it performs frequency conversion on data input to the encoding circuit. Also, the encoder 40
The scan order for variable-length encoding in 4 is as follows.
Here, an example in which zigzag order is performed has been described, but any scan order may be used, and a scan order according to the characteristics of data input to the present encoding circuit may be selected.

[0082]

As described above, according to the encoding circuit of the first aspect of the present invention, the frequency conversion means for converting the data of the block to be processed into frequency components, and quantizing the frequency components. In a coding circuit comprising a quantization means and a coding means for performing variable length coding on the quantized frequency components in a predetermined scan order, the non-zero quantized signal at the end of the block to be processed is EOB detection means for detecting a position of the frequency component in the predetermined scan order and outputting the position as a control signal to the encoding means, wherein the encoding means is configured to perform the predetermined scan indicated by the control signal. Variable-length coding is performed on the quantized frequency components up to the position in order, an EOB code indicating the final position of the effective component is added, and the variable-length coding process is stopped. Therefore, before performing the variable-length encoding in the encoding means, the insertion position of the EOB code is detected, and from the quantized frequency component at the position to the final quantized frequency component of the processing target block. Variable-length encoding process can be paused, and as a result,
Adaptive power consumption can be reduced without any adverse effect on image quality.

According to a second aspect of the present invention, in the encoding circuit according to the first aspect, the EOB detecting means includes a part for the processing target block from the quantizing means. A memory that temporarily holds the quantized frequency component and outputs the quantized frequency component in the predetermined scan order, and that is provided between the encoding unit and the quantized frequency component input from the memory; A counter for detecting a position, a comparator for comparing whether or not the quantized frequency component is 0, a buffer for storing the value of the quantized frequency component, and a buffer for storing a value of the comparator. And a register for holding the position of the quantized frequency component which is not 0, so that the EOB detecting means uses the EOB in the processing target block.
The insertion position of the code can be detected and indicated to the encoding means.

According to a third aspect of the present invention, in the encoding circuit according to the first aspect, the EOB detecting means includes: the quantizing means; It is provided between the processing target block and a memory that temporarily stores the quantized frequency components,
A counter for detecting the position of the quantized frequency component input from the quantizing means, and a first comparator for comparing whether the quantized frequency component is 0 or not;
A buffer for storing the value of the quantized frequency component, a conversion table for converting the value of the counter into a value in the predetermined scan order, and a non-zero quantum based on a result of the first comparator. A register for holding a position of the digitized frequency component in a predetermined scan order, and a position held in the register for storing the position of the last non-zero quantized frequency component of the processing target block in the predetermined scan order. And a second comparator for comparing whether or not the position is the position of the EOB code, so that the EOB detecting means detects the insertion position of the EOB code in the processing target block, and Can be shown.

According to a fourth aspect of the present invention, in the encoding circuit according to the first aspect, the EOB detecting means is provided between the frequency converting means and the quantizing means. And a counter for detecting the position of the frequency component input from the frequency conversion means, and comparing the frequency component with a quantized value which is a divisor for dividing the frequency component in the quantization means. A first comparator, a conversion table for converting the value of the counter into the value in the predetermined scan order, and a predetermined value of the non-zero quantized frequency component based on a result of the first comparator. The register holding the position in the scan order and the position held in the register are the position of the last non-zero quantized frequency component of the processing target block in the predetermined scan order. Since so and a second comparator for comparing whether, in the EOB detection unit,
The insertion position of the EOB code in the block to be processed can be detected and indicated to the encoding means.

According to the encoding circuit of the fifth aspect of the present invention, a frequency converting means for converting the data of the processing target block into a frequency component, a quantizing means for quantizing the frequency component, Encoding means for performing variable-length encoding of the quantized frequency component in a predetermined scan order, wherein a non-zero quantized frequency component at the end of the processing target block is EOB detection means for detecting a position in the predetermined scan order and outputting the position as a control signal to the quantization means and the encoding means, wherein the quantization means The frequency component up to the position in the scan order is quantized, and the quantization process is paused. The encoding means performs the quantity in the position in the predetermined scan order indicated by the control signal. Variable-length coding up to the converted frequency component, an EOB code indicating the final position of the effective component is added, and the variable-length coding process is paused. The above EO
The position where the B code is inserted is detected, and quantization processing from the frequency component at the position to the final frequency component of the processing target block, and the final processing of the processing target block from the quantized frequency component at the position The variable-length code processing up to the quantized frequency component can be suspended, and as a result, more power consumption can be reduced without any adverse effect on the image quality.

According to the encoding circuit of the present invention, in the encoding circuit of the present invention, the EOB detecting means is provided between the frequency converting means and the quantizing means. A memory for temporarily storing the frequency components for the processing target block from the frequency conversion means and outputting the frequency components in the predetermined scan order, and a frequency input from the memory in the predetermined scan order. A counter for detecting the position of the component, a first comparator for comparing the frequency component with a quantized value which is a divisor for dividing the frequency component in the quantization means, and stores the value of the frequency component A buffer for storing the position of the non-zero quantized frequency component in a predetermined scan order based on the result of the first comparator; In EOB detection unit detects the insertion position of the EOB code in the target block, it can be shown in the quantization means and coding means.

Further, according to the encoding method of the present invention, a frequency conversion step of frequency-converting the data of the block to be processed into a frequency component, a quantization step of quantizing the frequency component, An EOB detection step of determining whether the quantized frequency component is zero and detecting the position of the last non-zero quantized frequency component in the predetermined scanning order at the end of the processing target block; And the variable-length coding of the quantized frequency component up to a position in the predetermined scanning order of the frequency component detected in the EOB detection step, to indicate that this is the final position of the effective component. An EOB code is added, and an encoding step for suspending the variable length encoding process is provided.
By detecting the insertion position of the B code, it becomes possible to suspend the variable length code processing from the quantized frequency component at the position to the final quantized frequency component of the processing target block, and as a result, In addition, it is possible to adaptively reduce power consumption without adversely affecting image quality.

Further, according to the encoding method of the present invention, a frequency conversion step of frequency-converting the data of the block to be processed into a frequency component; An EOB detection step of comparing a quantized value, which is a divisor to be divided, to detect the position of the last non-zero quantized frequency component in the predetermined scan order in the last block of the processing target block; And a variable-length encoding of the quantized frequency component up to a position in a predetermined scan order of the frequency component detected in the EOB detection step, and An EOB code indicating the final position is added, and an encoding step for suspending the variable length encoding process is provided.
Before performing the variable-length coding, the insertion position of the EOB code is detected, and the variable-length coding process from the quantized frequency component at the position to the final quantized frequency component of the processing target block is paused. And as a result,
Adaptive power consumption can be reduced without any adverse effect on image quality.

According to the encoding method of the ninth aspect of the present invention, the frequency conversion step of frequency-converting the data of the block to be processed into a frequency component; the frequency component; An EOB detection step of comparing a quantized value which is a divisor to divide the current block and detecting a position of a quantized frequency component other than the last 0 in the processing target block in a predetermined scanning order; A quantization step of quantizing the frequency components up to a position in the predetermined scan order of the frequency components detected in the EOB detection step, and suspending the quantization process; and a predetermined scan order of the frequency components. The variable-length coding is performed on the quantized frequency component up to the position of EO to indicate that it is the final position of the effective component.
A coding step of adding a B code and suspending the variable-length coding process. Therefore, before quantization, a position where the EOB code is inserted is detected, and processing is performed from a frequency component at the position. It is possible to suspend the quantization processing up to the final frequency component of the target block and the variable length code processing from the quantized frequency component at the position to the final quantized frequency component of the processing target block. Become
As a result, more power consumption can be reduced without adversely affecting the image quality.

According to the encoding program of the present invention, the data of the block to be processed is frequency converted and quantized by the computer, and the quantized frequency components are converted in a predetermined scanning order. A coding program for executing a process of performing variable-length coding, comprising: a frequency conversion step of performing frequency conversion of data of a processing target block into a frequency component; a quantization step of quantizing the frequency component; It is determined whether the frequency component is zero or not, and at the end of the processing target block,
An EOB detecting step of detecting a position of the non-zero quantized frequency component in the predetermined scan order;
The quantized frequency component up to the position in the predetermined scan order of the frequency component detected in the B detection step is subjected to variable-length encoding to generate an EOB code indicating the final position of the effective component. And a coding step of suspending the variable-length coding process, so that the data of the processing target block is frequency-converted and quantized, and the quantized frequency components are subjected to variable-length In the encoding process, it is possible to provide a program capable of adaptively reducing power consumption without adversely affecting image quality.

According to the encoding program of the present invention, the data of the block to be processed is frequency-converted and quantized by the computer, and the quantized frequency components are converted in a predetermined scanning order. A coding program for performing a process of performing variable length coding, the frequency converting step of performing frequency conversion of data of a processing target block into a frequency component, and dividing the frequency component in the quantization process with the frequency component. An EOB detection step of comparing a quantized value which is a divisor to detect a position of the last non-zero quantized frequency component in the predetermined scan order at the end of the block to be processed; A quantizing step for quantizing, and the frequency component detected in the EOB detecting step is located at a position in a predetermined scanning order. The variable-length coding is performed on the quantized frequency component, an EOB code indicating the final position of the effective component is added, and the coding step for stopping the variable-length coding process is included. In the process of frequency-converting and quantizing the data of the processing target block and performing variable-length coding on the quantized frequency components in a predetermined scanning order, adaptive power consumption without adversely affecting the image quality. A program that can be reduced can be provided.

According to the encoding program of the twelfth aspect of the present invention, the data of the block to be processed is frequency-converted and quantized by the computer, and the quantized frequency components are converted in a predetermined scanning order. A frequency conversion step of performing frequency conversion of data of a processing target block into a frequency component, and a divisor for dividing the frequency component in the quantization process. And an EOB detection step of detecting the position of the last non-zero quantized frequency component in the predetermined scan order at the end of the processing target block, The detected frequency component is quantized with respect to the frequency component up to a position in a predetermined scan order, and a quantization process is performed. And a variable length encoding of the quantized frequency component up to the position of the frequency component in a predetermined scan order, and an EOB code indicating the final position of the effective component. And a coding step of suspending the variable-length coding process, so that the data of the processing target block is frequency-converted and quantized, and the quantized frequency components are subjected to variable-length coding in a predetermined scan order. In the encoding process, it is possible to provide a program capable of further reducing power consumption without adversely affecting image quality.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration of an encoding circuit according to Embodiment 1 of the present invention.

FIG. 2 is a diagram illustrating an encoding circuit according to the first embodiment of the present invention;
It is a figure showing the detailed composition of an EOB detector.

FIG. 3 is a flowchart showing a series of operations of the encoding circuit according to the first embodiment of the present invention.

FIG. 4 is a diagram illustrating a configuration of an encoding circuit according to a second embodiment of the present invention.

FIG. 5 is a diagram illustrating an encoding circuit according to a second embodiment of the present invention.
It is a figure showing the detailed composition of an EOB detector.

FIG. 6 is a flowchart showing a series of operations of an encoding circuit according to Embodiment 2 of the present invention.

FIG. 7 is a diagram illustrating a configuration of an encoding circuit according to a third embodiment of the present invention.

FIG. 8 is a diagram illustrating an encoding circuit according to a third embodiment of the present invention;
It is a figure showing the detailed composition of an EOB detector.

FIG. 9 is a flowchart showing a series of operations of an encoding circuit according to Embodiment 3 of the present invention.

FIG. 10 is a diagram illustrating a configuration of an encoding circuit according to a fourth embodiment of the present invention.

FIG. 11 is a diagram illustrating a detailed configuration of an EOB detector in an encoding circuit according to a fourth embodiment of the present invention.

FIG. 12 is a flowchart illustrating a series of operations of an encoding circuit according to Embodiment 4 of the present invention.

FIG. 13 is a diagram showing an output order when data in units of blocks are output horizontally (FIG. 13 (a)), and a diagram showing a scan order when zigzag scanning is performed on data in units of blocks (FIG. 13 (b)). )), And a table showing the data processing order, the corresponding zigzag order, DCT coefficients, and the values held in the registers at that time (FIG. 9C).

FIG. 14 is a diagram showing a state in which data is written to a memory, and the data is rearranged and read in the embodiment of the present invention.

FIG. 15 is a diagram illustrating a configuration of a conventional encoding circuit.

[Explanation of symbols]

101, 201, 301, 401, 501 DCT 102, 202, 302, 402, 502 Quantizer 103, 203, 303, 503 Memory 104, 204, 304, 404, 504 Encoder 105, 205, 305, 405 EOB Detector 110, 210, 310, 410 Control signal 311, 411 Quantized value 1051 Comparator 1052, 2052, 3052, 4052 Counter 1053, 2053, 3053, 4053 Selector 1054, 4056 N-stage shift register 1055, 2055, 3055, 4055 Registers 2051, 3051, 4051 First comparator 2054, 3054 Second comparator 2056, 3056 Data processing order-zigzag order conversion table 4054 Memory

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5C053 FA21 FA23 GA11 GB21 GB22 GB26 GB32 KA01 5C059 KK49 MA23 MC01 MC11 MC24 ME01 SS11 UA02 UA39 5J064 AA00 BA09 BA16 BC00 BC01 BC04 BC05 BC14 BC16 BC25 BC29 BD02 BD03 BD04

Claims (12)

[Claims] 1. A frequency conversion means for frequency-converting data of a block to be processed into a frequency component, a quantization means for quantizing the frequency component, and a variable-length code for converting the quantized frequency component in a predetermined scanning order. A position of the last of the block to be processed in the predetermined scan order of the non-zero quantized frequency component, and the position is controlled by a control signal. EOB detection means for outputting to the encoding means as above, wherein the encoding means performs variable length encoding on the quantized frequency component up to a position in the predetermined scan order indicated by the control signal. An EOB code indicating the last position of the effective component, and suspending the variable-length encoding process. 2. The encoding circuit according to claim 1, wherein said EOB detecting means temporarily stores said quantized frequency components of said processing target block from said quantizing means and performs said predetermined scan. A counter for detecting the position of the quantized frequency component input from the memory; A buffer for storing the value of the quantized frequency component, and a position of the non-zero quantized frequency component based on the result of the comparator. And a register. 3. The encoding circuit according to claim 1, wherein said EOB detecting means temporarily holds said quantizing means and said quantized frequency components of said processing target block from said quantizing means. A counter for detecting the position of the quantized frequency component input from the quantizing means, and comparing whether the quantized frequency component is 0 or not. A first comparator, a buffer for storing the value of the quantized frequency component, a conversion table for converting the value of the counter into a value in the predetermined scan order, and a result of the first comparator A register that holds the position of the non-zero quantized frequency component in a predetermined scan order, based on the position of the non-zero quantized frequency component. It has been provided a second comparator for comparing whether the position in the predetermined scan order frequency components, and coding circuit, characterized in that. 4. The encoding circuit according to claim 1, wherein said EOB detection means is provided between said frequency conversion means and said quantization means, and wherein a frequency component inputted from said frequency conversion means is provided. A first detector for comparing the frequency component with a quantized value that is a divisor for dividing the frequency component in the quantization means; and a counter for scanning the value of the counter for the predetermined scan. A conversion table for converting the value into a sequence value, a register for holding the position of the non-zero quantized frequency component in a predetermined scan order based on the result of the first comparator, A second comparator for comparing whether or not the calculated position is a position of the last non-zero quantized frequency component of the processing target block in the predetermined scanning order. Encoding circuit, wherein the door. 5. A frequency conversion means for frequency-converting data of a processing target block into a frequency component, a quantization means for quantizing the frequency component, and
Encoding means for performing variable-length encoding in a predetermined scan order, wherein a position of the last non-zero quantized frequency component in the predetermined scan order in the last scan block is detected. And an EOB detecting unit that outputs the position as a control signal to the quantization unit and the encoding unit. Quantizing the component, suspending the quantization process, the encoding means performs variable length encoding up to the quantized frequency component at a position in the predetermined scan order indicated by the control signal, An encoding circuit, comprising: adding an EOB code indicating the last position of an effective component; and suspending variable-length encoding processing. 6. The encoding circuit according to claim 5, wherein said EOB detection means is provided between said frequency conversion means and said quantization means, and said block to be processed from said frequency conversion means is provided. A memory for temporarily storing the frequency components for the predetermined minutes and outputting the same in the predetermined scan order, a counter for detecting the position of the frequency components input from the memory in the predetermined scan order, the frequency component, and the quantum A first comparator for comparing a quantized value, which is a divisor for dividing the frequency component, in a converting means; a buffer for storing the value of the frequency component; A register for holding a position of a non-zero quantized frequency component in a predetermined scanning order. 7. A frequency conversion step of frequency-converting the data of the processing target block into a frequency component, a quantization step of quantizing the frequency component, and determining whether the quantized frequency component is zero. An EOB detection step of detecting the position of the last non-zero quantized frequency component of the processing target block in a predetermined scan order; and a predetermined EOB detection step of the frequency component. Variable length coding of the quantized frequency component up to the position in the scan order, adding an EOB code indicating the final position of the effective component, and suspending the variable length coding process And a coding method. 8. A frequency conversion step of frequency-converting data of a processing target block into a frequency component, and comparing the frequency component with a quantized value which is a divisor for dividing the frequency component in a quantization process. An EOB detection step of detecting the position of the last non-zero quantized frequency component of the target block in a predetermined scan order; a quantization step of quantizing the frequency component; and an EOB detection step. The variable frequency coding is performed on the quantized frequency component up to the position in the predetermined scanning order of the frequency component, and an EOB code indicating the final position of the effective component is added. A coding step of suspending the coding process. 9. A frequency conversion step of frequency-converting data of a processing target block into a frequency component; and comparing the frequency component with a quantization value that is a divisor for dividing the frequency component in a quantization process. An EOB detection step of detecting the position of the last non-zero quantized frequency component in the predetermined scan order of the block to be processed; and A quantization step of quantizing the frequency component up to the position and suspending the quantization process; and Coding step of performing long coding, adding an EOB code indicating the last position of the effective component, and pausing the variable length coding process. An encoding method characterized by: 10. An encoding program for causing a computer to perform a process of frequency-converting and quantizing data of a block to be processed and performing variable-length encoding of the quantized frequency components in a predetermined scan order. A frequency conversion step of frequency-converting the data of the processing target block into a frequency component, a quantization step of quantizing the frequency component, and determining whether the quantized frequency component is zero, An EOB detecting step of detecting a position of the last non-zero quantized frequency component of the processing target block in the predetermined scan order; and a predetermined scan order of the frequency component detected in the EOB detection step. Variable length coding is performed on the quantized frequency component up to the position at to indicate that the effective component is the final position. Adding OB code includes a coding step of pausing the variable length coding process, the encoding program characterized by. 11. An encoding program for causing a computer to perform a process of frequency-converting and quantizing data of a block to be processed and performing variable-length encoding of the quantized frequency components in a predetermined scan order. A frequency conversion step of frequency-converting the data of the processing target block into a frequency component; and comparing the frequency component with a quantized value that is a divisor for dividing the frequency component in the quantization processing. An EOB detection step of detecting the position of the last non-zero quantized frequency component in the predetermined scan order; a quantization step of quantizing the frequency component; and an EOB detection step. Variable-length encoding the quantized frequency component up to a position in the predetermined scan order of the frequency component, Adding EOB code indicating the end position of the active ingredient, comprising an encoding step of pausing the variable length coding process, the encoding program characterized by. 12. An encoding program for causing a computer to perform a process of frequency-converting and quantizing data of a processing target block and performing variable-length encoding of the quantized frequency components in a predetermined scan order. A frequency conversion step of frequency-converting the data of the processing target block into a frequency component; and comparing the frequency component with a quantized value that is a divisor for dividing the frequency component in the quantization processing. An EOB detection step for detecting the position of the last non-zero quantized frequency component in the predetermined scan order; and a position of the frequency component detected in the EOB detection step in the predetermined scan order. A quantization step of quantizing the certain frequency component and suspending the quantization process; Variable-length coding of the quantized frequency component up to the position in the order of the effective component, adding an EOB code indicating the final position of the effective component, and suspending the variable-length coding process. And an encoding program.