JP2002329810A - Semiconductor package assembly and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor package assembly for manufacturing a thin type package by three-dimensional mounting without using a thin type wafer and a thin type chip and its manufacturing method, and to provide a manufacturing method for a thin type semiconductor package using the semiconductor package aggregate. SOLUTION: In the semiconductor package assembly, a large number of the semiconductor packages containing the semiconductor chips are formed on an insulating tape base material having the same plane shape as the semiconductor wafer and a wiring pattern on a top face or an underside, the semiconductor chips are bonded on the top face of the insulating tape base, directing active surfaces downwards, peripheries are sealed with a sealing resin layer, the semiconductor chips are connected electrically to the wiring pattern of the insulating tape base material, and the rears of the semiconductor chips are ground and polished together with the sealing resin layer and formed in the same plane as the top face of the sealing resin layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package assembly suitable for manufacturing a thin semiconductor package by three-dimensional mounting and a method for manufacturing the same, and to a method for manufacturing a semiconductor package using the semiconductor package assembly.

[0002]

2. Description of the Related Art Miniaturization and weight reduction of electronic information devices,
Although demands for higher speed and higher functionality are increasing more and more, it has become a situation where conventional LSI technology alone cannot sufficiently meet this demand. That is, since the one-chip integration using the system LSI involves the development of wiring in a two-dimensional direction, there is a limit to the increase in speed due to the reduction in wiring, which leads to an increase in development cost and development period. As a solution, three-dimensional mounting has attracted attention.

[0003] The three-dimensional mounting is a mounting type in which a plurality of chips are stacked in the height direction, and the wiring can be shortened by three-dimensional connection (particularly, connection in the stacking direction), and at the same time, the mounting density is improved. be able to. Further, since it is not necessary to integrate the LSI into one chip, it is expected that the development period of the LSI is reduced and the cost is reduced. There are three levels of package level, chip level, and wafer level in three-dimensional mounting, but it is considered that three-dimensional mounting at the package level can realize many layers at an early stage. And
In order to realize high-density three-dimensional packaging at the package level, it is necessary to reduce the thickness of individual stacked chips.

Conventionally, to manufacture a thin chip, first, a semiconductor wafer is processed to be thin, and each semiconductor element (corresponding to each semiconductor chip) is formed on the thin wafer. Semiconductor chip. Then, the thin chips are stacked to produce a thin package. However, thin wafers and thin chips are prone to cracks and warpage during the manufacturing process, and have low mechanical strength, which requires complicated operations such as using a special carrier for handling. there were.

[0005]

SUMMARY OF THE INVENTION The present invention solves the above-mentioned problems of the prior art, and provides a semiconductor package assembly for manufacturing a thin package by three-dimensional mounting without using a thin wafer and a thin chip, and a method of manufacturing the same. It is an object of the present invention to provide a method and a method for manufacturing a thin semiconductor package using the semiconductor package assembly.

[0006]

According to a first aspect of the present invention, there is provided an insulating tape base having the same planar shape as a semiconductor wafer and having a wiring pattern on an upper surface or a lower surface. A large number of semiconductor packages including a semiconductor chip are formed on a material, and the semiconductor chip is bonded to the upper surface of the insulating tape base with the active surface facing downward, and the periphery is sealed with a sealing resin layer. , Electrically connected to the wiring pattern of the insulating tape substrate, the back surface of the semiconductor chip is ground and polished together with the sealing resin layer to form the same plane as the upper surface of the sealing resin layer A semiconductor package assembly is provided.

In the semiconductor package assembly according to the first aspect of the invention, the electrical connection between the semiconductor chip and the wiring pattern of the insulating tape substrate may be made by any of a beam lead, a bonding wire, and a bump.

According to the second invention of the present application, as a method of manufacturing the semiconductor package assembly of the first invention, the following steps are performed: the same planar shape as a semiconductor wafer and a wiring pattern provided on an upper surface or a lower surface. A step of bonding a large number of semiconductor chips with an active surface facing down to an upper surface of an insulating tape substrate, a step of electrically connecting the semiconductor chips to the wiring pattern of the insulating tape substrate, Forming a sealing resin layer covering the periphery and the back surface of the chip, and grinding and polishing the semiconductor chip and the sealing resin layer from the upper surface of the sealing resin layer to below the back surface of the semiconductor chip. A step of thinning the semiconductor chip and making a new back surface of the semiconductor chip and a new upper surface of the sealing resin layer flush with each other. Method for producing a body is provided.

In the method of the second invention, a beam lead,
The semiconductor chip can be electrically connected to the wiring pattern of the insulating tape base material by a bonding wire or a bump.

According to a third aspect of the present invention, there is provided a semiconductor device comprising a step of cutting the plurality of semiconductor packages individually by cutting the semiconductor package assembly of the first aspect between the semiconductor packages. A method for manufacturing a package is provided.

In the present invention, the back surface of the semiconductor chip is thinned by grinding and polishing in a state where a number of semiconductor packages including the semiconductor chip are formed on an insulating tape base material having the same planar shape as the semiconductor wafer. . Therefore,
Since there is no need to use thin wafers and thin chips,
There is no problem of cracking or warping which has conventionally occurred during the manufacturing process. Further, since the grinding and polishing of the semiconductor chip on the insulating tape substrate can be performed using existing equipment used for grinding and polishing of the semiconductor wafer, a complicated operation using a special carrier or the like is not required. as a result,
As compared with the conventional technology using thin wafers / thin chips, it is possible to easily achieve an improvement in yield, a reduction in cost, and a reduction in manufacturing time.

[0012]

Embodiments of the present invention will be described below with reference to the accompanying drawings. [Embodiment 1] FIGS. 1 and 2 show Embodiment 1 of the present invention.
Are shown in a perspective view and a sectional view, respectively. FIG. 2 shows a cross section taken along line XX of FIG. In FIG. 2 and each of the cross-sectional views referred to below, for the sake of convenience in clearly illustrating a very thin structure, the dimension in the thickness direction (vertical direction of each cross-sectional view) is changed in the length direction (the horizontal direction of each cross-sectional view). It is drawn considerably enlarged to the dimensions.

As shown in the drawing, a semiconductor package assembly 1 of the present invention has a large number of semiconductor packages 12 including semiconductor chips 11 formed on an insulating tape base material 10 having the same planar shape as a semiconductor wafer. The semiconductor chip 11 is adhered to the upper surface 10S of the insulating tape base material 10, the periphery thereof is sealed with a sealing resin layer 13A, and electrically connected to the wiring pattern 14 on the lower surface 10R of the insulating tape base material 10. The back surface 11S of the semiconductor chip 11 is ground and polished together with the sealing resin layer 13A so as to be flush with the upper surface 13S of the sealing resin layer 13A.

The wiring pattern 14 is made of the insulating tape base material 1.
0 is formed on the lower surface 10R with a copper foil or the like, and is electrically connected to the semiconductor chip 11 by a beam lead 14M formed integrally therewith. Beam lead 14M
Are sealed in the through holes 10H of the insulating tape base material 10 by the sealing resin layer 13B.

As shown in FIG. 2, the upper connection terminal 15 extends upward from the wiring pattern 14 to
0 and the upper connection terminal 15
Is exposed on the same surface as the upper surface 13S of the sealing resin layer 13A. The upper connection terminal 15 includes, for example, a conductor pillar 15A penetrating the insulating tape base material 10, and a conductor ball 15B thereon. In the illustrated example, the upper connection terminal 15 has a type in which both upper and lower ends are exposed, but a type in which the lower surface of the insulating tape base material 10 is covered with a solder resist layer and only the upper end of the upper connection terminal 15 is exposed. it can. In the case of the type in which only the upper end is exposed, in order to enable three-dimensional mounting, only the portion corresponding to the position of the upper connection terminal 15 is exposed without covering the lower surface of the wiring pattern 14 with solder resist, and the lower connection terminal is exposed there. (For example, 19 in FIG. 5)
Is provided. The upper connection terminal 15 is omitted in the perspective view of FIG.

Referring to FIG. 3, a method of manufacturing the above-mentioned semiconductor package assembly will be described. As shown in FIG.
An insulating tape base material 10 having the same planar shape as a semiconductor wafer is prepared. As the insulating tape base material 10, various organic materials or polymer materials can be used. In general, polyimide films, epoxy films reinforced with fibers such as glass or aramid, BT (bismaleimide triazine) films, PPE ( A resin film or a resin sheet such as a polyphenylene ether) film is suitable. The thickness of the insulating tape base material 10 is desirably thinner as long as the strength and rigidity required for the base material are ensured, in order to reduce the thickness of the semiconductor device.
A range of 5 μm to 100 μm, particularly around 75 μm, is used.

On the lower surface 10R of the insulating tape substrate 10, a wiring pattern 14 is formed by a copper foil or the like, and a conductor pillar 15A extends upward from the upper surface of the wiring pattern 14 and penetrates the insulating tape substrate 10. ing. The upper end of the conductor pillar 15A is exposed on the same plane as the upper surface 10S of the insulating tape base material 10.

The conductor pillar 15A is a pillar made of a metal such as copper or nickel, and is preferably a pillar made of a low melting point metal such as solder. As this solder, a silver-tin alloy (Ag
-Sn), a lead-tin alloy (Pb-Sn), a silver-tin-copper alloy (Ag-Sn-Cu), and a solder containing bismuth (Bi) or antimony (Sb) can be used.

As shown in the figure, the formation of the straight rod-shaped conductor pillar 15A penetrating the insulating tape base material 10 involves first putting an appropriate amount of flux into a through hole 10T whose lower end is closed by a wiring pattern 14, and This is performed by placing a low-melting metal ball such as a solder ball on the top and performing reflow. Or
The conductor pillar 15A may be formed by filling a metal such as copper in the through hole 10T by electrolytic plating.

The wiring pattern 1 extends inward from the lower opening end of the through hole 10H formed in the insulating tape base material 10.
A beam lead 14M as an inner lead formed integrally with the projection 4 projects.

Next, as shown in FIG. 3B, a large number of semiconductor chips 11 are adhered to the upper surface of the insulating tape base material 10, and the semiconductor chips 11 are insulated by beam leads 14M through the through holes 10H. Lower surface 10 of tape substrate 10
It is electrically connected to the R wiring pattern 14. Note that FIG.
In (2), the dimensions of the beam lead 14M are drawn longer than in FIG. 3 (1). This is because the drawing is performed by enlarging the vertical direction as described above. FIG.
There is no change in the dimension of the beam lead 14M between (2).

Next, as shown in FIG. 3 (3), a conductive ball 1 made of a low melting point metal such as solder similar to the conductive pillar 15A is provided on the upper end surface of the conductive pillar 15A penetrating the insulating tape base material 10.
5B is arranged, and the conductor pillar 1 is formed by performing a reflow process.
5A and the conductive ball 15B are combined to form an upper connection terminal 1
5 is assumed. Thereafter, a sealing resin layer 13A that covers the periphery and the back surface of the semiconductor chip 11 and the upper connection terminals 15 is formed. On the other hand, the sealing resin layer 13B filling the inside of the through hole 10H
Is formed, and the beam lead 14M is sealed with resin in the through hole 10H.

Next, as shown in FIG. 3D, the semiconductor chip 11 and the sealing resin layer 13A are
From the original upper surface 13S ₀ to the original back surface 1 of the semiconductor chip 11
It is ground and polished from the 1S ₀ to below, thinning the semiconductor chip 11. As a result of this grinding and polishing, the new back surface 11S of the semiconductor chip 11 becomes flush with the new upper surface 13S of the sealing resin layer 13A and is exposed upward.

Thus, for example, in the state shown in FIG.
The thickness of the semiconductor element 11 was about 50 μm
The thickness can be reduced to about 00 μm. As a result, 12
The semiconductor package assembly 1 thinned to about 0 to 300 μm is completed.

By cutting the semiconductor package assembly 1 thus manufactured between the respective semiconductor packages, a thin semiconductor package 2 shown in FIG. 4A is obtained. Thus, the three-dimensionally mounted thin semiconductor package 3 shown in FIG. FIG.
(2) shows an example in which the semiconductor packages 2 are stacked in two stages, but of course three or more layers can be stacked. In this stacking, as shown in FIG. 4B, external connection terminals 16 formed of solder balls formed on the lower surface of the wiring pattern 14 of the upper semiconductor package 2A and upper connection terminals 15 of the lower semiconductor package 2B. And between the upper and lower semiconductor packages 2A and 2B.

[Embodiment 2] FIG. 5 shows an example of a semiconductor package assembly 4 according to another embodiment. In the present embodiment, except that the electrical connection between the semiconductor chip 11 and the wiring pattern 14 is made by the bonding wire 17,
This is basically the same as the first embodiment. In particular, the plane configuration is
The configuration shown in FIG. 1 is the same as in the first embodiment.
FIG. 5 shows a cross section taken along line XX of FIG. 5, parts corresponding to those in the first embodiment are denoted by the same reference numerals as in FIG.

The wiring pattern 14 is made of the insulating tape base material 1.
0 is formed of copper foil or the like on the lower surface 10R, and is electrically connected to the semiconductor chip 11 by bonding wires 17. The bonding wires 17 are sealed in the through holes 10H of the insulating tape base 10 by the sealing resin layer 13B. In the example shown in FIG. 5, the lower surface of the semiconductor package assembly 4 is covered with a solder resist layer 18. However, the sealing resin layer 13B filling the through hole 10H and the lower connection terminal 19 provided on the lower surface of the wiring pattern 14 at a position corresponding to the position of the upper connection terminal 15
It is not covered with the solder resist layer 18. of course,
The presence of the solder resist layer 18 is not an essential configuration in the second embodiment, and may be a mode in which the solder resist layer 18 is not provided as in the first embodiment described with reference to FIG. That is, the presence or absence of the solder resist layer 18 can be selected regardless of the basic configuration of the first or second embodiment.

Referring to FIG. 6, a method of manufacturing the semiconductor package assembly according to the second embodiment will be described. As shown in FIG. 6A, similarly to the first embodiment, an insulating tape base material 10 having the same planar shape as a semiconductor wafer is prepared. However, in the example shown in FIG. 6, the lower surface of the insulating tape base material 10 has the wiring pattern 14 where the bonding wire 17 is joined, the through hole 10H, and the lower connection terminal 19 shown in FIG.
The entire surface excluding the wiring pattern 14 where the is formed is covered with the solder resist layer 18.

Next, as shown in FIG. 6 (2), a large number of semiconductor chips 11 are bonded to the upper surface of the insulating tape base material 10, and the bonding wires 17 are passed through the through holes 10H.
Thereby, the semiconductor chip 11 is electrically connected to the wiring pattern 14 on the lower surface 10R of the insulating tape base material 10.

Next, as shown in FIG. 6C, the upper connection terminal 15 and the sealing resin layer 1 are formed in the same manner as in the first embodiment.
Form 3A. On the other hand, a sealing resin layer 13B filling the inside of the through hole 10H is formed, and the bonding wire 17 is resin-sealed in the through hole 10H. The lower connection terminals 19 are formed by applying a solder paste.

Next, as shown in FIG. 6D, similarly to the first embodiment, the semiconductor chip 11 and the sealing resin layer 13A are formed.
Is ground and polished to thin the semiconductor chip 11. As a result, the new rear surface 11S of the semiconductor chip 11 becomes flush with the new upper surface 13S of the sealing resin layer 13A and is exposed upward.

Thus, for example, 5 in the state of FIG.
The semiconductor element 11 having a size of about
m. As a result, 120-3
Semiconductor package assembly 4 thinned to about 00 μm
Is completed.

By cutting the semiconductor package assembly 4 thus manufactured between the semiconductor packages, a thin semiconductor package can be obtained as in the first embodiment. A three-dimensionally mounted thin semiconductor package is obtained.

[Embodiment 3] FIG. 7 shows an example of a semiconductor package assembly 5 according to another embodiment. The present embodiment is basically the same as the first embodiment, except that the electrical connection between the semiconductor chip 11 and the wiring pattern 14 is made by bumps 20 using flip chip bonding. In particular, the plane configuration is the configuration shown in FIG. FIG. 7 shows a cross section taken along line XX of FIG. 7, parts corresponding to the first embodiment are denoted by the same reference numerals as in FIG.

As shown in the drawing, the semiconductor package assembly 5 of the present invention has a large number of semiconductor packages 12 including semiconductor chips 11 formed on an insulating tape base material 10 having the same planar shape as a semiconductor wafer. The semiconductor chip 11 is adhered to the upper surface 10S of the insulating tape base 10 via a wiring pattern 14, and the periphery thereof is sealed with a sealing resin layer 13A.
And is electrically connected to the wiring pattern 14 on the upper surface 10S of the insulating tape base material 10, and the back surface 11S of the semiconductor chip 11 is ground and polished together with the sealing resin layer 13A to form the sealing tape. It forms the same plane as the upper surface 13S of the resin stopper layer 13A.

The wiring pattern 14 is made of the insulating tape substrate 1
0 is formed on the upper surface 10R by a copper foil or the like, and is electrically connected to the semiconductor chip 11 by the conductor bumps 20.

As shown in FIG. 7, the upper connection terminal 21 extends upward from the wiring pattern 14 and penetrates the sealing resin layer 13A, and the upper end of the upper connection terminal 21 is the same as the upper surface 13S of the sealing resin layer 13A. It is exposed in a plane. The upper connection terminal 21 is formed of, for example, a conductive ball. Also,
The lower connection terminals 22 are formed by applying a solder paste.

Referring to FIG. 8, a method of manufacturing the semiconductor package assembly according to the third embodiment will be described. As shown in FIG. 8A, similarly to the first embodiment, an insulating tape base material 10 having the same planar shape as a semiconductor wafer is prepared. However, in the present embodiment, as shown, the wiring pattern 14 is provided on the upper surface of the insulating tape substrate 10.
Further, a through hole 10Q for forming a connection terminal downward from the wiring pattern 14 is formed.

Next, as shown in FIG. 8B, a large number of semiconductor chips 11 are bonded on the wiring patterns 14 on the upper surface of the insulating tape base material 10 by flip chip bonding, and the bumps 20 of the semiconductor chips 11 are formed. Thereby, the semiconductor chip 11 is electrically connected to the wiring pattern 14.

Next, as shown in FIG. 8C, the conductive ball 15 of the first embodiment is placed on the upper surface of the wiring pattern 14 at a position corresponding to the position of the through hole 10Q of the insulating tape base material 10.
The upper connection terminal 21 is formed in the same manner as the formation of B, and then the sealing resin layer 13A is formed in the same manner as in the first embodiment. Further, the conductor pillar 15 of the first embodiment is provided in the through hole 10Q.
The lower connection terminal 22 is formed in the same manner as the formation of A.

Next, as shown in FIG. 8D, the semiconductor chip 11 and the sealing resin layer 13A are replaced with the sealing resin layer 13A.
From the original upper surface 13S ₀ to the original back surface 1 of the semiconductor chip 11
It is ground and polished from the 1S ₀ to below, thinning the semiconductor chip 11. As a result of this grinding and polishing, the new back surface 11S of the semiconductor chip 11 becomes flush with the new upper surface 13S of the sealing resin layer 13A and is exposed upward.

As a result, for example, in the state of FIG.
The semiconductor element 11 having a size of about
m. As a result, 120-3
Semiconductor package assembly 5 thinned to about 00 μm
Is completed.

By cutting the semiconductor package assembly 5 thus manufactured between the semiconductor packages, a thin semiconductor package can be obtained as in the first embodiment. The three-dimensional mounted thin semiconductor package 3 is obtained.

[0044]

As described above, according to the present invention,
Provided are a semiconductor package assembly for manufacturing a thin package by three-dimensional mounting without using a thin wafer and a thin chip, a method for manufacturing the same, and a method for manufacturing a thin semiconductor package using the semiconductor package assembly. .

[Brief description of the drawings]

FIG. 1 is a perspective view showing the appearance of a semiconductor package assembly according to the present invention.

FIG. 2 is a sectional view showing an internal structure of the semiconductor package assembly having the appearance shown in FIG. 1 in which beam lead connection according to the first embodiment is performed.

FIG. 3 is a sectional view showing a manufacturing process of the semiconductor package assembly according to the first embodiment having the external appearance shown in FIG. 1 and the internal structure shown in FIG. 2;

FIG. 4 shows (1) a single semiconductor package obtained by cutting the semiconductor package assembly according to the first embodiment shown in FIGS. 1 and 2, and (2) a single semiconductor package having a plurality of layers. FIG. 3 is a cross-sectional view showing a three-dimensionally mounted semiconductor package stacked on the substrate.

FIG. 5 is a cross-sectional view illustrating an internal structure of the semiconductor package assembly having the appearance illustrated in FIG. 1 in which wire bond connection according to the second embodiment is performed.

FIG. 6 is a cross-sectional view showing a manufacturing process of the semiconductor package assembly according to the second embodiment having the appearance shown in FIG. 1 and the internal structure shown in FIG. 5;

FIG. 7 is a cross-sectional view illustrating an internal structure of the semiconductor package assembly having the appearance illustrated in FIG. 1 in which bump connection according to the third embodiment is performed.

FIG. 8 is a cross-sectional view showing a manufacturing process of the semiconductor package assembly according to the third embodiment having the external appearance shown in FIG. 1 and the internal structure shown in FIG. 7;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor package aggregate 2 ... Semiconductor package (single unit) 3 ... Three-dimensional mounting semiconductor package 4 ... Semiconductor package aggregate 5 ... Semiconductor package aggregate 10 ... Insulating tape base material 10S ... Top surface of insulating tape base material 10R ... lower surface of insulating tape base material 10H ... through-hole (for connecting semiconductor chip and wiring pattern) 10T ... through-hole (for forming conductive pillar 15A) 10Q ... through-hole (for forming lower connection terminal 21) 11 ... Semiconductor chip 11S: Back surface of semiconductor chip 11 11S ₀ : Back surface of semiconductor chip 11 before grinding and polishing (original back surface) 12: Semiconductor package 13A: Sealing resin layer 13B: Sealing resin layer 13S: Sealing resin layer 13A of the upper surface 13S ₀ ... ground and polished prior to the upper surface of the encapsulating resin layer 13A (the original upper surface) 14 ... wiring pattern 14M ... beam lead 15 Upper connection terminal 15 15A: conductor pillar (lower half of upper connection terminal 15) 15B: conductor ball (upper half of upper connection terminal 15) 16: external connection terminal 17: bonding wire 18: solder resist layer 19: lower connection Terminal 20: Bump 21: Upper connection terminal 22: Lower connection terminal

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Tomio Nagaoka Nagano Prefecture, Nagano-shi, Kurita-sha, 711 Toda, Shinko Electric Industries, Ltd. F term (reference) 5F061 AA01 BA05 CA10 CB13

Claims (5)

[Claims] A semiconductor package including a plurality of semiconductor chips is formed on an insulating tape base material having the same planar shape as a semiconductor wafer and having a wiring pattern on an upper surface or a lower surface. The active surface is adhered to the upper surface of the insulating tape substrate with the surface facing downward, the periphery is sealed with a sealing resin layer, and electrically connected to the wiring pattern of the insulating tape substrate. A semiconductor package assembly, wherein a back surface of the semiconductor chip is ground and polished together with the sealing resin layer so as to be flush with an upper surface of the sealing resin layer. 2. The semiconductor package according to claim 1, wherein the semiconductor chip and the wiring pattern of the insulating tape base are electrically connected by a beam lead, a bonding wire, or a bump. Aggregation. 3. The following step: a large number of semiconductor chips having an active surface facing down on the upper surface of an insulating tape substrate having the same planar shape as the semiconductor wafer and having a wiring pattern on the upper surface or lower surface. Bonding the semiconductor chip to the wiring pattern of the insulating tape substrate, forming a sealing resin layer that covers the periphery and the back surface of the semiconductor chip, The sealing resin layer is ground and polished from the upper surface of the sealing resin layer to below the back surface of the semiconductor chip to make the semiconductor chip thinner, and a new back surface of the semiconductor chip and the sealing resin layer Making the new upper surface coplanar with the new upper surface of the semiconductor package assembly. 4. The semiconductor package assembly according to claim 3, wherein said semiconductor chip is electrically connected to said wiring pattern of said insulating tape base material by a beam lead, a bonding wire, or a bump. Production method. 5. A method of manufacturing a semiconductor package, comprising a step of cutting the plurality of semiconductor packages individually by cutting the semiconductor package assembly according to claim 1 between the semiconductor packages. Method.