JP2002318723A - Cache controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a cache controller for accelerating the operating speed of a cache by preventing delay in the generation of an address to be inputted to the cache. SOLUTION: This cache controller is provided with a first register for holding address data, a second register for holding the address data held in the first register at next timing, a cache for receiving the address data, a comparator for receiving the output of the first and second registers, a first multiplexer for selecting the data of the comparator, a second multiplexer for selecting the data of the cache and an access controller for controlling the cache, and has a plurality of ways which do not confirm coincidence simultaneously to finish the selection of an address bus prior to comare the respective ways.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a cache control device, and more particularly, to a cache control device used as a set associative cache control device.

[0002]

2. Description of the Related Art In recent years, the operating frequency of general-purpose microcomputers and digital signal processors (hereinafter abbreviated as DSP) has been increased, and the operating frequencies of cache devices used for these have also been increased.

It is well known that, among the cache devices described above, set associative caches have recently been used for improving the cache hit rate, and have attracted attention. Such a conventional cache device is disclosed in, for example, JP-A-8-263370.

[0004] This set associative cash
Generally, the cache hit rate is improved as compared with a direct map cache having the same capacity.

Further, with the miniaturization of the latest semiconductor manufacturing process, the bus speed of the external storage of the general-purpose microcomputer or the DSP and the operation speed inside the processor are increasing. That is, the rate at which the hit rate of the cache memory inside the processor affects the performance of the entire processor increases.

It is expected that the use of the set associative system will increase more than the direct map system in order to improve the cache hit ratio in the future, but low power consumption measures are also required in order to use the processor for mobile terminals. .

In order to meet this demand, instead of comparing the ways of the set associative cache at the same time, for example, an existing set associative cache which first compares the way 0 and compares the remaining ways when the two do not match. Techniques are also well known.

FIG. 9 shows a configuration of the existing set associative cache device, and FIG. 10 shows an operation timing chart thereof.

The value of the address bus 80 input to the cache of FIG. 9, which is an existing technology, is not determined before the comparison of the caches, and the selector 82 selects the value of the address bus 1 or the value of the address bus 2. It is supposed to be.

For this reason, when the comparison of way 0 results in a mismatch, the selector 8
At 2, the next address is input as a signal 80 to the ways 1-3.

Then, at time t3 in FIG. 10, an address 80 to be input to the cache is generated.

[0012]

However, the above-mentioned conventional cache control device has the following problems.

That is, there is a disadvantage that the generation of the address 80 input to the cache at time t3 is delayed, and the operation speed of the cache is reduced.

A main object of the present invention is to provide a set associative cache having a plurality of ways that do not simultaneously check the coincidence, and to input an address input to the cache RAM of each way to a hit / miss signal generated from a result of comparison of a certain way. Instead of a multiplex method to choose more,
The object of the present invention is to provide a high-speed cache by making a selection in advance before comparing each way.

[0015]

SUMMARY OF THE INVENTION A cache control device according to the present invention has a first address bus connected to its input, a second address bus connected to its output, and a first address bus driven by a clock signal. A register, the second address bus connected to its input, a third address bus connected to its output, a second register driven by a clock signal, and the first address bus connected to its input. A connected first cache, a plurality of second caches having the second address bus connected to its input, and comparing the output of the second address bus with the output of the first cache. A first comparator, a plurality of second comparators for comparing an output of the third address bus with an output of the plurality of second caches, and data of the first and second comparators. No. to choose , A second multiplexer for selecting data of the first and second caches, and an access controller for controlling the first and second caches, the second address bus Prior to comparing the output of the first cache with the output of the first cache, and comparing the output of the third address bus with the output of the plurality of second caches. In this configuration, the selection of the bus is completed in advance.

Further, the first cache of the cache control device of the present invention includes a first tag RAM that receives the first address data, and the second cache stores the second address data. Received second tag RA
M.

Further, the first and second caches of the cache control device of the present invention are configured to include a data RAM controlled by the access controller.

Still further, in another cache control device according to the present invention, the first address bus is connected to its input, the second address bus is connected to its output, and the first register is driven by a clock signal. The second address bus is connected to its input, the third address bus is connected to its output, a second register driven by a clock signal, and the third address bus is connected to its input And
A fourth address bus connected to its output, a third register driven by a clock signal; a first cache having the first address bus connected to its input; and a second cache having the second address bus connected to the input. A second cache connected to the input; a plurality of third caches having the third address bus connected to the input; an output of the second address bus and an output of the first cache; A second comparator for comparing the output of the third address bus with the output of the second cache; a first comparator for comparing the output of the third address bus with the output of the second cache; A plurality of third comparators for comparing the outputs of the first, second and third comparators; a first multiplexer for selecting data of the first, second and third comparators; Third cache data And a second multiplexer to-option,
An access controller for controlling the first, second and third caches, wherein an output of the third address bus is compared with an output of the second address bus and an output of the first cache. Selecting the first to fourth address buses prior to comparing the output of the second cache and comparing the output of the fourth address bus with the outputs of the plurality of third caches; In advance.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A cache control device according to the present invention has a set associative cache configuration, in which an address has been selected for each way prior to comparing an address with a tag RAM.

When the result of the comparison between the address of the tag RAM of a certain way and the address does not match, the address to be used for the comparison of the next way has already been selected.
Comparison with AM can be performed at high speed. As a result, the cache can be operated at high speed.

A cache control device according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a cache control device according to a first embodiment of the present invention, and is an example of a configuration of a 4-way set associative cache.

Referring to FIG. 1, a cache control device 101 according to a first embodiment of the present invention has a first address bus 1 connected to its input and a second address bus 2 connected to its output. , A first register 18 driven by a clock signal, a second address bus 2 connected to its input, a third address bus connected to its output, and a second register 19 driven by a clock signal. And a way 0 cache (21) with the first address bus 1 connected to its input, and a way 1 cache (22) and a way 2 cache (23) with the second address bus 2 connected to its input. And way 3 cache (24), the output of the second address bus 2 and the way 0 cache (2
1), a comparator 26 for comparing the output of the third address bus 3 with the output of the way 1 cache (22), a comparator 26 for comparing the output of the third address bus 3 and the output of the way 2 A comparator 27 for comparing the output of the cache (23), a comparator 28 for comparing the output of the third address bus 3 and the output of the way 3 cache (24), and a comparator (25, 26, 27, 28), a first multiplexer 29 for selecting each data, a data of the way 0 cache (21), a data of the way 1 cache (22), a data of the way 2 cache (23) and a data of the way 3 cache (24). ), A second multiplexer 30 for selecting the data of way 2, a way 0 cache (21), a way 1 cache (22),
3) and an access controller 20 for controlling the way 3 cache (24).
Is compared with the data 4 of the way 0 cache (21), and the output of the third address bus 3 and the way 1 are compared.
Cache (22) data, way 2 cache (2
Prior to comparing the data of 3) with the data of the way 3 cache (24), the selection of the first to third address buses (1, 2, 3) is completed in advance.

Further, the way 0 cache (21)
Tag RAM 21 for receiving data of first address bus 1
a and a data RAM 21b for receiving control data of the access controller 20.

Further, way 1 cache (22)
Is a tag RAM for receiving data on the second address bus 2
22a and a data RAM 22b for receiving control data of the access controller 20.

Further, a way 2 cache (23)
Is a tag RAM for receiving data on the second address bus 2
23a and a data RAM 23b for receiving control data of the access controller 20. The way 3 cache (24) includes a tag RAM 24a for receiving data of the second address bus 2 and a data RAM 24b for receiving control data of the access controller 20. Have.

Then, the cache control device 101 according to the first embodiment of the present invention uses the way 0 cache (21) to reduce power consumption when determining a cache hit / miss.
Tag RAM 21a, tag RAM 22a of way 1 cache (22), tag R of way 2 cache (23)
AM23a, tag RAM of way 3 cache (24)
24a are not compared at the same time, but the tag RAM read from the way 0 cache (21) first is read.
The tag RAM data 4 of the memory 21a is compared with the address 2. If the addresses do not match, the tag RAM data 6 read from the remaining way 1 cache (22) and the tag RAM data read from the way 2 cache (23). The address 3 is compared with the data 8 and the tag RAM data 10 read from the way 3 cache (24).

The output 2 of the register 18 is connected to the address bus 1
Is latched, and contains the address value one clock before the observation reference time. The output 3 of the register 19 latches the value of the address bus 2 and contains the address value two clocks before the observation reference time.

Address bus 1 has way 0 cache (2
Address bus 2 is connected to way 1 cache (22), way 2 cache (23), and way 3
The cache line of the index corresponding to this address is connected to the cache R (24).
It is output as AM data (4, 6, 8, 10) and data RAM data (5, 7, 9, 11).

The way 0 cache (21), way 1 cache (22), and way 2 cache (23)
And the way 3 cache (24) are controlled by the access controller 20, and only the tag RAM and data RAM of the way cache from which the enable signals (31, 32) are output are output.

The data 4 of the tag RAM 21a read from the way 0 cache (21) is supplied to the comparator 27 by the tag RAM 2a read from the way 1 cache (22).
The data 6 of the tag RAM 23a read from the way 2 cache (23) is stored in the comparator 28.
Is input to the comparator 29, the data 10 of the tag RAM 24a read from the way 3 cache (24) is input to the comparator 30, the tag RAM data 4 of the way 0 is compared with the address 2, and the tag RAM data 6 of the way 1 is read. Is compared with address 2 and address 3 and tag RAM data 8 of way 2
Is compared with address 3, and tag RAM data 10 in way 3 is compared with address 3.

The comparison result signals (12, 13, 14, 1)
5) enters the selector 29, and the way of the read cache is selected. As a result of the comparison (signal 16), if there is a hit, it is determined that a cache hit has occurred, and among the output data (5, 7, 9, 11) of the data RAM, the output data of the data RAM of the way selected by the selector 30 is Output from the reference line 17.

If the comparison result (signal 16) indicates a miss, the access controller 20 selects the remaining ways 1 to 3, and repeats the same comparison as described above. As a result, when the hit / miss signal 16 is a miss, it is regarded as a true cache miss.

Next, the operation of the cache control device according to the first embodiment of the present invention will be described. First, way 0
The operation in the case of a cache hit will be described with reference to the configuration example of FIG. 1 and the timing chart of FIG.

At time t1, the access controller 20 asserts the enable signal 31 of way 0, and the address 1 accesses the way 0 of the cache.

At time t2, tag RAM data 4 and data RAM data 5 corresponding to address 1 are output from way 0. Tag RAM data 4 of way 0 output
Enters the comparator 25 and is compared with the address 2 so that the two match. The data RAM data 5 of the way 0 is output from the reference line 17 to the outside.

Next, the operation when a cache hit occurs in any of the ways 1, 2, and 3 will be described with reference to the configuration example of FIG. 1 and the timing chart of FIG.

At time t1, address 1 is accessed to cache way 0, and access controller 20 asserts enable signal 31 for way 0. Time t
In step 2, tag RAM data 4 and data RAM data 5 corresponding to address 1 are output from way 0.

Output tag RAM data 4 of way 0
Enters the comparator 25, is compared with the address 2, the two do not match, and the miss signal 16 is asserted.

The access controller 20 sends way 1,
A few enable signals 32 are asserted and the address 2
Are accessed in ways 1, 2, and 3 of the cache.

At time t3, tag RAM data 6, 8, 10 and data RAM data 7, 9, 11 corresponding to address 2 are output from ways 1, 2, and 3.

The output tag RAMs of ways 1, 2, and 3
Data 6, 8, and 10 are output from comparators 26, 27, and 2 respectively.
8 and is compared with address 3 and one of them matches. The data RAM of the matched way is output from the reference line 17 to the outside.

Next, the operation in the case of a cache miss will be described with reference to the configuration example of FIG. 1 and the timing chart of FIG.

At time t1, the address 1 accesses the cache way 0, and the access controller 20 asserts the enable signal 31 for the way 0.

At time t2, tag RAM data 4 and data RAM data 5 corresponding to address 1 are output from way 0. Tag RAM data 4 of way 0 output
Enters the comparator 25, is compared with the address 2, the two do not match, and the miss signal 16 is asserted.

The access controller 20 sends way 1,
A few enable signals 32 are asserted and the address 2
Are accessed in ways 1, 2, and 3 of the cache.

At time t3, tag RAMs 6, 8, 10 and data RAM data 7, 9, 11 corresponding to the value of address bus 2 are output from ways 1, 2, and 3.

Tag RAMs of ways 1, 2 and 3 output
Data 6, 8, and 10 are output from comparators 26, 27, and 2 respectively.
8 and is compared with the value on the address bus 3 and all of them do not match.

Next, another embodiment of the present invention will be described in detail with reference to the drawings. The cache control device according to the second embodiment of the present invention includes:
The address to be selected is further devised. FIG. 5 shows one configuration and FIG. 6 shows a timing chart.

The cache control device according to the second embodiment of the present invention uses an n-way set associative cache. At time t1, the address bus 1 accesses the cache way 0, and the access controller 20 controls the way 0. The enable signal 31 is asserted.

At time t2, tag RAM data 4 and data RAM data 5 corresponding to the value of address bus 1 are output from way 0. Tag RAM of output way 0
The data 4 enters the comparator 25, is compared with the value of the address bus 2, and when the values do not match, the miss signal 16 is asserted.

The access controller 20 sends ways 1 to
The n-1 enable signal 32 is asserted and the address 2
Are accessed to ways 1 to n-1 of the cache.

At time t3, the tag and data RAM corresponding to address 2 are output from ways 1 to n-1. The output data of the tag RAMs of the ways 1 to n-1 enter the respective comparators and are compared with the values of the address bus 3.

Next, FIG. 7 shows a configuration example of the cache control device according to the third embodiment of the present invention, and FIG. 8 shows a timing chart.

The cache control device according to the third embodiment of the present invention uses an n-way set associative cache, and has a configuration in which a determination of a cache hit / miss is made with a maximum of three clocks.

At time t1, the address bus 1 accesses the cache way 0, and the access controller 20 asserts the enable signal 31 for the way 0.

At time t2, tag RAM data 4 and data RAM data 5 corresponding to the value of address bus 1 are output from way 0. Tag RAM of output way 0
The data 4 enters the comparator 25 and is compared with the value of the address bus 2. When the data 4 does not match, the miss signal 16 is asserted.

The enable signal 61 of the way 1 is asserted by the access controller 20, and the address bus 2 accesses the way 1 of the cache.

At time t3, tag RAM data 6 and data RAM data 7 corresponding to address bus 2 are output from way 1. The output tag RAM data 6 of way 1 enters comparator 26 and is compared with address bus 3.
If the result is a mismatch, the miss signal 16 is asserted. Ways 2 to n from access controller 20
The enable signal 32 of -1 is asserted, and the address bus 3 accesses the cache ways 2 to n-1.

At time t4, tag RAM data and data RAM corresponding to address bus 3 from ways 2 to n-1
Data is output. The output tag RAM data of the ways 2 to n-1 enters the comparators, respectively, and the address bus 5
9 is compared.

In the cache control device according to the embodiment of the present invention, the order of the ways to be compared is changed from the way 0 to the ways 1, 2, and 3, but the comparison may be started from another way.

[0062]

As described above, the effects of the present invention will be described with reference to FIGS. In a set associative cache having a configuration in which comparison of all ways and addresses is not determined at the same time, when the comparison at time t2 results in a mismatch, the address for reading the required cache at time t3 is determined by looking at the miss signal 16. Rather than selecting, the addresses 1, 2, and 3 required for each way are prepared in advance at the time t1, so that the time corresponding to that can be saved. Therefore, the cache can be operated at higher speed.

[Brief description of the drawings]

FIG. 1 is a block diagram of a cache control device according to a first embodiment of this invention.

FIG. 2 is a time chart illustrating an operation of the cache control device according to the first embodiment of this invention.

FIG. 3 is a time chart illustrating a cache hit of the cache control device according to the first embodiment of this invention.

FIG. 4 is a time chart illustrating a cache miss of the cache control device according to the first embodiment of this invention.

FIG. 5 is a block diagram of a cache control device according to a second embodiment of this invention.

FIG. 6 is a time chart illustrating an operation of the cache control device according to the second embodiment of this invention.

FIG. 7 is a block diagram of a cache control device according to a third embodiment of the present invention. F.

FIG. 8 is a time chart illustrating an operation of the cache control device according to the third embodiment of this invention.

FIG. 9 is a block diagram of a conventional cache control device.

FIG. 10 is a time chart for explaining the operation of the conventional cache control device.

[Explanation of symbols]

 1, 2, 3 Address 4, 6, 8, 10 Tag RAM output 5, 7, 9, 11 Data RAM output 17 Reference line 20 Access controller 21, 22, 23, 24 way 21a, 22a, 23a, 24a Tag RAM 21b , 22b, 23b, 24b Data RAM 25, 26, 27, 28 Comparator 29, 30 Multiplexer

Claims (8)

[Claims] A first address bus connected to its input; a second address bus connected to its output; a first register driven by a clock signal; and said second address bus connected to its input. A second register connected to a third address bus connected to its output and driven by a clock signal; a first cache connected to the input of the first address bus; A plurality of second caches each having an address bus connected to its input; a first comparator for comparing an output of the second address bus with an output of the first cache; and a third address. A plurality of second comparators for comparing an output of a bus with an output of the plurality of second caches; a first multiplexer for selecting data of the first and second comparators; 1st and 1st A second multiplexer for selecting data of a cache of the first and second caches; and an access controller for controlling the first and second caches, wherein an output of the second address bus and an output of the first cache are provided. A cache, wherein the first to third address buses are selected in advance before performing the comparison and comparing the output of the third address bus with the output of the plurality of second caches. Control device. 2. The cache control device according to claim 1, wherein the cache control device is a set associative cache device. 3. The first cache includes a first tag RAM receiving the first address data, and the second cache stores a second tag RAM receiving the second address data. The cache control device according to claim 1 or 2, further comprising: 4. The cache control device according to claim 1, wherein the first and second caches include a data RAM controlled by the access controller. 5. The first comparator compares an output of the second address bus with an output of the first tag RAM, and wherein the plurality of second comparators output the third address. 5. The cache control device according to claim 1, wherein an output of a bus is compared with an output of the plurality of second tag RAMs. 6. The cache control device according to claim 1, further comprising: five or more caches. 7. The apparatus according to claim 1, wherein the number of the comparators is five or more.
The cache control device according to 2, 3, 4, or 5. 8. A first register connected to its input, a second address bus connected to its output, a first register driven by a clock signal, and said second address bus connected to its input. A third address bus connected to its output, a second register driven by a clock signal, the third address bus connected to its input, and a fourth address bus connected to its output. A third register connected and driven by a clock signal, a first cache having the first address bus connected to its input, and a second cache having the second address bus connected to its input. A cache; a plurality of third caches having the third address bus connected to an input thereof; and a first comparison comparing an output of the second address bus and an output of the first cache. A second comparator for comparing the output of the third address bus with the output of the second cache; and the output of the fourth address bus and the outputs of the plurality of third caches. A plurality of third comparators for comparison; a first multiplexer for selecting data of the first, second, and third comparators; and a data of the first, second, and third caches. A second multiplexer to be selected; and an access controller controlling the first, second, and third caches, and comparing an output of the second address bus with an output of the first cache. Prior to comparing the output of the third address bus with the output of the second cache, and comparing the output of the fourth address bus with the outputs of the plurality of third caches. 1st through Cache controller, wherein the dispense 4 of the selection of the address bus in advance.